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3rd International conference on Autonomic computing, ICAC 2006

作者： Agarwala, Sandip Chen, Yuan Milojicic, Dejan Schwan, Karsten College of Computing Georgia Institute of Technology Atlanta GA 30332 Hewlett Packard Labs. 1501 Page Mill Road Palo Alto CA 94304

ISBN: (纸本)1424401755

The scale, reliability, and cost requirements of enterprise data centers require automation of center management. Examples include provisioning, scheduling, capacity planning, logging and auditing. A key component of such automation functions is online monitoring. In contrast to monitoring systems designed for human users, a particular concern for online enterprise monitoring is Quality of Service (QoS). Since breaking service level agreements (SLAs) has direct financial and legal implications, enterprise monitoring must be conducted so as to maintain SLAs. This includes the ability to differentiate the QoS of monitoring itself for different classes of users or more generally, for software components subject to different SLAs. Thus, without embedding notions of QoS into the monitoring systems used in next generation data centers, it will not be possible to accomplish the desired automation of their operation. This paper both demonstrates the importance of QoS in monitoring, and it presents a QoS-capable monitoring system, termed QMON. QMON supports utility-aware monitoring while also able to differentiate between different classes of monitoring, corresponding to classes of SLAs. The implementation of QMON offers high levels of predictability for service delivery (i.e., predictable performance), and it is dynamically configurable to deal with changes in enterprise needs or variations in services and applications. We demonstrate the importance of QoS in monitoring and the QoS capabilities of QMON in a series of case studies and experiments, using a multi-tier web service benchmark. © 2006 IEEE.

关键词： Real time control

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An automatic approach to displaying web applications as Portlets 3rd

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3rd International conference on Distributed computing and Internet technology, ICDCIT 2006

作者： Bellas, Fernando Paz, Iñaki Pan, Alberto Díaz, Óscar Carneiro, Víctor Cacheda, Fidel Department of Information and Communications Technologies University of A Coruña A Coruña15071 Spain ONEKIN Research Group University of the Basque Country San Sebastián20018 Spain

ISBN: (纸本)9783540683797

Wrapping existing Web applications into portals allows to protect investment and improves user experience. Most current portlet-based portal servers provide a bridge portlet that allows to "portletize" a single Web page, that is, wrapping the whole page or a set of regions as a portlet. They use an annotation-based approach to specifying the page’s regions that must be extracted. This approach does not scale well when a whole application is to be portletized, since it requires to manually annotate each page. This paper describes the design of a bridge portlet that automatically adapts pages according to the space available in the portlet’s window. The bridge portlet delegates page adaptation to a framework that uses a chain of user-configurable "transformers". Each transformer implements an automatic page adaptation technique. Experiments show that our approach is effective. © Springer-Verlag Berlin Heidelberg 2006.

关键词： Portals

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Warp processors

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2006年第3期11卷 659-681页

作者： Lysecky, Roman Stitt, Greg Vahid, Frank Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA USA

We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions, reimplements those regions as a custom hardware circuit in the FPGA, and replaces the software region by a call to the new hardware implementation of that region. While not all benchmarks can be improved using warp processing, many can, and the improvements are dramatically better than those achievable by more traditional architecture improvements. The hardest part of warp processing is that of dynamically reimplementing code regions on an FPGA, requiring partitioning, decompilation, synthesis, placement, and routing tools, all having to execute with minimal computation time and data memory so as to coexist on chip with the main processor. We describe the results of developing our warp processor. We developed a custom FPGA fabric specifically designed to enable lean place and route tools, and we developed extremely fast and efficient versions of partitioning, decompilation, synthesis, technology mapping, placement, and routing. Warp processors achieve overall application speedups of 6.3X with energy savings of 66% across a set of embedded benchmark applications. We further show that our tools utilize acceptably small amounts of computation and memory which are far less than traditional tools. Our work illustrates the feasibility and potential of warp processing, and we can foresee the possibility of warp processing becoming a feature in a variety of computing domains, including desktop, server, and embedded applications.

关键词： design experimentation performance warp processors hardware/software partitioning FPGA configurable logic just-in-time (JIT) compilation dynamic optimization hardware/software codesign

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Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems

Multi-objective Optimal Controller Synthesis for Heterogeneo...

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International conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS)

作者： Lech Jozwiak Dominik Gawlowski Aleksander Slusarczyk Faculty of Electrical Engineering Eindhoven University of Technology MB Eindhoven The Netherlands

The recent spectacular progress in modern microelectronics created a big stimulus towards development of mobile, autonomous, embedded and re-configurable systems, but also resulted in many difficult to solve issues, as power and energy crisis or increased leakage power, that are especially serious for this sort of systems. What prevents the (re-)configurable heterogeneous embedded systems from becoming one of the main practically used paradigms is mainly inadequate support of the development methodologies and EDA-tools for efficient mapping of applications and producing power, energy, and speed optimized systems. As a part of our research that aims at development of effective methods and EDA-tools for the heterogeneous (re-)configurable embedded system synthesis, we performed a comparative analysis of several representative commercial and academic synthesis methods and tools for the FPGA-targeted controller synthesis. In this paper, the automatic hardware synthesis for the heterogeneous embedded systems is considered, when focusing on the efficient multi-objective controller synthesis. In particular, a part of results and conclusions from our analysis, and effective solutions of some problems observed are discussed

关键词： Optimal control Control system synthesis Embedded system Microelectronics Hardware CMOS technology Automatic control Physics computing Computer architecture Appropriate technology

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Digital library and Distance Learning Web service based Middleware: Specifications and applications

Digital library and Distance Learning Web service based Midd...

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International conference on Information and Communication Technologies: From Theory to applications, ICTTA

作者： H. Kashfi M.R. Razzazi CEIT Department Islamic Azad University of Qazvin Qazvin Iran CEIT Department Amirkabir University of Technology슠 Tehran Iran

Efforts for next generation digital library and e-learning architectures are aiming for a transition from these systems as integrated, centrally controlled systems to dynamic configurable federation of library and educational services and information collections. So, developers adapt their systems to novel technology trends and developments including technologies like Web services and the grid as well as the success of new paradigms like peer-to-peer networking; and also, service oriented architectures. Systems have major drawbacks because of their limitations in scalability, availability, distribution of computing power and storage system, as well as sharing information between users that contribute in these systems. Proposing a grid DLEL middleware, we described how some new technologies including agent, Web service and grid and emerging standards can be applied to digital library and e-learning

关键词： Software libraries Computer aided instruction Web services Middleware Electronic learning Centralized control Control systems Peer to peer computing Service oriented architecture Scalability

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Optimizing the Design of a configurable Digital Signal Processor for Accelerated Execution of the 2-D Discrete Cosine Transform

Optimizing the Design of a Configurable Digital Signal Proce...

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Annual Hawaii International conference on System Sciences (HICSS)

作者： C. Gloster Jr. W. Gay M. Amoo M. Chouikha Department of Electrical and Computer Engineering Howard University College of Medicine Washington D.C. DC USA

The advance of mobile electronics technology has produced handheld appliances allowing both wireless voice and data communications. As data communications become increasingly important in mobile computing applications, traditional microprocessors and the accompanying software are increasingly less able to meet the size constraints of these applications while delivering increased performance. One of the most important operations in the realm of digital signal and image processing is the 2-D Discrete Cosine Transform, used to compress both still images and streaming video. The BISON configurable Digital Signal Processor(BCDSP) architecture detailed here uses multiple memories, few instructions, and a special pipelined floating point arithmetic function core to run on a commercially available Field Programmable Gate Array(FPGA) board. The results demonstrate that although the clock speed of the FPGA board was 2 orders of magnitude slower than the microprocessor used in this study, the BCDSP implementation was still significantly faster.

关键词： Design optimization Signal design Digital signal processors Acceleration Discrete cosine transforms Data communication Application software Microprocessors Signal processing Field programmable gate arrays

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QMON: QoS- and Utility-Aware Monitoring in Enterprise Systems

QMON: QoS- and Utility-Aware Monitoring in Enterprise System...

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International conference on Autonomic computing (ICAC)

作者： S. Agarwala Yuan Chen D. Milojicic K. Schwan College of Computing Georgia Institute of Technology Atlanta GA USA Hewlett Packard Labs Palo Alto CA

The scale, reliability and cost requirements of enterprise data centers require automation of center management. Examples include provisioning, scheduling, capacity planning, logging and auditing. A key component of such automation functions is online monitoring. In contrast to monitoring systems designed for human users, a particular concern for online enterprise monitoring is Quality of Service (QoS). Since breaking service level agreements (SLAs) has direct financial and legal implications, enterprise monitoring must be conducted so as to maintain SLAs. This includes the ability to differentiate the QoS of monitoring itself for different classes of users or more generally, for software components subject to different SLAs. Thus, without embedding notions of QoS into the monitoring systems used in next generation data centers, it will not be possible to accomplish the desired automation of their operation. This paper both demonstrates the importance of QoS in monitoring and it presents a QoS-capable monitoring system, termed QMON. QMON supports utility-aware monitoring while also able to differentiate between different classes of monitoring, corresponding to classes of SLAs. The implementation of QMON offers high levels of predictability for service delivery (i.e., predictable performance) and it is dynamically configurable to deal with changes in enterprise needs or variations in services and applications. We demonstrate the importance of QoS in monitoring and the QoS capabilities of QMON in a series of case studies and experiments, using a multi-tier web service benchmark.

关键词： Quality of service Automation Resource management Computerized monitoring Web services Control systems Educational institutions Milling machines Costs technology management

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Multichat: Persistent, Text-As-You-Type Messaging in a Web Browser for Fluid Multi-Person Interaction and Collaboration

Multichat: Persistent, Text-As-You-Type Messaging in a Web B...

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Annual Hawaii International conference on System Sciences (HICSS)

作者： J. Schull M. Axelrod L. Quinsland Rochester Institute of Technology Rochester NY USA

To facilitate face to face conversation between deaf and hearing participants, we created a cross-platform, browser-based, persistent text-as-you-type system that aggregates each individual's utterances in revisable personal notes on a user-configurable multi-person workspace in a common web browser. The system increases the fluidity of real time interaction, makes it easier to keep track of an individual's contributions over time, and allows users to format their contributions and customize their displays. Because the system affords "full duplex" parallel communication in a web browser, it supports new patterns of interaction and new possibilities for dynamic browser-based visual representations of temporal patterns of communication. Furthermore, the near-real-time-architectures we are exploring seem to open the way to a family of centralized and peer-to-peer persistent conversation applications such as real-time wikis, collaborative web design systems, collaborative web-surfing applications, and an in-class discussion systems.

关键词： Collaboration Real time systems Collaborative work Deafness Auditory system Aggregates Displays Fluid dynamics Peer to peer computing Web design

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S5: The architecture and development flow of a software configurable processor

S5: The architecture and development flow of a software conf...

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4th IEEE International conference on Field Programmable technology

作者： Arnold, JM Stretch Inc Mountain View CA USA

ISBN: (纸本)0780394070

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a program in able Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

关键词： reconfigurable architectures software configurable processor instruction set extension embedded computing

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Powerful computing system for imaging applications on a whole semiconductor wafer

Powerful computing system for imaging applications on a whol...

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2005 Beijing International conference on Imaging: technology and applications for the 21st Century

作者： Lutsyk, Andriy Shmoylov, Volodymyr Lutsyk, Oleksiy Institute of Physics and Mechanics Institute of Applied Problems of Mechanics and Mathematics Ivan Franko National University of Lviv Lviv Ukraine Institute of Physics and Mechanics Lviv Ukraine Ukrainian Association of Signal Processing and Pattern Recognition

The homogeneous computing structure of new generation to be called a pulsating information array (Pulsyr) is considered in the paper. The main feature of the Pulsyrs is that they are oriented not on a chip, but on a wafer, the silicon semiconductor plate of diameter to 300 mm. The Pulsyrs are regarded as the base for implementation of high throughput configurable computing systems for different purposes and, in particularly, for image and video processing.

关键词： WSI circuits

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