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检索条件"任意字段=Conference on Configurable Computing - Technology and Applications"

共 333 条记录，以下是311-320 订阅

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Computer vision application on RIPP10 configurable platform using DIPSA modular architecture

Computer vision application on RIPP10 configurable platform ...

引用

conference on configurable computing - technology and applications

作者： Benitez, D Univ Las Palmas GC Dpto Informat & Sistemas Las Palmas Gran Canaria 35017 Spain

ISBN: (纸本)0819429872

Many vision tasks have stringent latency, throughput requirements, and real-time processing demand for greater parallelism. This paper describes a real-time Computer-Vision application that has been developed on a reconfigurable platform called RIPP10 from Altera. We use our simple, modular, reconfigurable and parallel specialized architecture called DIPSA. We analyze and quantify performance requirements demanded by an Automatic Target Recognition and Tracking algorithm and then propose a partitioning of the algorithm into DIPSA modules to achieve frame rate processing. Results of this implementation are used for addressing some issues that benefit and limit configurable computing systems.

关键词： computer architecture FPGA/CPLD real-time imaging computer vision

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Rapid implementation of mathematical and DSP algorithms in configurable computing devices

Rapid implementation of mathematical and DSP algorithms in c...

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conference on configurable computing - technology and applications

作者： Fiore, PD Myers, CS Smith, JM Pauer, EK Lockheed Martin Co Sanders Nashua NH USA

ISBN: (纸本)0819429872

Many real-time DSP applications can benefit from the use of FPGA or adaptive computing devices because these devices provide very high throughput for a small hardware cost. This efficiency comes with a price: it is very time consuming to actually program complicated algorithms in these devices. We have developed a new method of performing this implementation process, providing for an order of magnitude reduction in design time. Our approach consists of an interactive algorithm development tool closely coupled to a set of FPGA devices. From an algorithm script, the tool derives a hardware design, which includes the data path, host interlace, custom sequencer, and address generators. The design is loaded and executed in the FPGA whenever a call far the function is encountered in the algorithm script. Pieces of the algorithm may he ported incrementally;the algorithm will always execute properly, regardless of the state of porting from software to hardware. This approach is optimized to allow mathematicians, generally unskilled in efficient hardware algorithm design. to directly implement algorithms in FPGAs. This enables designers to quickly sec the effect of algorithmic changes and approximations on hardware efficiency, reducing the number and time of design iterations. We are currently porting our approach to the publicly available Ptolemy environment, which will facilitate the transfer of this methodology to the adaptive computing community.

关键词： FPGA DSP adaptive computing configurable computing rapid development Ptolemy

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Hardware/software codesign of a Fuzzy ART neural clusterer: the benefits of configurable computing

Hardware/software codesign of a Fuzzy ART neural clusterer: ...

引用

conference on configurable computing - technology and applications

作者： Poire, P Savaria, Y Daniel, W Cantin, MA Blaquiere, Y Ecole Polytech Dept Elect & Comp Engn Montreal PQ H3C 3A7 Canada

ISBN: (纸本)0819429872

This paper analyzes the performance differences found between software and hardware/sofware implementations of a reformulated Fuzzy ART neural network algorithm. This reformulated algorithm is a solution for a real time radar signal clustering problem. The software implementations run on a 50MHz TMS320C40 DSP, and the hardware/sofware implementation runs on the same DSP for its software part, whereas the FPGA based application specific hardware accelerator is realized on the MiroTech's X-CIM TIM40 module. This investigation of FPGA based acceleration gave excellent re suits for our application: acceleration factors up to 68.9 have been reached.

关键词： neural network clusterer fuzzy ART codesign FPGA

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Using the KressArray for reconfigurable computing

Using the KressArray for reconfigurable computing

引用

conference on configurable computing - technology and applications

作者： Hartenstein, R Herz, M Hoffmann, T Nageldinger, U Univ Kaiserslautern D-67663 Kaiserslautern Germany

ISBN: (纸本)0819429872

Multimedia applications commonly require high computation power mostly in conjunction with high data throughput. As an additional challenge, such applications are increasingly used in handheld devices, where also small package outlines and low power aspects are important. Many research approaches have shown, that accelerators based on reconfigurable hardware can satisfy those performance demands. Most of these approaches use commercial fine-grained FPGAs to implement reconfigurable accelerators. However, it has shown, that these devices are not always well suited for reconfigurable computing. The drawbacks here are the area-inefficiency and the insufficiency of the available design-tools. Besides the fine-grained FPGAs, coarse-grained reconfigurable architectures have been developed, which are more area efficient and better suited for computational purposes. In this paper, an implementation of such an architecture, the KressArray, is introduced and its use in the Map-oriented Machine with Parallel Data Access (MoM-PDA) is shown. The MoM-PDA is an FPGA-based custom computing machine, which is able to perform concurrent memory accesses by means of a dedicated memory organization scheme. The benefits of this architecture are illustrated by an application example.

关键词： reconfigurable computing parallel data access coarse grained reconfigurable architectures KressArray accelerators Xputer image processing

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Using delayed addition techniques to accelerate integer and floating-point calculations in configurable hardware

Using delayed addition techniques to accelerate integer and ...

引用

conference on configurable computing - technology and applications

作者： Luo, Z Martonosi, M Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)0819429872

This paper proposes and evaluates an approach for improving the performance of arithmetic calculations via delayed addition. Our approach employs the idea used in Wallace trees to delay addition until the end of a repeated calculation such as accumulation or dot-product;this effectively removes carry propagation overhead from the calculation's critical path. We present integer and floating-point designs that use this technique. Our pipelined integer multiply-accumulate (MAC) design is based an a fairly traditional multiplier design, but with delayed addition as well. This design achieves a 37MHz clock rare on an XC4036XL-2 FPGA. Next, we present a 32-bit floating-point accumulator based apr delayed addition. Here delayed addition requires a novel alignment technique that decouples the incoming operands from the accumulated result. A conservative version of this design achieves a 33 MHz clock rate. Finally, we also present a more aggressive 32-bit floating-point accumulator design that achieves a 66MHz clock rate. These designs demonstrate the utility of delayed addition for accelerating FPGA calculations in both the integer and floating-point domains.

关键词： Field programmable gate arrays

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Spatial and color clustering on an FPGA-based computer system

Spatial and color clustering on an FPGA-based computer syste...

引用

conference on configurable computing - technology and applications

作者： Leeser, M Kitaryeva, N Crisman, J Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

ISBN: (纸本)0819429872

We are mapping an image clustering algorithm onto an FPGA-based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

关键词： image processing computer vision digital library search image analysis FPGA computing systems configurable hardware

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Dynamically Programmable Cache

Dynamically Programmable Cache

引用

conference on configurable computing - technology and applications

作者： Nakkar, M Harding, J Schwartz, D Franzon, P Conte, T N Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)0819429872

Reconfigurable machines have recently been used as co-processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: 1) the small on-chip memory which results in slower execution time, and 2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory accesses problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implement multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X raster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).

关键词： reconfigurable computing FPGA embedded processors Data Cache convolution motion estimation

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ILI: an adaptive infrastructure for dynamic interactive distributed applications

ILI: an adaptive infrastructure for dynamic interactive dist...

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Proceedings of International Workshop on configurable Distributed Systems

作者： V. Martin K. Schwan College of Computing Georgia Institute of Technology Atlanta GA USA

Addresses the middleware that is necessary to realize the construction of distributed laboratories in which scientists can construct and use complex computations and then analyze and share their results across geographically separated collaborations. We present a model of such middleware for heterogeneous distributed computing platforms and also show how middleware can dynamically adapt to changes in the behavior of instruments and end users. To address the demands of applications executing in a distributed laboratory, we have developed an infrastructure, called ILI (Interactivity Layer Infrastructure), that can dynamically adapt to changes in the behavior of the computational instruments and end users across a shared and dynamically changing set of computational nodes and networks.

关键词： Laboratories Instruments Microwave integrated circuits Computer networks Atmospheric modeling Engines Educational institutions Postal services Electronic switching systems Reactive power

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Payoff-based communication adaptation based on network service availability

Payoff-based communication adaptation based on network servi...

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IEEE International conference on Multimedia computing and Systems (ICMCS)

作者： R. Kravets K. Calvert K. Schwan College of Computing Georgia Institute of Technology GA USA

Interactive applications will continue to push the limits of available network bandwidths, processing speeds, and other computing resources. These applications present challenges concerning the specification of service requirements for their multiple types of data transfer and the online management of service quality. We present a cooperative solution in which a configurable communication layer is used to adapt communication in response to both application requirements and network resource availability. Adaptation decisions are based on: (1) payoff functions which capture the requirements of the application in a functional form, and (2) service availability curves which represent network resource availability. Experimentation with representative multimedia applications demonstrates the benefit of using such payoff based adaptation.

关键词： Availability Electrical capacitance tomography Microwave integrated circuits Educational institutions Bandwidth Quality management Fluctuations Resource management Virtual environment

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Development of a distributed object-oriented system framework for the computer-integrated manufacturing execution system

Development of a distributed object-oriented system framewor...

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IEEE International conference on Robotics and Automation (ICRA)

作者： Fan-Tien Cheng E. Shen Jun-Yan Deng K. Nguyen Institute of Manufacturing Engineering National Cheng Kung University Tainan Taiwan Mitta Technology Group Inc. Sunnyvale CA USA

Today, most of the manufacturing execution systems (MES) are large, monolithic, insufficiently configurable and difficult to modify. Using a distributed object-oriented technique, we present a systematic approach to develop a computer-integrated MES framework which is open, modularised, distributed, configurable, interoperable, collaborative, and maintainable. The CORBA infrastructure is adopted to develop this integratable MES. We also use OLE automation and COM objects to construct sample applications. An example is shown to demonstrate the fruit of this systematic approach.

关键词： Computer aided manufacturing Distributed computing Job shop scheduling Manufacturing processes System testing Integrated circuit packaging Production facilities Computer integrated manufacturing Maintenance engineering Manufacturing automation

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