In the past, ad-hoc and manual testing of infrared imagers has not been a deterrent to the characterization of these systems due to the low volume of production and high ratio of skilled personnel to the quantity of u...
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In the past, ad-hoc and manual testing of infrared imagers has not been a deterrent to the characterization of these systems due to the low volume of production and high ratio of skilled personnel to the quantity of units under test. However, with higher volume production, increasing numbers of development labs in emerging markets, and the push towards less expensive, faster development cycles, there is a strong need for standardized testing that is quickly configurable by test engineers, which can be run by less experienced test technicians and which produce repeatable, accurate results. The IRWindows/sup TM/ system addresses these needs using a standard computing platform and existing automated IR test equipment. This paper looks at the general capabilities of the IRWindows/sup TM/ system, and then examines the specific results from its application in the PalmIR and Automotive IR production environments.
configurablecomputing is an area of active research that has sprung up over the last several years. By combining aspects of traditional computing, such as high performance microprocessor and commodity memory devices,...
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ISBN:
(纸本)0818677430
configurablecomputing is an area of active research that has sprung up over the last several years. By combining aspects of traditional computing, such as high performance microprocessor and commodity memory devices, with programmable hardware devices, configurablecomputing attempts to gain the benefits of both adaptive software and optimized hardware. Different types of configurablecomputing systems that have been either proposed of developed are discussed, along with their applications and the issues in tool design.
configurablecomputing has captured the imagination of many architects who want the performance of application-specific hardware combined with the flexibility of general-purpose computers. Despite the efforts of many ...
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ISBN:
(纸本)0818677430
configurablecomputing has captured the imagination of many architects who want the performance of application-specific hardware combined with the flexibility of general-purpose computers. Despite the efforts of many research groups over the past decade, successes have been rare because the configurable computers, so far, exhibit poor cost performance for most applications. And they are also notoriously hard to program. Future progress in configurable computers will result not from continued research along the same field programmable gate array-based path, but from a diversity of approaches including more coarse-grained configurable architectures and constrained programming models that allow more powerful compilation techniques.
Prior to the introduction of guard systems for electronic mail, guards tended to be overly specialized and not versatile enough for today's user community. This paper examines the use of Type Enforcement to create...
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Prior to the introduction of guard systems for electronic mail, guards tended to be overly specialized and not versatile enough for today's user community. This paper examines the use of Type Enforcement to create a highly assured yet administrator configurable guard. The administrator must be able to trust that the configuration provided will indeed be followed. This occurs by using highly assured or trusted components. These trusted components are then linked together via Type Enforcement to form a pipeline, with one input channel for data to enter the guard, and one separate, connected output channel for data to exit the guard. These channels are connected via assured processes whose behavior is restricted by the Type Enforcement mechanism. Furthermore, Type Enforcement is also used to isolate many components of the guard, which simplifies the assurance arguments. This technology is applied in the latest operational guards developed by Secure computing Corporation.
When evaluating architectural and packaging options for an architecture, one commonly encounters the problem of meeting performance requirements within the constraints of weight, volume and power envelope as well as t...
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ISBN:
(纸本)0818677430
When evaluating architectural and packaging options for an architecture, one commonly encounters the problem of meeting performance requirements within the constraints of weight, volume and power envelope as well as the amount of computation performance that can be realized with a given physical envelope. This assessment process can be guided by a metric to be relatively consistent in past applications. It incorporates throughput in million operations per second (MOPS), weight in kilograms, and power in watts. The MOPS/(***) ratio has been used to evaluate technology and packaging tradeoffs.
configurablecomputing is an area of active research that has sprung up over the last few years. By combining aspects of traditional computing, such as high performance microprocessor and commodity memory devices, wit...
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configurablecomputing is an area of active research that has sprung up over the last few years. By combining aspects of traditional computing, such as high performance microprocessor and commodity memory devices, with programmable hardware devices, configurablecomputing attempts to gain the benefits of both adaptive software and optimized hardware. Because the field is young it remains ill defined and often either misunderstood or misrepresented. Fortunately there currently exists a small number of applications which show significant improvement through the use of configurablecomputingtechnology, and have sparked much of the interest in the field. The article touches on some of the different types of configurablecomputing systems that have been either proposed or developed and consider applications that seem to be well suited to this approach, and discuss the open issues in tool design.
Summary form only given. configurablecomputing ideas are being explored to design high performance systems for many applications. Devices which provide partial reconfigurability of combinational logic are now in the ...
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Summary form only given. configurablecomputing ideas are being explored to design high performance systems for many applications. Devices which provide partial reconfigurability of combinational logic are now in the market. Future devices which provide dynamic reconfigurability of both combinational logic and interconnection network based on intermediate results promise enormous computational power. To realize the inherent potential of this technology we need algorithmic techniques and tools which exploit the hardware in a non trivial manner. Characteristics of future devices also need to be explored. Current approaches to design configurable solutions are largely based on logic synthesis in which an HDL description is statically compiled onto hardware. Using such an automated synthesis approach is not amenable to designing solutions which analyze the run time behavior of applications and exploit dynamic reconfiguration.
Prior to the introduction of guard systems for electronic mail, guards tended to be overly specialized and not versatile enough for today's user community. The paper examines the use of type enforcement to create ...
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Prior to the introduction of guard systems for electronic mail, guards tended to be overly specialized and not versatile enough for today's user community. The paper examines the use of type enforcement to create a highly assured yet administrator configurable guard. The administrator must be able to trust that the configuration provided will indeed be followed. This occurs by using highly assured or trusted components. These trusted components are then linked together via type enforcement to form a pipeline, with one input channel for data to enter the guard, and one separate, connected output channel for data to exit the guard. These channels are connected via assured processes whose behavior is restricted by the type enforcement mechanism. Furthermore, type enforcement is also used to isolate many components of the guard, which simplifies the assurance arguments. This technology is applied in the latest operational guards developed by the Secure computing Corporation.
Summary form only given. Metrics determine what kind of conclusions may be drawn from benchmark results, and also affect how benchmarks must be performed. The metrics in use in scientific computing benchmarks address ...
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Summary form only given. Metrics determine what kind of conclusions may be drawn from benchmark results, and also affect how benchmarks must be performed. The metrics in use in scientific computing benchmarks address mainly four questions: 1. How can a given algorithm be characterized? 2. How good is an algorithm to solve a problem on a given implementation? 3. How good is a machine across multiple problems? and 4. How effectively does an implementation algorithm combination scale? When evaluating architectural and packaging options for an architecture, one commonly encounters the problem of meeting performance requirements within the constraints of weight, volume and power envelope as well as the amount of computation performance that can be realized with a given physical envelope. This assessment process can be guided by a metric that we have found to be relatively consistent in past applications. It incorporates throughput in million operations per second (MOPS), weight (and implicitly volume) in kilograms, and power in watts. The MOPS/(***) ratio has been used to evaluate technology and packaging tradeoffs.
Over the past decade or more, processor speeds have increased much more quickly than memory speeds. As a result, a large, and still increasing, processor-memory performance gap has formed. Many significant application...
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ISBN:
(纸本)0819423165
Over the past decade or more, processor speeds have increased much more quickly than memory speeds. As a result, a large, and still increasing, processor-memory performance gap has formed. Many significant applications suffer from substantial memory bottlenecks, and their memory performance problems are often either too unusual or extreme to be mitigated by cache memories along. Such specialized performance 'bugs' require specialized solutions, but it is impossible to provide case-by-case memory hierarchies or caching strategies on general-purpose computers. We have investigated the potential of implementing mechanisms like victim caches and prefetch buffers in reconfigurable hardware to improve application memory behavior. Based on technology and commercial trends, our simulation-based studies use a forward-looking model in which configurable logic is located on the CPU chip. Given such assumptions, our results show that the flexibility of being able to specialize configurable hardware to an application's memory referencing behavior more than balances the slightly slower response times of configurable memory hierarchy structures. For our three applications, small, specialized memory hierarchy additions such as victim caches and prefetch buffers can reduce miss rates substantially and can drop total execution times for these programs to between 60 and 80% of their original execution times. Our results also indicate that different memory specializations may be most effective for each application; this highlights the usefulness of configurable memory hierarchies that are specialized on a per-application basis.
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