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检索条件"任意字段=Conference on Configurable Computing - Technology and Applications"

共 333 条记录，以下是51-60 订阅

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Using Type Enforcement to assure a configurable guard

Using Type Enforcement to assure a configurable guard

引用

Proceedings of the 1997 13th Annual Computer Security applications conference, ACSAC

作者： Greve, Paula Hoffman, John Smith, Richard E. Secure Computing Corp Roseville United States

Prior to the introduction of guard systems for electronic mail, guards tended to be overly specialized and not versatile enough for today's user community. This paper examines the use of Type Enforcement to create a highly assured yet administrator configurable guard. The administrator must be able to trust that the configuration provided will indeed be followed. This occurs by using highly assured or trusted components. These trusted components are then linked together via Type Enforcement to form a pipeline, with one input channel for data to enter the guard, and one separate, connected output channel for data to exit the guard. These channels are connected via assured processes whose behavior is restricted by the Type Enforcement mechanism. Furthermore, Type Enforcement is also used to isolate many components of the guard, which simplifies the assurance arguments. This technology is applied in the latest operational guards developed by Secure computing Corporation.

关键词： Security of data

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Performance metrics for configurable computing

Performance metrics for configurable computing

引用

30th Hawaii International conference on System Sciences (HICSS 30)

作者： Spaanenburg, H Honeywell Inc Ctr Technol Minneapolis MN 55418 USA

ISBN: (纸本)0818677430

When evaluating architectural and packaging options for an architecture, one commonly encounters the problem of meeting performance requirements within the constraints of weight, volume and power envelope as well as the amount of computation performance that can be realized with a given physical envelope. This assessment process can be guided by a metric to be relatively consistent in past applications. It incorporates throughput in million operations per second (MOPS), weight in kilograms, and power in watts. The MOPS/(***) ratio has been used to evaluate technology and packaging tradeoffs.

关键词： Computation theory

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A configurable Pruning Gaussian Image Filter for Energy-Efficient Edge Detection 26

A Configurable Pruning Gaussian Image Filter for Energy-Effi...

引用

26th IEEE International conference on Electronics, Circuits and Systems (ICECS)

作者： Soares, Leonardo Bandeira Cesar da Costa, Eduardo Antonio Bampi, Sergio Fed Univ Rio Grande Sul UFRGS Grad Program Microelect Porto Alegre RS Brazil Catholic Univ Pelotas UCPel Grad Program Elect Engn & Comp Pelotas RS Brazil Fed Inst Technol Rio Grande Sul IFRS Rio Grande Brazil

ISBN: (纸本)9781728109961

This paper presents a new configurable pruning Gaussian image filter CMOS architecture to address energy efficiency requirements regarding edge detection applications. Low-energy consumption is key for Internet of Things (IoT) devices. Many emerging IoT applications rely on cameras to extract video or image features by running power-hungry computer vision algorithms. The Gaussian image filter is one of the most compute intensive tasks for pre-processing edge detection techniques which are widely adopted in the computer vision domain. Therefore, our proposed 2D Gaussian filter architecture enables: i) a low power and low area overhead run-time configuration scheme based on clock gating technique to prune the Gaussian filter (GF) window size, and ii) run-time capability to balance the tradeoff between edge detection quality and energy efficiency. Our proposed configurable architecture is synthesized and mapped onto 45 nm technology for an ASIC implementation. Results show that for 6 different run-time profiles our proposed configurable architecture provides power dissipation reduction of up to 64% with multiple levels of edge detection quality, which is assessed by considering the performance conformance metric.

关键词： Gaussian Image filter Edge detection Energy Efficiency Approximate computing Architecture

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EcoGrid: A dynamically configurable object oriented simulation environment for economy-based Grid scheduling algorithms 11

EcoGrid: A dynamically configurable object oriented simulati...

引用

Proceedings of the Fourth Annual ACM Bangalore conference

作者： Mehta, Hemant Kanungo, Priyesh Chandwani, Manohar School of Computer Science and IT Devi Ahilya University Indore India Patel College of Science and Technology Indore India Department of Computer Engineering Institute of Engineering and Technology Devi Ahilya University Indore India

ISBN: (纸本)9781450307505

In this paper, an economy-based Grid simulator named as EcoGrid is presented. EcoGrid is developed as a test-bed for Grid scheduling algorithms that are based on dynamic load balancing. EcoGrid is dynamically configurable. It optimizes the cost of execution of a process and maximizes the profit of a service provider system. As compared to other commonly used Grid simulation tools like GridSim and SimGrid, this simulator provides more enhanced features like configurable, scalable and extensible. This object oriented simulator also supports execution of Java applications. EcoGrid supports simulation of both the economy based and non-economy based scheduling algorithm. Copyright 2011 ACM.

关键词： Grid computing

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Dynamically Programmable Cache

Dynamically Programmable Cache

引用

conference on configurable computing - technology and applications

作者： Nakkar, M Harding, J Schwartz, D Franzon, P Conte, T N Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)0819429872

Reconfigurable machines have recently been used as co-processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: 1) the small on-chip memory which results in slower execution time, and 2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory accesses problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implement multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X raster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).

关键词： reconfigurable computing FPGA embedded processors Data Cache convolution motion estimation

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A configurable context-aware simulator for smart home systems

A configurable context-aware simulator for smart home system...

引用

2011 6th International conference on Pervasive computing and applications, ICPCA 2011

作者： Fu, Qiang Li, Ping Chen, Cai Qi, Lanlan Lu, Yongqiang Yu, Chen Beijing University of Technology Beijing China South Lishilu Clinic PLA Second Artillery Beijing 100045 China

ISBN: (纸本)9781457702082

The development of distributed smart homes is accelerating with the approach of the Pervasive computing era. Heterogeneous devices and network is a significant feature in these smart homes. However, the realization of a real environment is difficult and always takes a long time. It is unrealistic to verify the availability of the entire system and make sure that all devices and applications can work together after finishing the development. In this paper we present a configurable context-aware simulator for distributed smart homes. XML configuration files are used to save information for constructing the home environment, virtual devices and services, simulating context information and testing the OSGi event interaction between devices. This makes the simulator can work under different smart home environment which based on the OSGi framework without modifying any code. And the simulated virtual devices can work with real devices with the help of the simulator. It is easier to provide a complete simulation environment for a device to test and verify during the development process. © 2011 IEEE.

关键词： Simulators

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Service Availability Driven Re-configurable Embedded System Design

Service Availability Driven Re-configurable Embedded System ...

引用

5th International conference on Information Intelligence, Systems, technology and Management

作者： Kumar, Anil Chakarverty, Shampa Patni Comp Syst NSEZ 142 E&FBlock B Noida India NSIT Div Comp Engn New Delhi India

ISBN: (纸本)9783642194221

Introduction of re-configurable hardware into embedded systems has given a new direction to fault tolerant computing. It is now feasible to satisfy the reliability and performance constraints on demanding applications while reducing the overall cost of the system. In order to evaluate the system's performance metrics, the application's specifications are mapped and scheduled to the computing and communication resources and their dynamic reconfiguration capabilities are exploited. Our automated architecture design algorithm explores the design space and selects the optimal architecture which reconfigures itself into partial functional states in such a way that the most important services as perceived by the user are always available. The system availability is evaluated on the basis of Continuous Time Malloy model and user's importance of service availability in partly and fully functional states. Two multi-objective genetic algorithms have been employed for architecture optimization.

关键词： Fault Tolerance Graceful degradation Architecture Optimization Multi-Objective Genetic Algorithm and CTMC

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Classifying Requirements for Variability Optimization in Multi-tenant applications 6

Classifying Requirements for Variability Optimization in Mul...

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6th IEEE International conference on Cloud computing technology and Science (CloudCom)

作者： Saleh, Ahmed I. Fouad, Mohammed A. Abu-Elkheir, Mervat Mansoura Univ Fac Engn Comp & Syst Dept Mansoura Egypt Mansoura Univ Fac Comp & Informat Sci Dept Informat Syst Mansoura Egypt Mansoura Univ Fac Comp & Informat Sci Dept Informat Technol Mansoura Egypt

ISBN: (纸本)9781479940936

Software as a Service (SaaS) providers can serve thousands of customers, which have hundreds of thousands of overlapping requirements, using a single application instance to offer service at a lower price. Even with a potentially large number of customers with varying requirements, a multi tenant application should make co-tenancy transparent to the tenants, which means that every tenant must appear to be the sole owner of the application, to achieve this, a highly configurable multi-tenant solution is needed. In this paper, we analyze variation in multiple tenants' requirements, to propose a classification for multi-tenant application requirements, and implement variability realization techniques depending on requirement levels. Furthermore, we prioritize the tenants' requirements to satisfy as many customer requirements as possible, and provide key guidelines to software architects and developers to implement a configuration layer in a multi-tenancy architecture.

关键词： Requirements Classification Multi-tenancy Variability Multi-tenant Application Architecture

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Assessing The Impact of Timing Errors on HPC applications 19

Assessing The Impact of Timing Errors on HPC Applications

引用

International conference for High Performance computing, Networking, Storage and Analysis (SC)

作者： Chang, Chun-Kai Yin, Wenqi Erez, Mattan Univ Texas Austin Austin TX 78712 USA

ISBN: (数字)9781450362290

ISBN: (纸本)9781450362290

Timing errors are a growing concern for system resilience as technology continues to scale. It is problematic to use low-fidelity errors such as single-bit flips to model realistic timing errors. We address the lack of holistic methodology and tool for evaluating resilience of applications against timing errors. The proposed technique is able to rapidly inject high-fidelity and configurable timing errors to applications at the instruction level. Our implementation has no runtime dependencies on proprietary tools, enabling full parallelism of error injection campaign. Furthermore, because an injection point may not generate an actual error for a particular application run, we propose an acceleration technique to maximize the likelihood of generating errors that contribute to the overall campaign with speedup up to 7X. With our tool, we show that realistic timing errors lead to distinct error profiles from those of radiation-induced errors at both the instruction level and the application level.

关键词： Fault tolerance Runtime High performance computing Computational modeling Parallel processing Timing Resilience Arithmetic

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A configurable FPGA implementation of PEG-based PS-LDPC decoder

A configurable FPGA implementation of PEG-based PS-LDPC deco...

引用

International conference on Pervasive computing, Signal Processing and applications

作者： Wang, Kun Liu, Ning-Qing Sun, Bin Sun, Hao-Wei Communication Research Center Harbin Institute of Technology Harbin China School of Mechanical Science and Engineering Daqing Petroleum Institute Daqing China

ISBN: (纸本)9780769541808

Low-density parity-check (LDPC) codes form an important subclass of error correcting coding techniques, and its implementation has been hot spot of domains such as signal process, magnetic recording or next generation communication for years. This paper proposes a configurable FPGA implementation of Partition-and-Shift LDPC decoder based on Min-Sum algorithm. An MPEG algorithm is introduced to reduce the complexity of searching for closed paths in shift matrix. And a routing paths switch concept is proposed to realize the expected configurability. Benefits of the proposed technique are demonstrated with FPGA design for differently configured PS-LDPC decoders which all achieve a Gbps throughput, low hardware cost and excellent BER performance at 16 iterations. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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