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检索条件"任意字段=Conference on Configurable Computing - Technology and Applications"

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Scalable and Bounded-time Decisions on Edge Device Network using Eclipse Zenoh 28

Scalable and Bounded-time Decisions on Edge Device Network u...

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28th IEEE International conference on Embedded and Real-Time computing Systems and applications (RTCSA)

作者： Shih, Chi-Sheng Lin, Hsiang-Jui Yuan, Yuyuan Kuo, Yi-Hung Liang, Wen-Yew Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan ADLINK Technol Inc Taipei Taiwan

ISBN: (数字)9781665453448

ISBN: (纸本)9781665453448

The enhanced computing platforms, which are on edge networks and used for embedding computing services, enable the processing of sensing data on edge and sharing the data with the peers of interest. Smart factories and autonomous vehicles are two typical examples. However, existing real-time communication protocols have limits on cross-network domains and complex data structures. To resolve the problems above, this work investigates a new distributed data exchange framework, Zenoh. As a unified and transparent middle-ware for devices over heterogeneous networks, Zenoh enables peers in different network domains to exchange messages in real-time by pub/sub data exchange pattern. Furthermore, it provides high flexibility and scalability by configurable end-to-end and hop-to-hop reliability and congestion control QoS profiles. This work proposes a bounded-time decision algorithm by Reliable Broadcast and CRDT based on Zenoh. This work also benchmarks the protocol's capability over cross-domain networks and investigate the overhead of our algorithms implemented on Zenoh. The throughput and latency performance shows the potential for practical communication between robots in factories or autonomous vehicles on roads.

关键词： Concurrent computing Protocols Scalability Stacking Throughput Robot sensing systems Real-time systems

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A Reconfigurable Approximate computing RISC-V Platform for Fault-Tolerant applications 27

A Reconfigurable Approximate Computing RISC-V Platform for F...

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27th Euromicro conference on Digital System Design

作者： Delavari, A. Ghoreishy, F. Shahhoseini, H. S. Mirzakuchaki, S. Iran Univ Sci & Technol Sch Elect Engn Tehran Iran

ISBN: (纸本)9798350380392;9798350380385

The demand for energy-efficient and high-performance embedded systems drives the evolution of new hardware architectures, including concepts like approximate computing. This paper presents a novel reconfigurable embedded platform named "phoeniX", using the standard RISC-V ISA, maximizing energy efficiency while maintaining acceptable application-level accuracy. The platform enables the integration of approximate circuits at the core level with diverse structures, accuracies, and timings without requiring modifications to the core, particularly in the control logic. The platform introduces novel control features, allowing configurable trade-offs between accuracy and energy consumption based on specific application requirements. To evaluate the effectiveness of the platform, experiments were conducted on a set of applications, such as image processing and Dhrystone benchmark. The core with its original execution engine, occupies 0.024mm(2) of area, with average power consumption of 4.23mW at 1.1V operating voltage, average energy-efficiency of 7.85pJ per operation at 620MHz frequency in 45nm CMOS technology. The configurable platform with a highly optimized 3-stage pipelined RV32I(E)M architecture, possesses a DMIPS/MHz of 1.89, and a CPI of 1.13, showcasing remarkable capabilities for an embedded processor.

关键词： Approximate computing Low Power Design RISC-V Embedded Processor Energy-Efficient Computation Very Large Scale Integration

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Using reconfigurable hardware to customize memory hierarchies

Using reconfigurable hardware to customize memory hierarchie...

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conference on High-Speed computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic

作者： Zhong, PX Martonosi, M PRINCETON UNIV DEPT ELECT ENGNPRINCETONNJ 08544

ISBN: (纸本)0819423165

Over the past decade or more, processor speeds have increased much more quickly than memory speeds. As a result, a large, and still increasing, processor-memory performance gap has formed. Many significant applications suffer from substantial memory bottlenecks, and their memory performance problems are often either too unusual or extreme to be mitigated by cache memories along. Such specialized performance 'bugs' require specialized solutions, but it is impossible to provide case-by-case memory hierarchies or caching strategies on general-purpose computers. We have investigated the potential of implementing mechanisms like victim caches and prefetch buffers in reconfigurable hardware to improve application memory behavior. Based on technology and commercial trends, our simulation-based studies use a forward-looking model in which configurable logic is located on the CPU chip. Given such assumptions, our results show that the flexibility of being able to specialize configurable hardware to an application's memory referencing behavior more than balances the slightly slower response times of configurable memory hierarchy structures. For our three applications, small, specialized memory hierarchy additions such as victim caches and prefetch buffers can reduce miss rates substantially and can drop total execution times for these programs to between 60 and 80% of their original execution times. Our results also indicate that different memory specializations may be most effective for each application; this highlights the usefulness of configurable memory hierarchies that are specialized on a per-application basis.

关键词： memory latency configurable computing victim cache prefetching

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CTFS: A configurable Tuning Framework on SHENWEI System 21

CTFS: A Configurable Tuning Framework on SHENWEI System

引用

5th International conference on High Performance Compilation, computing and Communications, HP3C 2021

作者： Wu, Wei Zhu, Qi Wang, Fei Qi, Fengbin Jiangnan Institute of Computing Technology Wuxi214083 China Tsinghua University Beijing100084 China

ISBN: (纸本)9781450389648

Performance tuning faces challenges of the heterogeneousness, complexity and flexibility of the modern processors. Due to the limited knowledge of the underlining architecture, users are usually confused about which optimizing should be enabled to speed up their applications on the target processor. In this paper, a configurable tuning framework, CTFS, is proposed to probe the compiler options automatically to optimize programs on SHENWEI system. Tightly coupling with the system software of the SHENWEI family processors, CTFS provides flexible iterative target supports and configurable iterative progress, which dramatically improvement user-friendliness of the computer systems built on SHENWEI family processors. The evaluation shows that with the help of CTFS, the performance of the SWDNN cases can be improved about 9% on average compared with the-O3 optimizing level. A case study of a real-world application, Graph500, which is speeded up by 27% with the help of CTFS. © 2021 ACM.

关键词： Program compilers

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Design of precision configurable multiply accumulate unit for neural network accelerator

Design of precision configurable multiply accumulate unit fo...

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2022 International conference on Artificial Intelligence, Internet of Things and Cloud computing technology, AIoTC 2022

作者： Chen, Jian Zhou, Xinru Li, Xinhe Wang, Lijie Lu, Shengli Liu, Hao School of Electronic Science and Engineering Southeast University Nanjing Jiangsu China

With the increasing size of models in Convolutional Neural Networks (CNNs) recently, the demand for memory size, bandwidth and computational resources has gradually become a central issue. Quantification has a pivotal role in dramatically reducing the computation of CNN models and bandwidth. However, quantization technology is difficult to improve the throughput and power efficiency of accurately fixed accelerators. Different applications have different requirements for accelerators in all aspects, and accurately fixing accelerators lacks the flexibility to meet these requirements. In this paper, a precision configurable processing unit (PE) is proposed, which not only simplifies the computing unit and the external complex configurable logic, but also introduces the concept of approximate calculation, while ensuring a certain precision of CNN. For the first time, approximate computation is introduced in a configurable computational unit, which allows the architecture to further reduce power consumption based on bit-level flexibility and to accommodate parameters from different quantization methods of the network. The design of this paper is implemented in SMIC 40nm process library. Compared with Bit Fusion [1], this method achieves the lowest accuracy of 98.49% in Lenet, ensuring that the area and power consumption are reduced by 53.2% and 19.8% respectively. © 2022 Copyright for this paper by its authors.

关键词： Electric power utilization

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Re-configurable parallel stream processor with self-assembling and self-restorable micro-architecture

Re-configurable parallel stream processor with self-assembli...

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International conference on Parallel computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

作者： Kirischian, Lev Terterian, Irina Chun, Pil Woo Geurkov, Vadim Ryerson University Toronto Canada

ISBN: (纸本)0769520804

In this paper we present a concept of the self - assembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx "Virtex" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload and gives ability for self-restoration of processing micro architectures when hardware fault occurs. This Paper presents a description of system level architecture of run - time re-configurable multi-stream parallel processor for video applications and results gained on the prototype.

关键词： Parallel processing systems

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Proceedings - 2011 6th International conference on Pervasive computing and applications, ICPCA 2011

Proceedings - 2011 6th International Conference on Pervasive...

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2011 6th International conference on Pervasive computing and applications, ICPCA 2011

ISBN: (纸本)9781457702082

The proceedings contain 92 papers. The topics discussed include: a novel load balancing scheme for QoS provisionings over heterogeneous wireless networks;slotting optimization of warehouse based on hybrid genetic algorithm;the museum access and historical relic manage system based on RFID technology;distributed metadata management scheme in cloud computing;a configurable context-aware simulator for smart home systems;real-time traffic information collecting and monitoring system based on the Internet of things;mobility management QoS architecture based on a cross-layer scheme;the evaluation of qualitative assessment dynamics (QAD) methodology for managing trust in pervasive computing environments;cluster and set topology control on virtual backbone for coal mime;remote conference system based on 3G under pervasive computing;and energy-efficient cooperative communication with multi-relay contention and power allocation.

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Methodology to determine relationships between performance factors in hadoop cloud computing applications

Methodology to determine relationships between performance f...

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4th International conference on Cloud computing and Services Science, CLOSER 2014

作者： Bautista Villalpando, Luis Eduardo April, Alain Abran, Alain Department of Software Engineering and Information Technology - ETS University of Quebec Montreal Canada Department of Electronic Systems Autonomous University of Aguascalientes Aguascalientes Mexico

ISBN: (纸本)9789897580192

Cloud computing is a model for enabling ubiquitous, convenient, on-demand network access to a shared pool of configurable computing resources. Cloud computing users prefer not to own physical infrastructure, but instead rent Cloud infrastructure, a Cloud platform or software, from a third-party provider. Sometimes, anomalies and defects affect a part of the Cloud platform, resulting in degradation of the Cloud performance. One of the challenges in identifying the source of such degradation is how to determine the type of relationship that exists between the various performance metrics which affect the quality of the Cloud and more specifically Cloud applications. This work uses the Taguchi method for the design of experiments to propose a methodology for identifying the relationships between the various configuration parameters that affect the quality of Cloud computing performance in Hadoop environments. This paper is based on a proposed performance measurement framework for Cloud computing systems, which integrates software quality concepts from ISO 25010 and other international standards. Copyright © 2014 SCITEPRESS - Science and technology Publications.

关键词： Cloud computing

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Cloud computing as an Information technology Infrastructure for Civil Engineering SMEs

Cloud Computing as an Information Technology Infrastructure ...

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2nd International conference on Parallel, Distributed, Grid and Cloud computing for Engineering

作者： Dolenc, M. Klinc, R. Univ Ljubljana Fac Civil & Geodet Engn Ljubljana 61000 Slovenia

ISBN: (纸本)9781905088423

One of the key challenges of IT for architecture, engineering and construction is to provide the efficient, effective and flexible access to information and to provide all possible channels of communication. The world today is becoming increasingly mobile and users often do their work with the help of several different devices during their day. That is why the unified access to networks, servers, storage, applications, and services is needed. In order to achieve that mentioned resources cannot reside on local devices anymore, they should rather live in "the cloud" and be accessible via Web services to a vast spectrum of devices from different locations. Cloud computing is still an evolving paradigm that is rather difficult to define but it usually described as a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources that can be rapidly provisioned and released with minimal management effort or service provider interaction. The continuous process improvement via the strategic implementation of innovative information and communication technologies is essential for the long-term survival of construction firms. Unfortunately because of the specifics of the AEC sector SME construction companies have difficulties keeping up with the pace of the advancements in the technology and software. The paper examines the cloud computing model and other upcoming technologies and trends through civil engineering SME specific requirements.

关键词： cloud computing Web 2.0 social networks civil engineering engineering collaboration requirements

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Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor 16

Implementation of Reed Solomon Encoder on Low-Latency Embedd...

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16th IEEE International Wireless Communications and Mobile computing conference (IEEE IWCMC)

作者： Saidi, Hajer Turki, Mariem Marrakchi, Zied Obeid, Abdulfattah Abid, Mohamed Natl Engn Sch Sfax Digital Res Ctr Sfax CRNS CES Res Lab Sfax Tunisia Natl Engn Sch Sfax CES Res Lab Sfax Tunisia Mentor Graph Corp Sfax Tunisia King Abdulaziz City Sci & Technol Natl Ctr Elect & Photon Technol Riyadh Saudi Arabia

ISBN: (纸本)9781728131290

Having high efficiently embedded systems is important for various applications, especially, for modern communication systems, wireless sensor networks, mobile networks, and digital storage systems. Therefore, an efficient error control and correction solution in digital data is an important issue to ensure data protection. In this context, Reed Solomon codes are often used for error corrections. These embedded applications are implemented as software cores, hardware cores or a mixture of software-hardware Intellectual Property (IPs). In this paper authors proposes an efficient metric to improve performance, flexibility and cost of Reed Solomon (RS) Encoder by implementing this algorithm in Re-configurable System on Chip (SoC). The proposed system is composed of a low power ARM processor connected to a hierarchical embedded Field Programmable Gate Array (FPGA) to ensure the acceleration task with the best lowlatency which targets a wide range of applications. This is the first reconfigurable SoC composed by Tree-based embedded FPGA that targets the RS-Encoder algorithm. The first contribution is the design of a complete SoC integrating a software embedded FPGA (eFPGA) which is fully synthesized and implemented into an FPGA platform. The second added value is that the embedded FPGA size can go up to 4 KLUTS with a big number of inputs/outputs. The third contribution is that the proposed SoC targets one of the most powerful algorithms. The eFPGA integration introduces a chip area overhead but it proves interesting results in terms of run-time. Indeed, for 100 software instructions, the eFPGA is faster 4 times compared to a hardware accelerator and 412 times compared to the software implementation of the RS algorithm.

关键词： Embedded FPGA Re-configurable Tree-Based SoC Reed Solomon

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