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A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable computing

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2010年第8期45卷 1615-1626页

作者： Rossi, Davide Campi, Fabio Spolzino, Simone Pucillo, Stefano Guerrieri, Roberto ARCES I-40123 Bologna BO Italy STMicroelect Technol R&D I-20041 Agrate Brianza MB Italy

This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastructure based on a 64-bit Network On Chip. The SoC combines a fine grain embedded FPGA, a mid grain configurable processor and a coarse grain reconfigurable array. An ARM processor featuring a resident operating system is the SoC supervisor, managing communication, synchronization and reconfiguration mechanisms. This computational model enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigurable engines. The SoC has been fabricated in 90-nm technology, the die area being 110 mm(2);it integrates 97 million transistors and has a peak power consumption of 2.5 W. In order to demonstrate the proposed computational model and the reconfigurable signal processor capabilities in a real test case, a video surveillance motion detection application was implemented in the SoC. When running this application, the device proved able to deliver 120 GOPS dissipating 1.45 W.

关键词： Digital signal processors globally asynchronous locally synchronous Network-on-Chip reconfigurable architectures System-on-Chip

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Exploring Challenges in Mobile Cloud computing: An overview

Exploring Challenges in Mobile Cloud Computing: An overview

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4th International conference on the Next Generation Information technology Summit, Confluence 2013

作者： Tuli, Anupriya Hasteer, Nitasha Sharma, Megha Bansal, Abhay Amity University U.P. India

ISBN: (纸本)9781849198462

Cloud computing has been the topic of research for quite some time now. It is a model for enabling convenient, ubiquitous, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, applications, and services including security, application development, etc.) that can be rapidly provisioned and released with minimal management effort or service provider interaction. On the other hand, the increasing technological enhancement in the field of mobile computing is demanding pervasive and ubiquitous computing (PUC), which has given birth to the idea of integrating the concept of Cloud with mobile computing. This new paradigm known as Mobile cloud computing (MCC), has emerged as an area of keen interest among researchers. Mobile Cloud computing is a mobile computing technology that uses unified elastic resources of different clouds and network technologies to provide mobile user with high computing power and storage capacity with limited resources in hand, and is based on the "pay-as-you-use" principle. This paper analyses the MCC architecture, exploring all possible challenges surrounding it under two groups (Challenges in Mobile computing & Challenges in Cloud computing) and finally concluding with heterogeneity being the prime factor contributing to these challenges.

关键词： Mobile cloud computing

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Workflow technology for drug discovery

Workflow technology for drug discovery

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3rd International conference on Grid and Pervasive computing Symposia/Workshops, GPC 2008

作者： Luo, Liangying Zhang, Ruisheng Zhang, Chunyan Fan, Xiaoliang Li, Lian Engineering Research Center of Open Source Software and Real-time Systems Department of Information Science and Engineering Lanzhou University Lanzhou Gansu 730000 China

ISBN: (纸本)9780769531779

Grid computing can integrate huge services and resources across distributed, heterogeneous, dynamic virtual organizations, and provide tremendous computing power in parallel. Workflow technology enables the user to compose complex Grid applications on distributed heterogeneous and unreliable hardware resources without taking care of lower level details. The drug discovery process almost comprises a number of sub processes, in which various software to be invoked, complex computing and huge amounts of data analyze are involved. Scientific workflow is the process of combining data and processes into a configurable, structured set of steps that implement semi-automated. Distributed processing and parallel computing capacity can improve the Computational efficiency. Therefore, the problems in drug discovery can be solved using the workflow technology. This paper discusses the problem on drug discovery process and presents how to utilize workflow in our eSOC System to resolve the three most important issues in drug discovery. © 2008 IEEE.

关键词： Grid computing

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Edge-Optimized AI Architecture: MRAM-based Near Memory computing Core Balancing between Memory Capacity and Computation

Edge-Optimized AI Architecture: MRAM-based Near Memory Compu...

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2024 IEEE International conference on Integrated Circuits, Technologies and applications, ICTA 2024

作者： Yang, Xi Chang, Liang Wang, Yuanbo Wang, Jingke Fan, Chao Wu, Zhongmou Zhou, Jun University of Electronic Science and Technology of China Chengdu611731 China Nanjing Houmo AI Inc Nanjing210008 China Casicyber Industrial Technology Research Insititute Chengdu610317 China

ISBN: (纸本)9798331530709

General-purpose edge neural networks require a lightweight architecture, delivering both suitable memory capacity and compute resources. Typically, the SRAM-based computing-in memory (CIM) architecture is difficult to provide sufficient storage to fulfilling the computing requirements, and various buffers are needed. In this work, we present a novel high-capacity MRAM-based near memory computing (NMC) architecture with configurable computing unit, adeptly striking a balance between the edge network's demands for storage and computing. It has realized a storage density of 1.49 Mb / mm2 on-chip and an excellent energy efficiency of 6.164 TOPS/W. © 2024 IEEE.

关键词： Magnetic bubble memories

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Lessons learned in designing user-configurable modular robotics 2

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2nd International conference on Robot Intelligence technology and applications, RiTA 2013

作者： Lund, Henrik Hautop Center for Playware Technical University of Denmark Building 326 2800 Kgs Lyngby Denmark

ISBN: (纸本)9783319055817

User-configurable robotics allows users to easily configure robotic systems to perform task-fulfilling behaviors as desired by the users. With a user configurable robotic system, the user can easily modify the physical and functional aspect in terms of hardware and software components of a robotic system, and by making such modifications the user becomes an integral part in the creation of an intelligence response to the challenges posed in a given environment. I.e. the overall intelligent response in the environment becomes the integration of the user's construction and creation with the semi-autonomous components of the user-configurable robotic system in interaction with the given environment. Components constituting such a user-configurable robotic system can be characterized as modules in a modular robotic system. Several factors in the definition and implementation of these modules have consequences for the user-configurability of the system. These factors include the modules granularity, autonomy, connectivity, affordance, transparency, and interaction. © Springer International Publishing Switzerland 2014.

关键词： Human robot interaction

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Designing and Programming the configurable Cloud 17

Designing and Programming the Configurable Cloud

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14th ACM International conference on computing Frontiers

作者： Putnam, Andrew Microsoft US Redmond WA 98052 USA

ISBN: (纸本)9781450344876

Process technology improvements have historically allowed an effortless expansion of the capacity and capabilities of computers and the cloud with few changes to the underlying software or programming model. However, the end of Dennard Scaling means that performance and efficiency gains will rely on the customization of the hardware for each application. Yet customizing hardware for each application runs contrary to the trend to moving more and more applications to a common hardware infrastructure the Cloud. Microsofts Catapult project has brought the power and performance of FPGA-based reconfigurable computing to hyperscale datacenters, accelerating major production cloud applications such as Bing web search and Microsoft Azure, and enabling a new generation of machine learning and artificial intelligence applications. These diverse workloads are accelerated using the same underlying hardware by using highly programmable silicon. The presence of ubiquitous and programmable silicon in the datacenter enables a new era of hardware/software co-design across a wide variety of workloads, opening up affordable and efficient performance across an enormous set of workloads. Catapult is now deployed in nearly every new server across the more than a million machines that make up the Microsoft hyperscale cloud. In this talk, I will describe the next generation of the Catapult configurable cloud architecture, and the tools and techniques that have made Catapult successful to date. I will discuss areas where traditional hardware and software development flows fall short, the domains where this programmable hardware holds the most potential, and how this technology can enable new computing frontiers.

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Distance Education Application Architecture and Cloud computing 8

Distance Education Application Architecture and Cloud Comput...

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8th IEEE International conference on Application of Information and Communication Technologies (AICT)

作者： Akcay, Muammer Armutlu, Hasan Dumlupinar Univ Dept Comp Engn Kutahya Turkey Usak Univ Karahalli Vocat Sch Comp Technol Usak Turkey

ISBN: (纸本)9781479941209

Distance education systems, initially perceived as a knowledge management system and knowledge management system in the preparation of distance education applications architectures have been used. However, students in the distance education system modules, tutorials, modules, such as the adequacy of student assessment and tutorial are many human factors. This application architectures and algorithms used in distance education because they are not flexible enough to be applied to these factors, they are forced to respond. Distance education systems must be more flexible and re-configurable. Cloud computing, which is based on sharing knowledge and equipment, services to gather under a single roof instead of offering a solution for each service is an information technology. Cloud computing technologies, more flexible compared to conventional information technology, can be updated quickly and are innovative. Distance education system through the use of cloud computing in addressing the needs of distance education is emerging architectures and algorithms. In this paper, application architecture according to the distance education system will be created. This application architecture will be utilized when creating cloud services and these services will be studied harmony with each other.

关键词： distance education cloud computing architecture algorithm

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An emulator for exploring RaPiD configurable computing architectures

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11th International conference on Field-Programmable Logic and applications, FPL 2001

作者： Fisher, Chris Rennie, Kevin Xing, Guanbin Berg, Stefan G. Bolding, Kevin Naegle, John Parshall, Daniel Portnov, Dmitriy Sulejmanpasic, Adnan Ebeling, Carl Department of Computer Science and Engineering University of Washington Box 352350 SeattleWA98195-2350 United States

ISBN: (纸本)3540424997

The RaPiD project at the University of Washington has been studying configurable computing architectures optimized for coarse-grained data and computation units and deep computation pipelines. This research targets applications in the signal and image-processing domain since they make the greatest demand for computation and power in embedded and mobile computing applications, and these demands are increasing faster than Moore’s law. This paper describes the RaPiD Emulator, a system that will allow the exploration of alternative configurable architectures in the context of benchmark applications running in real-time. The RaPiD emulator provides enough FPGA gates to implement large RaPiD arrays, along with a high performance streaming memory architecture and high-bandwidth data interfaces to a host processor and external devices. Running at 50 MHz, the emulator is able to achieve over 1 GMACs/second. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Memory architecture

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Warship Reusable Component Model Development Approach for Parallel and Distributed Simulation 16th

Warship Reusable Component Model Development Approach for Pa...

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Joint conference of the 16th Asia Simulation conference / SCS International Autumn Simulation Multi-conference (AsiaSim/SCS AutumnSim)

作者： Ma, Haibo Yao, Yiping Tang, Wenjie Natl Univ Def Technol Coll Informat Syst & Management Changsha Hunan Peoples R China

ISBN: (纸本)9789811026638;9789811026621

Model reuse is a key issue to be resolved in parallel and distributed simulation when developing military simulation applications at present. However, component model built by different domain experts usually have diversiform interfaces, couple tightly and bind with simulation platforms and specific applications closely. As a result, they are difficult to be reused across different simulation platforms as well as applications. In addition, traditional model reuse ways lack consideration about reusability efficiency of similar reusable models. As for developing warship models in practical application, there also lack pragmatic method to describe its simulation space from conception space. To address the problem, this paper first proposed the parameterization-configurable framework for reusable component model that supports similar models once developed but multiple reused adapting to varied function requirement. Based on this framework, then our reusable model development approach for warship model is elaborated, which contains three phases: (1) design the warship configurable function set based on capacity demand;(2) use CMPA (Capacity, Mission, Process, Action) description method to map the function set from conception model to simulation model;(3) implement and encapsulate the model with the reusable simulation model development specification. The approach provides a pragmatic technical means for developing warship component reusable models in complex military simulation application, which helps improving efficiency of development and could be referenced for other similar models.

关键词： Reuse Parameterization-configurable framework Warship simulation modeling CMPA

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Towards Run-Time Re-configurable Techniques for Real-Time Embedded applications

Towards Run-Time Re-Configurable Techniques for Real-Time Em...

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Proceedings of the International conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'03

作者： Oliver, Timothy F. Maskell, Douglas L. Ctr. for High Perf. Embedded Systems School of Computer Engineering Nanyang Technology University Singapore Singapore

ISBN: (纸本)193241505X

Many embedded applications can benefit from the flexible custom computing opportunities that FPGA technology offers. The Run-Time Reconfiguration (RTR) of the FPGA as an application is being served provides further flexibility. It gives the opportunity to reuse FPGA space used by custom computing circuits that are not operational in a given time frame. Custom computing circuits can meet very tight real-time requirements but when it comes to reconfiguring these circuits, the time taken can be comparatively long and non-deterministic. There is a need for a suitable development environment to investigate how to cope with or reduce the RTR time. This paper describes how this can be achieved with currently available tools and technologies. We first review an appropriate subset of the available technology to implement a system comprising a CPU running a RTOS on a SoPC that can be adapted using RTR. Then we propose a system architecture that is feasible with current technology. We outline the processes and databases needed to support RTR of the SoPC. We present how the RTOS is made aware of the architectural constraints and reconfiguration options, thus simplifying the use of reconfigurable hardware for the application programmer.

关键词： Field programmable gate arrays

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