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检索条件"任意字段=Conference on Configurable Computing - Technology and Applications"

共 333 条记录，以下是81-90 订阅

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Energy-Efficient Hardware Acceleration through computing in the Memory

Energy-Efficient Hardware Acceleration through Computing in ...

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Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Paul, Somnath Karam, Robert Bhunia, Swarup Puri, Ruchir Intel Corp Hillsboro OR 97124 USA Case Western Reserve Univ Cleveland OH USA IBM Corp Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9783981537024

Energy-efficiency has emerged as a major barrier to performance scalability for modern processors. We note that significant part of processor's energy requirement is contributed by processor-memory communication. To address the energy issue in processors, we propose a novel hardware accelerator framework that transforms high-density memory array into a configurable computing resource to accelerate variety of tasks - both compute- and data-intensive. It exploits the block-based architecture of nanoscale memory to create a spatially connected array of lightweight processors, each of which uses a memory block as its local memory. The proposed framework provides some unique advantages for hardware acceleration compared to conventional accelerators: 1) memory array provides large set of parallel resources with high bandwidth, which can be configured to perform computing in spatio/temporal manner leading to dramatic reduction in processor-memory traffic;2) it brings the computing engine close to the data, thus drastically minimizing the von Neumann bottleneck;3) finally, it exploits the advances in memory technologies and integration approaches e.g. 3D integration to achieve better technology scalability compared to alternative reconfigurable accelerator platforms. Simulation results for several data-intensive applications show that the proposed computing approach provides significant improvement in energy-efficiency compared to software while achieving significantly lower hardware overhead.

关键词： integration microprocessor chips performance evaluation power aware computing reconfigurable architectures 3D integration approach block-based architecture computing engine configurable computing resource energy issue energy-efficient hardware acceleration hardware accelerator framework high-density memory array lightweight processors memory technologies nanoscale memory performance scalability processor energy requirement processor-memory communication processor-memory traffic spatially connected array von Neumann bottleneck Arrays Flash memories Hardware Nonvolatile memory Organizations Program processors

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Single package re-configurable processor for data acquisition at 250°C

Single package re-configurable processor for data acquisitio...

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IMAPS High Temperature Electronics conference, HiTEC 2008

作者： Romanko, Thomas J. Johnson, Michael T. Ohme, Bruce W. Honeywell International Inc. Honeywell Aerospace Defense and Space 12001 State Highway 55 Plymouth MN 55441 United States

ISBN: (纸本)9781615670918

A high-temperature data processing device is required for applications gathering sensor data and control of electronics in environments which operate above 200°C. This paper discusses the process of leveraging advances in high temperature electronics and integrating them for new applications and improved system performance. It centers on the development of the 250°C High Temperature (HT) SOI CMOS process technology, several new HT products, and HT package technology. Honeywell integrates a HT FPGA, SRAM and EEPROM into a Multi-Chip Module (MCM) creating a flexible, re-configurable computing platform for sensor data processing and control applications at 250°C. A reconfigurable processor enables the ability to gather information from multiple sources and then control multiple devices with a single electronics assembly while reducing size, weight and power. Packaged in a small 2.2 × 0.75 inch (56 × 18 mm) MCM, the module operates at clock rates up to 10MHz from a single 5V supply. Although power consumption is strongly dependent on configuration, the targeted demonstration configuration clocked at 1MHz power dissipation is on the order of 100mW. The combination of all these technologies and application code to operate the module provides a significant improvement over existing technology for data acquisition applications.

关键词： Data acquisition

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Area and Energy Efficient Approximate Square Rooters for Error Resilient applications 33

Area and Energy Efficient Approximate Square Rooters for Err...

引用

33rd IEEE International conference on VLSI Design / 19th International conference on Embedded Systems

作者： Arya, Neelam Soni, Teena Pattanaik, Manisha Sharma, G. K. ABV Indian Inst Informat Technol & Management Gwalior 474015 Madhya Pradesh India

ISBN: (数字)9781728157016

ISBN: (纸本)9781728157016

Approximate computing is gaining momentum for design of accuracy-energy configurable circuits for error-tolerant applications. In this paper, a low power reduced area square root (SQR) circuit is presented that achieves remarkable area and energy efficiency, while introducing trivial inaccuracies in the results. Two approximate designs are proposed for restoring array based square-root circuit for error-resilient applications. In the first design, approximate restoring subtractor cells are used to substitute exact SQR subtractor cells by simplifying the boolean expressions. The second design reduces the design complexity and increases energy efficiency by using the classic approximate computing technique of bit-truncation. Both the designs are implemented for 8- and 16-bit square-root circuit design with different values of approximation parameter 'd' for achieving various design trade-off points. Our results indicate that the proposed approximated SQR designs show an improvement in terms of delay, power consumption, energy and area and improves these parameters on average by 37%, 24%, 18%, and 44%, respectively for 16-bit SQR designs when implemented on CMOS 45-nm technology node without compromising much on accuracy. Also, the proposed approximate designs are tested on error tolerant applications including contrast enhancement for medical images and envelope detection in AM (Amplitude Modulation) communication systems. Furthermore, our results validate the approximate square-root designs with improvement in Contrast to Noise ratio (CNR) for image processing applications and an acceptable Signal to Noise ratio (SNR) for analog communication system.

关键词： Approximate computing square root circuit energy efficiency restoring subtractor cells error-resilient applications image processing

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A new virtualized environment for application deployment based on docker and AWS

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International conference on Information Science and applications, ICISA 2016

作者： Tihfon, Gemoh Maliva Kim, Jinsul Kim, Kuinam J. School of Electronics and Computer Engineering Chonnam National University Gwangju500-757 Korea Republic of Convergence Security Department Kyonggi University SuwonGyonggi-Do Korea Republic of

ISBN: (纸本)9789811005565

The setup environment and deployment of distributed applications is a human intensive and highly complex process that poses significant challenges. Nowadays many applications are developed in the cloud and existing applications are migrated to the cloud because of the promising advantages of cloud computing. The very core of cloud computing is virtualization. In this paper, we will look at application deployment with Docker. Docker is a lightweight containerization technology that has gained widespread popularity in recent years. It uses a host of the Linux kernel’s features such as namespaces and croup’s to sandbox processes into configurable virtual environments. Presenting two common serious challenging scenarios in the software development environment, we propose a multi-task PaaS cloud infrastructure using Docker and AWS services for application isolation/optimization and rapid deployment of distributed applications. © Springer Science+Business Media Singapore 2016.

关键词： Cloud computing

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RFD Based Technique on QoS Parameters using Cloud computing 6

RFD Based Technique on QoS Parameters using Cloud Computing

引用

6th Smart Cities Symposium, SCS 2022

作者： Nayak, Nihar Ranjan Mishra, Srinivas Chowdhury, Subrata Dutta, Pushan Kumar Ramya, G. Department of CSE Presidency University Bengaluru India Andhra Pradesh Chittoor India Dept of ECE School of Engineering and Technology Amity University Kolkata India Department of Information Technology VIT University Vellore India

ISBN: (纸本)9781839538544

Cloud computing is a prominent paradigm and a network of server technology where different services, application, and substantial computing resources are cost-effectively handled over the internet. The class of technology day by day moves to new stalk border technologies which make a great outcome on process aliveness and in the way of doing computing and businesses. Cloud technology is a supporter of the current business process, on-demand meshwork access to a mutual spot of configurable computing resources (e.g., networks, servers, store, applications, and services) that can be speedily provisioned and free with nominal management activity or Interactive nature in business application which claim into several services that can be contract in real-time scenario. This includes virtualization, brokering services, programming methods, queuing work, CPU cores, and action time. The proposed algorithms achieve essential results in the optimal scheduling utilization and modify the complete action of the cloud computing systems. These algorithms can grips a more significant number of individual requests, providing a outstrip provisioning of resources and providing better result in response time, cost and time. © 2022 IET conference Proceedings. All rights reserved.

关键词： Cloud computing

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configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning 5

Configurable Multi-Precision Floating-Point Multiplier Archi...

引用

5th IEEE International conference on Artificial Intelligence Circuits and Systems, AICAS 2023

作者： Kuo, Pei-Hsuan Huang, Yu-Hsiang Huang, Juinn-Dar National Yang Ming Chiao Tung University Department of Electronics and Electrical Engineering & Institute of Electronics Hsinchu Taiwan

ISBN: (纸本)9798350332674

The increasing AI applications demands efficient computing capabilities to support a huge amount of calculations. Among the related arithmetic operations, multiplication is an indispensable part in most of deep learning applications. To support computing in different precisions demanded by various applications, it is essential for a multiplier architecture to meet the multi-precision demand while still achieving high utilization of the multiplication array and power efficiency. In this paper, a configurable multi-precision FP multiplier architecture with minimized redundant bits is presented. It can execute 16× FP8 operations, or 8× brain-floating-point (BF16) operations, or 4× half-precision (FP16) operations, or 1× single-precision (FP32) operation every cycle while maintaining a 100% multiplication hardware utilization ratio. Moreover, the computing results can also be represented in higher precision formats for succeeding high-precision computations. The proposed design has been implemented using the TSMC 40nm process with 1GHz clock frequency and consumes only 16.78mW on average. Compared to existing multi-precision FP multiplier architectures, the proposed design achieves the highest hardware utilization ratio with only 4.9K logic gates in the multiplication array. It also achieves high energy efficiencies of 1212.1, 509.6, 207.3, and 42.6 GFLOPS/W at FP8, BF16, FP16 and FP32 modes, respectively. © 2023 IEEE.

关键词： Deep learning

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The definition and implementation of a framework for web-based configurable software

The definition and implementation of a framework for web-bas...

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2009 11th IEEE International conference on e-Health Networking, applications and Services, Healthcom 2009

作者： Wu, Junjie Zhu, Yonghua Zhu, Huaiyang School of Computer Engineering and Science Shanghai University No.149 Yan Chang Road Shanghai China Computing Center of Shanghai University Shanghai University Bldg. D Shang Da Road Shanghai China Shanghai Rongheng Information Technology Ltd. Bldg. 3 No.28 Lane 91 Eshan road Shanghai China

As existing web-based application has shortcomings of long development life cycle, low reuse rate and poor expansibility causes a great number of problems for the developers and users. Based on these problems, a framework for web-based configurable software is presented in this paper. This framework is composed of three layers and seven main modules. Under the guidance of this framework, a web-based configurable software was implemented. Finally, the efficiency and the scalability of this framework are proved by a practical application. © 2012 Springer-Verlag GmbH.

关键词： Life cycle

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LEMO-MR: Low overhead and elastic MapReduce implementation optimized for memory and CPU-intensive applications

LEMO-MR: Low overhead and elastic MapReduce implementation o...

引用

2nd IEEE International conference on Cloud computing technology and Science, CloudCom 2010

作者： Fadika, Zacharia Govindaraju, Madhusudhan Computer Science Department Binghamton University P.O. Box 6000 Binghamton NY 13902-6000 United States

ISBN: (纸本)9780769543024

Since its inception, MapReduce has frequently been associated with Hadoop and large-scale datasets. Its deployment at Amazon in the cloud, and its applications at Yahoo! and Facebook for large-scale distributed document indexing and database building, among other tasks, have thrust MapReduce to the forefront of the data processing application domain. The applicability of the paradigm however extends far beyond its use with data intensive applications and diskbased systems, and can also be brought to bear in processing small but CPU intensive distributed applications. In this work, we focus both on the performance of processing large-scale hierarchical data in distributed scientific applications, as well as the processing of smaller but demanding input sizes primarily used in diskless, and memory resident I/O systems. In this paper, we present LEMO-MR (Low overhead, elastic, configurable for in-memory applications, and on-demand fault tolerance), an optimized implementation of MapReduce, for both on-disk and in-memory applications, describe its architecture and identify not only the necessary components of this model, but also trade offs and factors to be considered. We show the efficacy of our implementation in terms of potential speedup that can be achieved for representative data sets used by cloud applications. Finally, we quantify the performance gains exhibited by our MapReduce implementation over Apache Hadoop in a compute intensive environment. © 2010 IEEE.

关键词： MapReduce

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A Gamification Model for Resource Sharing in Malaysian Schools Using Cloud computing Platform 16th

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16th International conference on Intelligent Systems Design and applications (ISDA)

作者： Rahman, M. Nordin A. Saidu, Abdullahi Nababa Kadir, M. Fadzil A. Shamsudin, Syadiah Nor Saany, Syarilla Iryani A. Univ Sultan Zainal Abidin Fac Informat & Comp Besut Campus Besut 22200 Malaysia

ISBN: (纸本)9783319534800;9783319534794

Cloud computing is a technology that delivers a pool of configurable computing resources to the users. The insufficient systems for sharing of resources, poor extended pattern of resource sharing system, inadequate network and computing facilities have become an issue in school management. This article discusses a model for resource sharing in Malaysian schools using cloud computing platform. The sharing of resources is modelled based on Multi-Person Prisoner's Dilemma and Peer-Approved incentive mechanism that gives justification to users in the resource utilization. The concept of software as a service is adopted to make the model can be managed in the cloud environment. Based on the proposed model, a prototype is developed and deployed into cloud using OpenStack architecture. The prototype is evaluated using questionnaire instrument that is based on four attributes of usability metrics. The result shows that the model usability achieved 79.28% of effectiveness, 81.35% of efficiency, 91.8% of learnability and 93.18% of satisfaction. The proposed model could save the cost of buying computing and storage infrastructure since all the resources are cloud based.

关键词： Software as a service (SaaS)

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CFPM: Run-time configurable Floating-Point Multiplier 18

CFPM: Run-time Configurable Floating-Point Multiplier

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18th International conference on Ph.D Research in Microelectronics and Electronics (PRIME)

作者： Saggese, Gerardo Napoli, Ettore Strollo, Antonio Giuseppe Maria Univ Napoli Federico II DIETI Naples Italy Univ Salerno DIEM Salerno Italy

ISBN: (纸本)9798350303209

Approximate computing is a new approach that can help to reduce power consumption in error-resilient applications. Although many works have been proposed for fixed-point multipliers with predetermined levels of accuracy, they are not able to adapt to a wide range of applications, that need floating-point calculations with time-varying requirements. In this paper, we introduce an adjustable floating-point multiplier in which groups of partial products can be dynamically truncated, while the approximation error is reduced with the help of a simple rounding technique. In the proposed floating-point multiplier, precision and power can be adjusted at run-time based on the users' requirements. The developed circuits are synthesized in TSMC 28 nm CMOS technology. The comparison with the state-of-the-art shows a good trade-off between error and power consumption. Furthermore, we demonstrate the suitability and versatility of our multiplier through image processing applications, proving that it can be usefully employed in real-world scenarios.

关键词： Approximating computing Approximate multiplier Floating-Point multiplier run-rime reconfigurability low-power

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