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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1418 条记录，以下是91-100 订阅

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A 2GS/s 10-bit time-interleaved capacitive DAC for self-interference-cancellation application 16

A 2GS/s 10-bit time-interleaved capacitive DAC for self-inte...

引用

2021 International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design, SMACD 2021 and 16th conference on PhD Research in microelectronics and Electronics, PRIME 2021

作者： Eslami, Mazyar Abedinkhan Manstretta, Danilo Castello, Rinaldo Microelectronics Laboratory University of Pavia Pavia Italy

ISBN: (纸本)9783800755899

This article presents a 2-GS/s time-interleaved (TI) 10-bit capacitive digital-to-analog converter (CDAC) for self-interference-cancellation (SIC) application. It is also capable of working as a non-TI & stand-alone CDAC with 1-GS/S clock frequency. By taking advantage low parasitic capacitance and equivalent parasitic capacitance at bottom and top plate of MIM capacitor, the split-capacitor technique is used without significant degradation in the linearity. The special architecture of the designed layout also relieves the local and radial oxide gradient error. The CDAC is designed in 28nm CMOS technology. If the CDAC works in stand-alone mode with 1-GS/s clock frequency, followed by an additional anti-aliasing filter and the baseband input frequency equals 10.74 MHz, the ENOB, SFDR and THD at the output of the filter is equal to11.3-bit,76 dB and 76dB, respectively. © VDE VERLAG GMBH.

关键词： Digital to analog conversion

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Analysis of Grid Integrated PV System for Different Load Power Factors

Analysis of Grid Integrated PV System for Different Load Pow...

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Recent Trends in microelectronics, Automation, Computing and Communications Systems (ICMACC), International conference on

作者： G. Lakshminarayana G. Sasi Kumar Adidela Vagdevi Department of EEE VNR Vignana Jyothi Institute of Engineering and Technology Hyderabad India

ISBN: (数字)9798350366570

ISBN: (纸本)9798350366587

The growing apprehension over global warming, along with rising energy needs, has propelled the traditional power infrastructure towards greater reliability through integration of renewable energies into grid. Incorporating renewable energies into grid presents numerous challenges. Throughout the day, the output power of the photovoltaic systems fluctuates. This paper elucidates how various power factors on the load side affect the entire system. Several simulation cases are conducted using different power factors to analyze the impact on the entire grid-integrated PV system. Furthermore, it is observed that the converter and filter design play major role in synchronization of PV with grid. Developing sufficient control techniques for grid-connected inverter equipped with LCL filter is a complex task. The grid integrated PV system is explored through simulations conducted in MATLAB/Simulink, where an initial network model is developed for the PV power system. This paper suggests that the low value of the power factor may lead to heavy damage due to the high current flow in loads and these simulation results are presented as per power factors extemporizations.

关键词： Reactive power Renewable energy sources simulation Production Propulsion Inverters Power system reliability Synchronization Reliability Load modeling

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Multi-Scale Electrothermal Co-simulation of GaN HEMTs at the Device and Packaging Levels

Multi-Scale Electrothermal Co-Simulation of GaN HEMTs at the...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Yi Zhang Ziyue Zhang Yuchao Wu Zhiying Chen Dong Lu Ke Xue Renjie Wang Smart Manufacturing Thrust HKUST(GZ) Guangzhou China Microelectronics Thrust HKUST(GZ) Guangzhou China College of Future Technology HKUST(GZ) Guangzhou China

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) are critical for high-power and high-frequency applications but face challenges from self-heating and inadequate thermal management, which degrade performance and reliability. Existing tools like Technology Computer Aided design (TCAD) and finite element analysis (FEA) lack integrated electrothermal coupling capabilities. This study proposes a multi-scale electrothermal co-simulation framework to bridge device-level electrical behavior and packaging-level thermal dynamics. The methodology integrates 2D TCAD simulations for localized Joule heating in the two-dimensional electron gas (2DEG) region with 3D FEA modeling to evaluate heat dissipation across packaging structures. An iterative loop couples the electrical power density from TCAD into FEA as averaged heat sources, updating boundary conditions until thermal convergence is achieved. Key innovations include a deep neural network (DNN) to resolve highly localized heat distributions from TCAD data and an equivalent thermal conductivity model for computational efficiency. The multi-scale approach successfully captured electrothermal interactions, enabling optimized packaging designs and material adjustments to balance heat generation and power efficiency. This work demonstrates the necessity of a coupled simulation for accurate performance prediction and thermal management in GaN HEMTs, offering a pathway to enhance reliability in high-power applications.

关键词： Heating systems Performance evaluation Temperature distribution Solid modeling HEMTs Packaging Electronic packaging thermal management Thermal management MODFETs Gallium nitride

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modeling and optimization of supply sensitivity for a time-domain temperature sensor 16

Modeling and optimization of supply sensitivity for a time-d...

引用

作者： Tan, Jun Ilmenau Germany

ISBN: (纸本)9783800755899

This paper presents a methodology for modeling and optimizing the supply sensitivity for a time-domain temperature sensor. Many modern System-on-Chip (SoC) designs integrate multiple functional blocks, such as sensors, power management units (PMU), and wired/wireless communication interfaces. Interference on the supply line between such blocks becomes critical, since it has a significant impact on sensor performance. Many state-of-the-art designs utilize supply sensitivity as a sensor parameter to describe the immunity to supply interference. Therefore, modeling and analysis of this parameter to optimize sensor performance is needed. This paper begins with the modeling of the common time-domain temperature sensor, while an instance of the model is precisely created with extracted parameters. Additionally, verification is performed by comparing the model with a transistor-level design. Finally, the optimization methodology for supply sensitivity improvement is discussed. The results show that the DC supply sensitivity is significantly reduced by a factor of 41. With the proposed methodologies, a further AC supply sensitivity can be analyzed and optimized, so that sensor performance in SoC designs can be improved. © VDE VERLAG GMBH.

关键词： Temperature sensors

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Russian Instrument Engineering on the Issue Development of Electronic Components and Application of Compact SPICE Models

Russian Instrument Engineering on the Issue Development of E...

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Informatics, Electronics, and Radio Engineering (PIERE), International conference Problems of

作者： Vladislav V. Bodrov Ivan L. Reva Novosibirsk State Technical University Novosibirsk Russia

ISBN: (数字)9798331516321

ISBN: (纸本)9798331516338

At present, in the conditions of technological limitations, the most important task is the rapid restoration and modernization of the Russian microelectronics industry. And this is problematic without the appearance in the country of modern crystal rulers with design standards less than 0.25 microns. The creation of crystal technology is a very expensive and knowledge-intensive process, which includes not only the acquisition and launch of the entire fleet of technological equipment, but also the development of the necessary routing technologies, which involve the creation of a PDK (process design kit), allowing developers of ultra-large-scale integrated circuits, using computer-aided design systems, to design a crystal that, in terms of electrical parameters and characteristics with an acceptable error, will completely coincide with the test results of the manufactured crystal. This is achieved through the use of simulation Program with Integrated Circuit Emphasis - SPICE models, which allow you to accurately and reliably describe the operation of the active elements of the circuit, primarily transistors. To assess the current state and determine the route for creating complete SPICE models for a specifically selected technology, the article analyzes technical information on this issue: basic concepts, structure, types, selection criteria and scope of application of SPICE models. Based on the results of the analysis, a route for creating complete SPICE models of transistors was outlined.

关键词： Semiconductor device modeling Solid modeling Analytical models design standards Crystals SPICE Reliability engineering Transistors Integrated circuit modeling Integrated circuit reliability

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A High-Resolution SAR ADC design with Linearity Enhancement Achieving Signal-to-Noise-and- Distortion-Ratio of 97.4dB 5

A High-Resolution SAR ADC Design with Linearity Enhancement ...

引用

5th IEEE International conference on Electronics Technology, ICET 2022

作者： Chen, Zulin Wang, Zongmin Zhang, Tieliang Yang, Song Yang, Long Beijing Microelectronics Technology Institute China Academy of Launch Vehicle Technology Beijing100076 China

ISBN: (纸本)9781665485081

Spaceborne industry and medical imaging equipment have been developed rapidly these years, resulting in the demand for system performance, integration level and energy efficiency in their signal chains. SAR ADCs that reside in the region where it runs faster than 1MS/s with 16-bit to 18-bit resolution have good prospects in these fields. A high-resolution SAR ADC with Signal-to-Noise-and-Distortion-Ratio (SNDR) enhanced by digital calibration is proposed based on the 0.25 mu m Mixed-Signal CMOS process, using a 5V external reference while the digital works in 2.5V. design issues across voltage domains are discussed. SPECTRE and MATLAB tools are used for modeling and simulation. Results show that the SNDR is 70.8dB before calibration, which gives an ENOB value of 11.47-bit. While after calibration, the SNDR is 97.4dB, reaches an ENOB value of 15.88-bit. © 2022 IEEE.

关键词： Calibration

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Analysis and modeling of Non-ideal Effects in SAR ADC

Analysis and Modeling of Non-ideal Effects in SAR ADC

引用

International conference on ASIC

作者： Yaxin Zeng Hao Xu Xi Feng Na Yan State Key Laboratory of Integrated Chip and Systems Fudan University Shanghai China Beijing Smartchip Semiconductor Technology Co. Ltd Beijing Smartchip Microelectronics Technology Co. Ltd Beijing China

For high resolution SAR ADC, the noise and distortion will significantly degrade the performance, thus should be considered carefully during design. This paper presents a behavioral modeling of SAR ADC in Simulink. The model includes the performance limitations such as clock jitter, capacitor mismatch, sampled KT/C noise for switches, noise and offset of comparator and S/H on-resistance distortion. The simulation results of the proposed model provide guidance in choosing the circuit structure and determine spec breakdown of each block in the SAR ADC, which increases the design efficiency with fast design iterations.

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An essay on the next generation of performance-driven analog/RF IC EDA tools: The role of simulation-based layout optimization 16

An essay on the next generation of performance-driven analog...

引用

作者： Martins, Ricardo Gusmão, António Canelas, António Passos, Fábio Lourenço, Nuno Horta, Nuno Instituto de Telecomunicações Lisboa Portugal Instituto Superior Técnico Universidade de Lisboa Portugal Dialog Semiconductors Lisboa Portugal

ISBN: (纸本)9783800755899

Despite the fact that analog and radio-frequency (A/RF) integrated circuit (IC) design automation has been intensively studied in the last few decades, only automatic circuit-level sizing methodologies have achieved a satisfactory level of maturity. Layout and its countless issues have challenged all automation attempts, and two limiting factors must be addressed to force their way into the industrial environment: plug-and-play capabilities and accurate assessment of post-layout performance degradation. This paper brainstorms around the idea of developing the ultimate fully automatic "performance-driven" A/RF IC synthesis by incorporating simulation-based layout optimization concepts in the flow. The essay is carried the PONDEROUS tool, a novel and highly integrated, but exceptionally computationally intensive, placement A/RF IC optimizer. © VDE VERLAG GMBH.

关键词： Timing circuits

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Investigation of Methods for Expanding the Application of Integration Neural Network and Their Appropriate Structures

Investigation of Methods for Expanding the Application of In...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Yoshiharu Iwata Hidefumi Wakamtsu Osaka University Graduate School of Eng. Osaka Japan

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

simulation-based optimization is increasingly used in the thermal design of power devices. However, using highly accurate simulations such as FEM often takes too much time and makes sufficient optimization difficult. Therefore, surrogate model construction, which reduces the simulation time, is attracting attention. To address this problem, we focused on integration neural networks (INNs), which can construct highly accurate surrogate models with a small amount of training data by integrating deductive and inductive models. However, existing INNs cannot be applied as deductive models; they are only models that can be expressed by multiple regression analysis. Therefore, we extended the functionality of INNs to a model that can multiply and divide polynomial equations. As a result, we were able to construct a model with a coefficient of determination of 0.98 for the FEM simulation model.

关键词： Analytical models Thermal expansion Accuracy Neural networks Mathematical models Data models Finite element analysis Thermal analysis Regression analysis Integrated circuit modeling

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Investigation of Self-Heating Effect on the Void Embedded SOI MOSFETs

Investigation of Self-Heating Effect on the Void Embedded SO...

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IEEE Electron Devices Technology and Manufacturing conference (EDTM)

作者： Yizhan Liu Xiaoyan Liu School of Software and Microelectronics Peking University Beijing China School of Integrated Circuits Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

Self-heating effect (SHE) in void embedded SOI (VESOI) MOSFET was analyzed using 3-D finite-element modeling (FEM) simulation. The induced void under the silicon channel improved short channel effect (SCE), however, degraded the thermal performance. The impacts of related device geometry and process fluctuation are investigated to provide guidelines for mitigating the self-heating effect in device design, as the scaling-down of the device. The results indicate that the embedded void has a significant impact on device lattice temperature.

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