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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Characterization and modeling of Thin Film Interface Strength Considering Mode Mixity

Characterization and Modeling of Thin Film Interface Strengt...

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Electronic Components and Technology conference (ECTC)

作者： A. Xiao L. G. Wang W. D. van Driel L. J. Ernst O. van der Sluis D. G. Yang G. Q. Zhang Delft University of Technnology Delft Netherlands NXP Semiconductors Research Nijmegen Netherlands

Interfacial delamination is a common cause of failure in microelectronic packages. Characterization and prediction of interface behavior in manufacturing, testing and application conditions is demanded in order to reduce development times and costs of IC packages. In the design processes of microelectronics, possible interface delamination is evaluated by the critical energy release rate to detach the materials. This critical energy release rate can be obtained experimentally using various approaches. However, its measurement is complicated due to the fact that adhesion strength is not only temperature and moisture dependent but also stress state (mode mixity [1]) dependent. This paper describes our efforts on interface characterization as a function of mode dependency. A new test setup is designed and built. It allows transferring two separated loads on a single specimen. The test methodology that is developed in this paper is also able to evaluate the interfacial fracture toughness as function of temperature and moisture. The crack length, necessary for calculation of the energy release rate is measured by means of an optical microscope. Finite element simulation is used to interpret the experimental results and thus to establish the critical energy release rates and mode mixities.

关键词： Transistors Delamination microelectronics Packaging Moisture Optical microscopy Manufacturing Integrated circuit testing Costs Application specific integrated circuits

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The design and optimization of gain-boosted OTA for high speed and high accuracy sample and hold amplifier

The design and optimization of gain-boosted OTA for high spe...

引用

2007 7th International conference on ASIC Electronic Version(ASICON 2007)

作者： Liu Zao,Cheng Jun,Zhang Hong,Chen Guican Department of microelectronics,Xi'an Jiaotong University,710049

In this paper,a systematical method of designing a high gain and high speed gain-boosted operational transconductance amplifier(gain-boosted OTA) is introduced through mathematically modeling its small signal equivalent circuits in a simple and useful *** applying root locus techniques to the conclusion of this model,two different ways of optimizing the performance of the gain-boosted OTA are *** verifying the design methods,SMIC 0.18μm CMOS technology and 1.8V supply voltage are applied to implement this high gain and high speed *** simulation results show that the output of the sample and hold amplifier(SHA) using these OTAs has minimized ring and overshoot,achieving SNR over 100dB and SNDR over 70dB with 39.9MHZ sinusoid input,and at the higher frequency region,with input signal of 79.9MHZ,the SNR over 81dB and SNDR over 63dB can be achieved.

关键词： SHA The design and optimization of gain-boosted OTA for high speed and high accuracy sample and hold amplifier OTA

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A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC simulation of MPSoCs

A Fully Static Scheduling Approach for Fast Cycle Accurate S...

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2007 International conference on microelectronics (ICM'07)

作者： Richard Buchmann Alain Greiner LIP6/UPMC Université Pierre et Marie Curie Paris France

This paper presents principles and tools to facilitate Multi-Processor System on Chips (MPSoCs) design and modeling, and to speed up cycle accurate SystemC simulation. We describe an effective way to build an hardware architecture virtual prototype, using a library of SystemC simulation models based on communicating synchronous finite state machines. This modeling approach supports a fully static scheduling strategy, based on the analysis of the combinational dependency graph. Our static scheduling algorithm has been implemented in the SystemCASS simulator, and provides speed-up of one order of magnitude versus the standard event-driven SystemC simulation engine. The modeling approach proposed in this paper has been adopted by the SoCLIB french national project, that is an open modeling and simulation platform for multi-processors system on chips.

关键词： Computational modeling Hardware Job shop scheduling Virtual prototyping Discrete event simulation Dynamic scheduling Signal processing System-on-a-chip Libraries Automata

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Study of Two Control Strategies Based in Fuzzy Logic and Artificial Neural Network Compared with an Optimal Control Strategy Applied to a Buck Converter

Study of Two Control Strategies Based in Fuzzy Logic and Art...

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conference of the North American Fuzzy Information Processing Society - NAFIPS

作者： N. L. Diaz J. J. Soriano Laboratory for Automation Microelectronics and Computational Intelligence Universidad Distrital Francisco José de Caldas Bogota Colombia

The dc-dc converters are highly efficient tools used to supply power to different systems, they have a nonlinear behavior and variations at their main parameters could affect their stability. This document studies and compares different control strategies, linear and non linear controllers applied to a Buck converter. There are mainly three control strategies treated in this paper. First an optimal control based design, by employing The quadratic performance index (QPI) is used, second a knowledge based fuzzy control is studied and third an artificial neural network (ANN) as a dynamic emulator of the fuzzy control is proposed. Some comparisons about the systems composed by the plant and a controller, in variation of a few plant parameters were made; in addition the computational time in simulation is compared between the two intelligent controllers.

关键词： Optimal control Fuzzy logic Artificial neural networks Buck converters Fuzzy control DC-DC power converters Power supplies Stability Performance analysis Computational modeling

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Computing Systematic Offset in Amplifiers Using Hierarchical Graph-Based Sizing and Biasing

Computing Systematic Offset in Amplifiers Using Hierarchical...

引用

2007 International conference on microelectronics (ICM'07)

作者： Ramy Iskander Marie-Minerve Louerat Andreas Kaiser LIP6-SOC Laboratory Université Pierre et Marie Curie Paris France ISEN Department I.E.M.N Lille France

A hierarchical graph-based sizing and biasing method of analog circuits has been previously developed. However, conflicts appear in dependency graphs generated by our method due to the large number of degrees of freedom in analog design. Therefore, an enhanced method is presented that automatically detects conflicts and resolves them by inserting systematic offset voltages as additional degrees of freedom into the graph. During graph evaluation, a systematic offset is evaluated as the voltage difference between conflicting nodes, which can be eliminated by transposing it to the inputs of the circuit. As an example, we have successfully applied our method to the sizing of a single-ended two-stage operational amplifier.

关键词： Analog circuits Circuit synthesis Equations Voltage Hardware design languages Laboratories Operational amplifiers Computational modeling Circuit simulation Analog computers

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VCSEL device modeling and parameter extraction technique

VCSEL device modeling and parameter extraction technique

引用

14th IEEE International conference on Electronics, Circuits and Systems (ICECS 2007), vol.1

作者： K. Minoglou G. Halkias E. D. Kyriakis-Bitzaros D. Syvridis A. Arapogianni NCSR-Demokritos Institute of Microelectronics Athens Greece Department of Electronics TEI of Pireaus Egaleo Athens Greece Department of Informatics and Telecommunications University of Athens Athens Greece

An efficient model scheme that combines the nonlinear behaviour of the input parasitics with the intrinsic fundamental device rate equations of the Vertical Cavity Surface Emitting Lasers (VCSELs) is proposed. The model parameter values are extracted using a fully defined systematic technique from dc current-optical power-voltage (I-L-V) and ac S{sub}11-S{sub}21 response measurements. Extraction and simulation procedures are implemented in commercial integrated circuit design tools. Investigation on their accuracy and efficiency is performed by comparing simulation results with the experimental measurements.

关键词： Vertical cavity surface emitting lasers Parameter extraction Power system modeling Integrated circuit measurements Circuit simulation Nonlinear equations Laser modes Surface emitting lasers Current measurement Integrated circuit synthesis

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design of A Voltage Comparator using for Switching Regulator

Design of A Voltage Comparator using for Switching Regulator

引用

7th International conference on ASIC (ASICON 2007), vol.2

作者： Yuanjie Bin Feng Quanyuan Institute of Microelectronics Southwest Jiaotong University Chengdu Sichuan China

In this paper, a comparator used for switching regulator is presented. This design uses a bias stage with the structure of negative feedback to get more stable DC bias voltages. The comparator is formed by 3 stages: input stage, a emitter coupled differential pair;middle stage, a folded cascode amplifier and output stage be consisted by a Active Load Inverter. These simulation result shown in this paper is got by Hspice with a 0.6um CMOS technologies and 3.6V power supply.

关键词： Voltage Regulators Negative feedback CMOS technology Power supplies MOSFETs Circuits Delay Power dissipation Semiconductor device modeling

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POSIX modeling in SystemC 06

POSIX modeling in SystemC

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ASP-DAC 2006: Asia and South Pacific design Automation conference 2006

作者： Posadas, Hector Aádamez, Jesuás Saánchez, Pablo Villar, Eugenio Blasco, Francisco Microelectronics Engineering Group University of Cantabria Santander Spain DS2 Valencia Spain

ISBN: (纸本)0780394518

Early estimation of the execution time of Real-Time embedded SW is an essential task in complex, HW/SW embedded system design. Application SW execution time estimation requires taking into account the impact of the underlying RTOS. As a consequence, RTOS modeling is becoming an active research area. SystemC provides a framework for multiprocessing, HW/SW co-simulation at several abstraction levels. In this paper, a SystemC library for POSIX modeling and simulation is presented. By using the library, the SystemC specification using POSIX functions is converted automatically into a timed simulation estimating the execution time of the application SW running on the POSIX platform. The library works directly on the source code. Therefore, it provides an early and fast estimation of the performance of the system as a consequence of the architectural mapping decisions. Although accuracy is lower than when using lower-level techniques, it supports high-level design-space exploration as simulation time is significantly less than RT (ISS) simulation1. © 2006 IEEE.

关键词： Embedded systems

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Word level functional coverage computation 06

Word level functional coverage computation

引用

11th Asia and South Pacific design Automation conference

作者： Alizadeh, Bijan Microelect Res & Dev Ctr Iran Tehran Iran

ISBN: (纸本)0780394518

This paper proposes a word-level coverage metric to determine the completeness of a set of properties verified by a word-level method. An algorithm is presented to compute a functionality based coverage metric for a sequence property as specification. Control, intermediate and output signals are represented by a multiplexer based structure of linear integer equations, and RT level properties are directly applied to this representation. A set of integer equations are symbolically simulated based on the specified property in a predictable time. We used a canonical form of linear Taylor Expansion Diagram.

关键词： Data structures Boolean functions Circuit simulation Logic Equations Computational modeling Taylor series microelectronics Research and development Multiplexing

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UWB receiver design and two-way-ranging simulation using VHDL-AMS

UWB receiver design and two-way-ranging simulation using VHD...

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2nd conference on Ph D Research in microelectronics and Electronics

作者： Crepaldi, Marco Casu, Mario R. Graziano, Mariagrazia Zamboni, Maurizio Politecn Torino VLSI Lab Dipartimento Elettr Turin Italy

ISBN: (纸本)1424401569

Utra-Wide Band (UWB) impulse radio systems are appealing in location aware applications because of the high resolution of the measurement of pulses Time-Of-Flight (TOF). This paper describes a complete UWB receiver for indoor localization based on the non-coherent Energy Detection approach, and the simulation of a Two-Way-Ranging (TWR) Time-Of-Arrival (TOA) scheme between two transceivers. This is done with the aid of the design flow provided by the ADVanceMS simulator and the VHDL-AMS modeling language. The tool is suitable for every application aimed at the integration of mixed-signal Systems on Chips (SoC) allowing successive refinement steps starting from the VHDL-AMS models of the analog front-end and going down to their equivalent Spice/Spice-RF models. The complete VHDL/VHDL-AMS receiver model is described and, in order to validate the simulation tool, preliminary results obtained with the Alt. PHY UWB 802.15.3 indoor channel model are presented.

关键词： Radio systems

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