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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是1051-1060 订阅

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Chapter 13, Thermal modeling and characterization in microelectronics

Chapter 13, Thermal modeling and characterization in microel...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

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modeling leakage in ASIC libraries

Modeling leakage in ASIC libraries

引用

Custom Integrated Circuits conference (CICC)

作者： S. Lichtensteiger L. Wissel J. Engel P. Sulva IBM Microelectronics Essex Junction VT USA

Leakage is one of today's most important VLSI design issues, and ASIC design tools require accurate library leakage models. Leakage models have been traditionally derived from Spice simulation, but this approach is difficult and inflexible. Further, Spice simulation may not be possible for all IP in the library. We propose a new approach to modeling leakage of ASIC libraries. This approach is simple and flexible, and it is viable for all IP in the library. It requires no Spice simulation, yet its accuracy has been verified in silicon. It has been implemented for our 90nm ASICs

关键词： Application specific integrated circuits Libraries Subthreshold current Temperature dependence Physics FETs microelectronics Very large scale integration Silicon Electronic design automation and methodology

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Fracture mechanics based crack and delamination risk evaluation and RSM/DOE concepts for advanced microelectronics applications

Fracture mechanics based crack and delamination risk evaluat...

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6th International conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in Micro-Electronics and Micro-Systems

作者： Auersperg, J Seiler, B Cadalen, E Dudek, R Michel, B Fraunhofer Inst Reliabil & Microintegrat Berlin Dept Mech Reliabil & Micro Mat IZM D-13355 Berlin Germany

ISBN: (纸本)0780390628

Fatigue and failure of advanced electronic packages and related systems is often caused by their increasing use under harsh environmental conditions - extreme temperatures, in particular. As a result, its thermomechanical reliability becomes more and more one of the most important preconditions for adopting it in industrial applications. Residual stresses from several steps of the manufacturing process, thermal and static and dynamic mechanical loading conditions along with the fact that microelectronic packages are basically compounds of materials with quite different Young's modules and thermal expansion coefficients contribute to interface delamination, chip cracking and fatigue of interconnects. Consequently, numerical investigations by means of nonlinear parameterized FEA, fracture mechanics concepts are frequently used for design optimizations using sensitivity analyses [1]. So, numerical design studies can help to optimize designs of electronics applications at the earlier phase of the product development processes. Unfortunately, this methodology typically accounts for classical stress/strain evaluation or life time estimations of solder interconnects using modified Coffin-Manson approaches. Delamination or bulk fracture mechanisms usually remain unconsidered. This contribution intends to figure out and discuss ways of using fracture mechanics numerical approaches in connection with parameterized FEA based DOE/RSM. For improving such methods, the evaluation of mixed mode interface delamination phenomena of several ceramics/encapsulant-specimens under bending has been combined with experimental deformation measurements. Measured force vs. deflection curves, deformation fields as results of optical inspection and deformation analysis as well as crack tip vs. deflection curves determined using constitute the input for the delamination modeling by means of FEM. Major goal of the study is to make such a way determined interface toughness parameters applicable wit

关键词： Electronics packaging

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Distortion analysis of three-stage amplifiers with reversed nested-Miller compensation

Distortion analysis of three-stage amplifiers with reversed ...

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European conference on Circuit Theory and design, ECCTD

作者： S.O. Cannizzaro G. Palumbo S. Pennisi DIEES (Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi) Universita Catania Italy

A theoretical evaluation of high-frequency distortion of three-stage amplifiers adopting the reversed nested Miller compensation is presented. The inherent computation complexity is reduced by exploiting a suitable amplifier model, and the nonlinear contribution of each stage is enucleated. Transistor-level simulations on a CMOS circuit are found to be in very good agreement with expected results.

关键词： Harmonic distortion Capacitors Semiconductor device modeling Voltage Computational modeling Linearity Operational amplifiers Nonlinear distortion Circuit simulation microelectronics

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design and Simulated Annealing Optimization of a Static Comparator for Low-Power High-Speed CMOS VLSI

Design and Simulated Annealing Optimization of a Static Comp...

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International conference on microelectronics, ICM

作者： B. Kheradmand-Boroujeni K. Shojaee A. Afzali-Kusha Low-Power High-Performance NanoSystems Laboratory Electrical and Computer Engineering Department Faculty of Engineering University of Tehran Tehran Iran

In this work, we present a new architecture for designing static low-power high-speed comparators based on tristate buffers. The delay of this structure is a logarithmic function of the fan-in. With a minor modification, the circuit can be optimized for high speed or low power operation. The performance of the circuit has also been optimized using simulated annealing method. To assess the efficiency of the comparators, they have been simulated in a 100nm CMOS technology. The results for VDD = 1V show a maximum delay of 302ps (570ps) and a power consumption of 614μw (150μw) for a 64 bit high-speed (low-power) comparator at 2GHz. Compared to a conventional tree comparator, the high-speed (low-power) circuits show a 9 (10) times better energy delay product (EDP).

关键词： Simulated annealing design optimization Very large scale integration Delay Energy consumption design engineering Circuit simulation CMOS technology design methodology Computational modeling

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3D TCAD simulation of nanoscale Multi-Gate FETs (MuGFETs)

3D TCAD Simulation of nanoscale Multi-Gate FETs (MuGFETs)

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International conference on microelectronics, ICM

作者： M. Nawaz Infineon Technologies Munich Germany

Aggressive scaling of bulk MOS device dimensions has been the major contributor driving improvements in integrated circuit performance. Due to limitations on gate oxide thickness, and source/drain junction depth, further scaling of MOSFET devices in the sub-50 nm process generation will be difficult, if not impossible. New device architecture and new material combinations are therefore needed to overcome technological challenges. Despite the added process complexity, double (FinFET) or triple (Tri-Gate) gate Multi-Gate FET (MuGFET) devices are emerging as strong candidates for low power or high performance applications in the future. This work report on the theoretical design evaluation of MuGFETs using commercial three-dimensional (3D) TCAD simulation tool. Because of three dimensional geometry of MuGFETs and complex channel profiles required to adjust the threshold voltage beyond 50 nm gate length, conventional 1D or 2D TCAD (process and device simulation) simulations are not directly applicable and hence not suited well from the point of view of accuracy and predictability. All critical process steps (i.e., channel implant, gate oxide growth, extension implant, halo implant, spacer formation and source-drain implant) for tri-gate MuGFETs on standard SOI have been included in the process simulation. The total number of mesh points for the half-device was approximately 180,000, while the processing time was 10-12 hours. Device simulations have been performed using drift diffusion model taking into account quantum confinement effects, bandgap narrowing effects, low field (doping and temperature dependence) and high field mobility models including surface scattering model of Lombardi.

关键词： FETs Implants Semiconductor process modeling Solid modeling Predictive models Circuit simulation MOS devices MOSFET circuits Integrated circuit technology FinFETs

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Recent advances in verification, equivalence checking & SAT-solvers

Recent advances in verification, equivalence checking & SAT-...

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International conference on VLSI design

作者： D. Pradhan M. Abadir M. Varea Department of Computer Science University of Bristol Bristol UK Motorola Inc. USA University of Southampton UK

design flow, RTL-verification, simulation-based techniques, basic concepts of equivalence checking, combinational equivalence checking, ATPG-based techniques, compare point matching, mitering, don't cares, solver overview (structural verification, BDD-based solvers, SAT-based solvers), decision diagrams (BDDs, zBDDs, word-level DDs). Also covered are concepts in SAT solvers (backtrack-search algorithm, effective techniques, including nonchronological backtracking & Boolean constraint propagation), new EDA-related techniques (covering immediate implications, partial-clauses, local decisions & partial clauses). Finally, the tutorial gives an overview of various commercially available tools, & their applicability. Also discussed are future challenges, such as design for verifiability & potential new directions.

关键词： Computer science Data structures Boolean functions microelectronics Embedded system USA Councils Computational modeling Computer simulation Books Engineering management

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Bridging circuits and electromagnetics in a curriculum aimed at microelectronic analog and microwave simulation and design

Bridging circuits and electromagnetics in a curriculum aimed...

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IEEE International conference on Microelectronic Systems Education

作者： V. Jandhyala Y. Kuga D. Allstot C.J.R. Shi Department of Electrical Engineering University of Washington Seattle WA USA

Higher operating frequencies and increased integration have led to electromagnetic effects being ubiquitous in microelectronics for digital, analog, and RF applications at the board, package, and chip levels. Classical curricula have tended to teach circuits and electromagnetics as two distinct areas. This paper presents courses at the University of Washington that aim to bridge the circuit-electromagnetic gap by teaching electromagnetics top-down "on demand" i.e. at the level of complexity required for a given application rather than the bottom-up approach of classical electromagnetics that did not necessarily mesh well with circuits curricula.

关键词： Microwave circuits microelectronics Circuit simulation Electromagnetics Multiconductor transmission lines Transmission line matrix methods Distributed parameter circuits Mathematical model Computational modeling Power system transients

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Wireless Hearing Aids System simulation

Wireless Hearing Aids System Simulation

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Asilomar conference on Signals, Systems & Computers

作者： H.K. Garg Tang Bin Zhang Liang R.S. Rana Department of Electrical & Computer Engineering National University of Singapore Singapore 11 Science Park Road Institute of Microelectronics Singapore Graduate Program in Bioengineering National University of Singapore Singapore

Although wireless hearing aid systems have been proposed by several research groups, no viable whole-system simulation results have been reported so far for better evaluation of this advanced hearing device. In this paper, a system-level simulation using ADStrade is presented based on one of the typical wireless hearing aid architecture. The results show that the wireless hearing aid system function can be simulated and verified. And from these results, we can get a very promising performance which can be used for further design

关键词： Hearing aids Auditory system Circuit simulation Radio frequency Noise cancellation Mathematical model Costs RF signals Signal processing Computational modeling

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Computer simulation of Germanium Nanowire Field Effect Transistors

Computer Simulation of Germanium Nanowire Field Effect Trans...

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International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yiming Li Hung-Mu Chou Bo-Shian Lee Chien-Sung Lu Shao-Ming Yu Microelectronics and Information Systems Research Center National Chiao Tung University Hsinchu Taiwan Microelectronics and Information Systems Research Center National Chiao Tung University Taiwan Department of Electrical Engineering National Central University Taiwan

In this paper, electrical characteristics of germanium (Ge) nanowire field effect transistors (FETs) are computationally investigated. A calibrated three-dimensional (3D) density-gradient simulation is performed to explore the electrical characteristics of Ge omega-shaped-gate FETs. The examined nanodevices are with a 70% gate coverage ratio. By evaluating the threshold voltage roll-off, the transfer characteristics, and the leakage current, our numerical results have shown that the Ge nanowire FET has potentially higher driving-capability than that of the silicon (Si) one. Due to good channel controllability of the omega-shaped-gate FET with the 70% gate coverage ratio, compared with the Si nanowire FET, the high mobility Ge nanowire FET significantly suppresses the effect of band-gap narrowing on the transport characteristics. Leakage current of the Ge nanowire FET depends upon the thickness of the gate channel film. A thinner Ge film leads to a lower leakage current. Preliminary numerical study on the Ge Nanowire FET with a propoer selection on gate material provides interesting results for the design and fabrication of high performance nanodevices in nanoelectronics era.

关键词： Computer simulation Germanium FETs Leakage current Electric variables Computational modeling Threshold voltage Silicon Controllability Photonic band gap

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