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IEEE International Behavioral modeling and simulation conference

作者： Zhang, H Doboli, A SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA

ISBN: (纸本)0780386159

This paper presents a method for fast time-domain simulation of analog systems with nonlinear parameters. Specifically, the paper focuses on Sigma-Delta analog-to-digital converters (ADC). The method generates compiled-code simulators based on symbolic analysis. Code is optimized using loop invariant elimination, and constant folding. Circuits are described as structural macromodels. Nonlinear parameters are expressed using piecewise linear (PWL) models. The paper presents a technique for automatically creating PWL models through model extraction from trained neural networks (NN). As compared to existing behavioral simulation methods for Sigma-Delta ADC, this technique is fully automated and more accurate. In our experiments, compiled-code simulation was about 100x faster than Spectre (numerical) simulation.

关键词： microelectronics

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modeling of TE cooling of pump lasers

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IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES 2004年第4期27卷 724-730页

作者： Labudovic, M Li, J Optovia Corp Acton MA 01720 USA Univ Massachusetts Lowell Photon Ctr Lowell MA 01854 USA

The pump laser is a key module in optical amplifiers for long-haul fiber optic telecommunication systems. Its core component is a semiconductor laser diode mounted on a thermoelectric cooler. It is of crucial importance to maintain the laser diode temperature in a narrow range during operation in order to achieve satisfactory performance and reliability of the module. Therefore, a proper thermal management solution is very important to the pump module design. In this paper, a three-dimensional finite element analysis on thermoelectric cooling is presented. The modeling results show good agreement with the experimental results obtained by IR thermometry. When the heat source has a high power dissipation and a small footprint compared to the size of the heat sink, the spreading resistance becomes important. To analyze the maximum performance of the heat sink, both single and dual pump module configurations are considered.

关键词： finite element model (FEM) heat transfer pump laser thermoelectric cooler (TEC)

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From chemical building blocks of polymers to microelectronics reliability

From chemical building blocks of polymers to microelectronic...

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5th International conference on Thermal and Mechanical simulation and Experiments in microelectronics and Microsystems

作者： Bressers, HJL van Driel, WD Jansen, KMB Ernst, LJ Zhang, GQ ATO Innovat Philips Semicond NL-6534 AE Nijmegen Netherlands

ISBN: (纸本)0780384202

Among various materials, polymers are widely used in microelectronics as different product constituents, such as encapsulants, conductive or non-conductive adhesives, underfills, molding compounds, insulators, dielectrics, and coatings. The behavior of these polymer constituents determines the performance, such as functionality and reliability, of the final products. Therefore, the successful development of microelectronics depends on, to some extend, the optimal design and processing of polymer materials. Due to the development trends of microelectronics, characterized mainly by ongoing miniaturization down to the nano scale, technology & functionality integration, eco-designing, shorter-time-to-market, development and application of polymers become one of the bottlenecks for the microelectronic industry. Aiming at optimizing the product/process development, much effort is directed to understanding and designing polymer behavior in microelectronics, such as in material pre-selection, processing, characterization and modeling. Although these efforts are necessary, the ultimate benefits can only be realized if the relationship between chemistry and the behavior can be understood and predicted. This paper presents some results of our effort to establish the links between chemical details of the polymers and microelectronics reliability.

关键词： microelectronics

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Reliability analysis and design for the fine-pitch flip chip BGA packaging

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IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES 2004年第4期27卷 684-693页

作者： Peng, CT Liu, CM Lin, JC Cheng, HC Chiang, KN Natl Tsing Hua Univ Dept Power Mech Engn Adv Microsyst Packaging & Nanomech Res Lab Hsinchu 300 Taiwan Feng Chia Univ Dept Aeronaut Engn Taichung 40724 Taiwan

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively, investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.

关键词： accelerated thermal cycling testing daisy chain finite element modeling flip chip BGA parametric design reliability

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Voltage and sizing optimization for low power buffered digital designs

Voltage and sizing optimization for low power buffered digit...

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16th International conference on microelectronics, ICM 2004

作者： Farbiz, F. Behnam, A. Emadi, M. Esfandiarpoor, B. Kusha, A. Afzali Device Modeling and Simulation Lab ECE Dept. University of Tehran Tehran Iran

A circuit design style with separate logic and buffer tages is investigated for its energy and delay characteristics. Then a new numerical approach is proposed for determining the optimum transistor sizing and supply voltage according to the minimum energy-delay product as a figure of merit (FOM). The results agree perfectly with the simulation data gathered from the SPICE simulation and are much more accurate than the ones proposed in the previous works. ©2004 IEEE.

关键词： Buffer circuits

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Challenges of thermomechanical design and modeling of ultra fine-pitch wafer level packages

Challenges of thermomechanical design and modeling of ultra ...

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Proceedings of the 5th International conference on Thermal and Mechanical simulation and Experiments in microelectronics and Microsystems, EuroSimE 2004

作者： Tay, Andrew A.O. Nano/Microsyst. Intgn. Laboratory Department of Mechanical Engineering National University of Singapore

ISBN: (纸本)0780384202

With the relentless trend towards ever increasing number of I/Os of IC chips, the pitch of chip-to-substrate interconnections are ever decreasing. As the pitch is decreased so also will be the stand-off. If the coefficient of the thermal expansion of the chip and substrate remains the same, and the temperature cycling range remains the same, the stresses and strains induced in the interconnections will increase dramatically. This will probably decrease the fatigue life of the interconnections to an unacceptably low level unless novel designs and materials can be produced to address the problem. This paper describes the challenges in the design and thermomechanical modeling of the reliability of the next generation ultra fine-pitch wafer level packages. Three designs of interconnections at 100μm pitch for 20mm × 20mm wafer level packages are proposed and modeled. Two thermomechanical modeling approaches, namely, the Equivalent Beam Approach and the Small Sector Approach, have been developed to perform the the effective modeling of 40,000 interconnections per package. It was found that the key parameter is the coefficient of thermal expansion of the board which has to be made to match closer to that of the silicon chip in order to meet current reliability standards.

关键词： Chip scale packages

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Effect of metal layout design on passivation crack occurrence using both experimental and simulation techniques

Effect of metal layout design on passivation crack occurrenc...

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5th International conference on Thermal and Mechanical simulation and Experiments in microelectronics and Microsystems

作者： van Silfhout, RBR van Driel, WD Li, Y van Gils, MAJ Janssen, JHJ Zhang, GQ Tao, G Bisschop, J Ernst, LJ Philips CFT Ctr Ind Technol NL-5600 MD Eindhoven Netherlands

ISBN: (纸本)0780384202

Thermo-mechanical reliability is one of the concerns for semiconductor developments due to miniaturization introduction of new materials, and higher application temperatures. FE modeling techniques are developed to predict the effect of IC interconnect metal designs on the thermo-mechanically-induced cracking of passivation layers. Experimental techniques on specially designed IC packages are developed to verify the predicted passivation cracks. With the verified 2D and 3D models, various simulations are performed and it is established that delamination of IC/compound interface is a key trigger for passivation cracking. When delamination is present, crack occurrence is found to depend on the metal layout and location on the IC. Optimizing the metal layout design can even prevent passivation cracks. By combining efficient & accurate simulations with a limited number of experiments, passivation crack can be quantitatively predicted prior to physical prototyping.

关键词： Integrated circuit layout

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Prediction of thermo-mechanical integrity of wafer backend processes

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microelectronics RELIABILITY 2004年第12期44卷 2011-2017页

作者： Gonda, V Den Toonder, JMJ Beijer, J Zhang, GQ van Driel, WD Hoofman, RJOM Ernst, LJ Delft Univ Technol NL-2628 CD Delft Netherlands Philips Ctr Ind Technol NL-5600 MD Eindhoven Netherlands Philips Res Labs NL-5656 AA Eindhoven Netherlands Philips Res Leuven B-3001 Louvain Belgium

More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase the importance of thermomechanical reliability, as confirmed by the ITRS (International technology roadmap for semiconductors;[1]). Since most of the thermomechanical problems initiate in the design phase, failure prevention-designing for reliability, is strongly desired. To support wafer backend process development, it is necessary to develop reliable and efficient methodologies (both testing and modeling) to predict the thermal and mechanical behavior of backend processes. This paper presents our research results covering the backend process reliability modeling considering both thermal and mechanical (CMP) loading. The emphasis is particularly on the effect of using Cu/SiLK low-dielectric-constant (low-k) structure instead of the traditional Al/SiO2. SiLK is a particular polymeric low-k material developed by the Dow Chemical Company [2] [Adv. Mater. 12 (2002) 1767]. Our results shows that Cu/SiLK structures exhibit significantly different reliability characteristics than their aluminum predecessors, and that they are more critical from several design aspects. This not only makes the stress management in the stacks more difficult, but also strongly impacts packaging. (C) 2004 Elsevier Ltd. All rights reserved.

关键词： microelectronics SEMICONDUCTORS ALUMINUM ELECTRIC conductivity

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Hardware description language modeling of an electrostatically actuated Bi-axial micromirror

Hardware description language modeling of an electrostatical...

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Proceedings of the 5th International conference on Thermal and Mechanical simulation and Experiments in microelectronics and Microsystems, EuroSimE 2004

作者： Parrain, Fabien Megherbi, Souhil Raynaud, Gilles Mathias, Hervé Gilles, Jean-Paul Bosseboeuf, Alain Schröpfer, Gerold Faure, Nicolas Cusin, Pierre Institut d'Electronique Fondamentale UMR 8622 Bât. 220 F 91405 Orsay Cedex France Coventor Sari 3 ave. Quebec ZI de Courtaboeuf F 91140 Villebon France Colibrys SA Maladière 83 CH 2007 Neuchâtel Switzerland

ISBN: (纸本)0780384202

Recent developments in Micro-Electro-Mechanical System (MEMS) and micromachining technologies have made possible the development and the integration of micromirrors that can be employed for a number of consumer applications such as free space optical switching, 2D scanning or image projection. This high level of integration provides many advantages such as reproductivity and improved performance. Obviously these increased levels of miniaturization raise new characterization and modeling concerns. We present in this paper the design, the fabrication process, the characterization and the behavioral modeling approach of a novel electrostatically actuated bi-axial micromirror. This MOEMS is a result of a joint development between our partners Colibrys and Coventor companies. In the field of this work two HDL multi-physics models using Verilog-A language and Matlab have been developped and validated by different experimental measurements.

关键词： Mirrors

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modeling of integrated monolithic transformers for silicon RF IC

Modeling of integrated monolithic transformers for silicon R...

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11th IEEE International conference on Electronics, Circuits and Systems, ICECS 2004

作者： Gharniti, Ouail E.L. Kerhervé, Eric Bégueret, Jean-Baptiste Jarry, P. IEEE Microelectronics IXL Laboratory ENSEIRB University of Bordeaux France

ISBN: (纸本)0780387155

We present a compact and scalable model for on-chip transformers fabricated in silicon IC technology. The model is driven from the layout and the process technology specifications. It is suitable for design optimization and circuit simulation. EM-simulation is used to validate the model. The proposed model shows excellent agreement with EM-simulation over a large frequency range(1-15GHz). © 2004 IEEE.

关键词： Electric transformers

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