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Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

microelectronics RELIABILITY 2004年第12期44卷 1957-1965页

作者： Tee, TY Zhong, ZW STMicroelect Singapore 319521 Singapore Nanyang Technol Univ Sch MPE Singapore Singapore

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables. (C) 2004 Elsevier Ltd. All rights reserved.

关键词： MINIATURE electronic equipment microelectronics TEMPERATURE RELIABILITY (Personality trait)

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Demonstration of a SiGe RF LNA design using IBM design kits in 0.18 /spl mu/m SiGe BiCMOS technology

Demonstration of a SiGe RF LNA design using IBM design kits ...

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design, Automation and Test in Europe conference and Exhibition, DATE 2004

作者： Chen, Yiming Yuan, Xiaojuen Scagnelli, David Mecke, James Gross, Jeff Harame, David IBM Microelectron. Div. San Diego CA United States IBM Microelectronics Division BTV VT United States

ISBN: (纸本)0769520855

A 1.5 GHz-2.0 GHz low noise amplifier (LNA) is designed in IBM 0.18 um BiCMOS technology using IBM design kits in cadence design flow. The fabricated LNA chip is packaged and tested. The measured results (gain, noise figure, and IIP3) correlate with the simulation very well. The results demonstrate that IBM SiGe technology, modeling, design kits and the cadence design flow are solid and accurate for RFIC design. © 2004 IEEE.

关键词： Low noise amplifiers

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Stacked-chip packaging: Electrical, mechanical, and thermal challenges

Stacked-chip packaging: Electrical, mechanical, and thermal ...

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2004 Proceedings - 54th Electronic Components and Technology conference

作者： Awad, Elie Ding, Hanyi Graf, Richard S. Maloney, J.J. IBM Microelectronics 1000 River Street Essex Junction VT 05452

A stacked-chip package offers many benefits, including improved electrical performance (shorter chip-to-chip interconnects), reduced printed circuit board (PCB) area, reduced weight, reduced cost when compared to a multi-package solution, and efficient integration of dissimilar integrated circuit (IC) technologies. The trade-offs to these improvements are the complex electrical, mechanical, and thermal challenges associated with stacked-chip packaging. These challenges put new demands on modeling and analysis capabilities. This paper describes these challenges and how modeling and simulation are used during package design to overcome them while improving overall module performance and reducing the qualification time and overall time to market.

关键词： Electronics packaging

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modeling of cure-induced warpage of plastic IC packages

Modeling of cure-induced warpage of plastic IC packages

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Proceedings of the 5th International conference on Thermal and Mechanical simulation and Experiments in microelectronics and Microsystems, EuroSimE 2004

作者： Yang, D.G. Jansen, K.M.B. Ernst, L.J. Zhang, G.Q. Van Brief, W.D. Bressers, H.J.L. Delft University of Technology Mekelweg 2 2628 CD Delft Netherlands Philips-CFT PO Box 218 5600 MD Eindhoven Netherlands Philips Semiconductors P.O. Box 30008 6534 AE Nijmegen Netherlands

ISBN: (纸本)0780384202

The accurate prediction of warpage induced during manufacturing processes is important for the optimal design of both package structure and process conditions. In this paper, a cure-dependent viscoelastic constitutive model is established to model the cure-induced warpage after the map-mould manufacturing process. In the model, the relaxation moduli of the silica particle -filled polymer during the curing process are considered to be a sum of two parts, i.e. the cure-dependent equilibrium moduli and the transient parts. The equilibrium moduli are modeled with a model based on scaling analysis. The relaxation behavior of the transient part is described by the cure-dependent relaxation amplitude and reduced relaxation times which are based on the time-conversion superposition principle. The cure-dependent parameters are characterized by using an integrated approach of DMA and DSC measurements. The chemical shrinkage strain is measured with an online density measuring setup. The viscoelastic parameter-functions of the resin measured by DMA and DSC have been incorporated in the MARC finite element code. Finite element modeling is carried out for three configurations of a carrier package map-mould and the warpage induced during the curing process and cooling down is predicted. The results show that warpage induced during the curing process has a significant contribution on the total warpage of the map.

关键词： Chip scale packages

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modeling of Integrated Monolithic Transformers for Silicon RF IC

Modeling of Integrated Monolithic Transformers for Silicon R...

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11th IEEE International conference on Electronics, Circuits and Systems, ICECS 2004

作者： EL- Gharniti, Ouail Kerhervé, Eric Bégueret, Jean-Baptiste Jarry, P. Microelectronics IXL Laboratory CNRS UMR 5818 ENSEIRB University of Bordeaux France

ISBN: (纸本)0780387155

We present a compact and scalable model for on-chip transformers fabricated in silicon IC technology. The model is driven from the layout and the process technology specifications. It is suitable for design optimization and circuit simulation. EM-simulation is used to validate the model. The proposed model shows excellent agreement with EM-simulation over a large frequency range(1-15GHz). © 2004 IEEE.

关键词： Silicon

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Thermal modeling for power MOSFETs in DC/DC applications

Thermal modeling for power MOSFETs in DC/DC applications

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5th International conference on Thermal and Mechanical simulation and Experiments in microelectronics and Microsystems

作者： Bulut, Y Pandya, K Vishay Siliconix Inc Santa Clara CA 95054 USA

ISBN: (纸本)0780384202

In today's dc-to-dc converters, power MOSFETs in through-hole packages have almost completely disappeared as the industry moves toward all-surface-mount implementations. This means an increasing demand for power MOSFET packages with a smaller footprint, a lower profile, and lower thermal resistance. While MOSFETs in the D(2)PAK and DPAK packages were able to provide the appropriate level of power dissipation for dc-to-dc applications, their physical size always constrained converter-packaging density. Surface-mount alternatives Such as the SO-8 address the size issue, but their thermal performance is limited by the need to dissipate power through the leads and onto the PCB. One of the principal concerns in dc-to-dc power supply design is controlling heat. By increasing the efficiency of the power switch (MOSFET), it is possible to reduce heat generated, reducing size requirements and the need for heat sinking. An optimal power design distributes power across the dc-to-dc converter to eliminate (or at least greatly reduce) hotspots on the power board. To achieve this, it is critical early in the design phase to understand the thermal effects of critical components. The provision of a heat flow model for the MOSFET, accurately predicting temperature effects for the switching elements on the PCB, will save time in development and allow for optimal space utilization and power component distribution. Recent major developments in silicon technology have helped power MOSFET manufacturers to reduce on-resistance (r(DS(on))) for a given die size to almost negligible levels. MOSFETs for switching applications are now available with silicon resistances around 1 mOmega. Having reached this plateau, attention is now being turned to ways that innovative packaging can be used to improve the overall device thermal performance. A basic measure of a device's thermal performance is the junction-to-case thermal resistance, R-TH,R-JC, which is the thermal resistance between a power MOSF

关键词： MOSFET devices

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Thermal and Mechanical simulation and Experiments in microelectronics and Microsystems - EuroSimE 2004 (IEEE Cat. No.04EX831)

Thermal and Mechanical Simulation and Experiments in Microel...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

The following topics are dealt with: industrial trends; technology developments; virtual thermal mechanical prototyping; thermal mechanical behavior at wafer level; dynamic compact thermal and electro-thermal models; experimental and numerical interaction; modeling and designing of advanced packaging; thermal behavior modeling and characterization; advanced numerical simulation methodologies; small scale thermal and fluid aspects in microsystems; modeling in micro technology; designing for reliability; material characterization and modeling; modeling of MEMS and optical devices; simulation-based thermal design strategies; solder reliability behavior; CFD and FE modeling of thermal performance; micro- to macro-scale thermal design challenges in microelectronics solder fatigue; characterization and modeling of polymer behavior; new developments in microelectronics reliability.

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design and modeling of on-chip electrostatic discharge (ESD) protection structures

Design and modeling of on-chip electrostatic discharge (ESD)...

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International conference on microelectronics, MIEL

作者： J.J. Liou Xiaofang Gao Department of Electrical and Computer Engineering University of Central Florida Orlando FL USA Modeling and Simulation Group Intel Corporation Sacramento CA USA

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a computer-aided design tool for ESD protection design and applications. Specifically, we develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. Experimental data measured from the transmission line pulsing (TLP) technique and human body model (HBM) tester are included in support of the model.

关键词： Electrostatic discharge Protection Biological system modeling design automation Application software Robustness Standards development SPICE Circuit simulation Electrostatic measurements

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Voltage and sizing optimization for low power buffered digital designs

Voltage and sizing optimization for low power buffered digit...

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International conference on microelectronics, ICM

作者： F. Farbiz A. Behnam M. Emadi B. Esfandiarpoor A.A. Kusha Device Modeling and Simulation Laboratory ECE Department University of Tehran Tehran Iran

A circuit design style with separate logic and buffer stages is investigated for its energy and delay characteristics. Then a new numerical approach is proposed for determining the optimum transistor sizing and supply voltage according to the minimum energy-delay product as a figure of merit (FOM). The results agree perfectly with the simulation data gathered from the SPICE simulation and are much more accurate than the ones proposed in the previous works.

关键词： design optimization Delay Logic circuits Logic design Capacitance Threshold voltage Circuit simulation Logic devices Digital circuits Equations

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System design for DSP applications in transaction level modeling paradigm

System design for DSP applications in transaction level mode...

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design Automation conference

作者： A.K. Deb A. Jantsch J. Oberg Department of Microelectronics and Information Technology Royal Institute of Technology Kista Sweden

In this paper, we systematically define three transaction level models (TLMs), which reside at diferent levels of abstraction between the functional and the implementation model of a DSP system. We also show a unique language support to build the TLMs. Our results show that the abstract TLMs can be built and simulated much faster than the implementation model at the expense of a reasonable amount of simulation accuracy.

关键词： Digital signal processing Context modeling Computational modeling design automation design methodology Permission microelectronics Information technology Embedded computing design engineering

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