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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是101-110 订阅

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Investigation of Self-Heating Effect on the Void Embedded SOI MOSFETs

Investigation of Self-Heating Effect on the Void Embedded SO...

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IEEE Electron Devices Technology and Manufacturing conference (EDTM)

作者： Yizhan Liu Xiaoyan Liu School of Software and Microelectronics Peking University Beijing China School of Integrated Circuits Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

Self-heating effect (SHE) in void embedded SOI (VESOI) MOSFET was analyzed using 3-D finite-element modeling (FEM) simulation. The induced void under the silicon channel improved short channel effect (SCE), however, degraded the thermal performance. The impacts of related device geometry and process fluctuation are investigated to provide guidelines for mitigating the self-heating effect in device design, as the scaling-down of the device. The results indicate that the embedded void has a significant impact on device lattice temperature.

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Circuitry of Micro-Power JFET and CMOS Input Differential Stages for Op-Amps on Silicon and Wide-Band Semiconductors

Circuitry of Micro-Power JFET and CMOS Input Differential St...

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2022 International Siberian conference on Control and Communications, SIBCON 2022

作者： Chumakov, Vladislav Prokopenko, Nikolay Titov, Alexey Don State Technical University Rostov-on-Don Russia Don State Technical University Institute for Design Problems in Microelectronics of RAS Zelenograd Rostov-on-Don Russia Southern Federal University Rostov-on-Don Russia

ISBN: (纸本)9781665476287

The study presents an analysis of universal JFET and CMOS differential stages (DS) circuits. Such cascades provide a smaller range of transistor currents (10-100 $\mu$A) compared to classical cascades. The described DSs are implemented on combined process technologies, and therefore can be designed on JFET, BJT or CMOS chips. In addition, gallium arsenide, diamond gallium nitride, thin-film TFT and silicon carbide transistors. A computer simulation of the static modes of the developed DSs and their current dependences is presented. The results of GaAs DS modeling and its frequency dependence are presented. © 2022 IEEE.

关键词： Thin films

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modeling and simulation of Cmut and Pmut Ultrasound Transducers and Package Using a Multiphysics Approach

Modeling and Simulation of Cmut and Pmut Ultrasound Transduc...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Nilavazhagan Subbiah Jash Banker Soundara Pandian Mohanraj Braig Dominik Erhard Landgraf Sebastian Pregl Bassou Khouya Alexandre Halbach Andrew Tweedie Infineon Technologies AG Infineon Technologies Dresden GmbH Quanscient Oy Finland

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

Ultrasound transducers have diverse applications in medical imaging, consumer electronics, and automotive industries, offering advantages such as non-invasive medical imaging, reliable and non-mechanical transduction of input signals. Micro-Electro-Mechanical Systems (MEMS) based ultrasound transducer solutions, including Piezoelectric Micromachined Ultrasound Transducer (PMUT) and Capacitive Micromachined Ultrasound Transducer (CMUT) devices, exhibit superior performance compared to traditional piezo-ceramic based solutions due to their low cost, compact design, high efficiency and wideband operation capability, furthermore monolithic integration with electronics is possible. However, the development of these cutting-edge technologies requires sophisticated simulation tools to understand and manipulate the underlying ultrasound physics, which is essential for engineering applications. The newly developed simulation methodology will be utilized to model three-dimensional arrays of CMUT and PMUT cells. simulations are performed on cutting-edge designs of Infineon-developed chips using the Quanscient Allsolve software. The results obtained through resonance frequency measurements on PMUT devices and CMUT devices will be evaluated and compared with the simulation results obtained using the presented methodology. Additional capabilities on building ultrasound simulation models with multiphysics is elaborated in this work and demonstrated. Projections for further development in the simulation environment are also presented.

关键词： Performance evaluation Micromechanical devices Solid modeling Ultrasonic imaging Transducers simulation Software Resonance Wideband Biomedical imaging

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Prediction of thermo-mechanical properties of PCB conductive layers using convolutional neural networks

Prediction of thermo-mechanical properties of PCB conductive...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Mariia Shevchuk Christian Schipfer Matthias Haselmann Qi Tao Peter Fuchs Polymer Competence Center Leoben Leoben Austria Austria Technologie & Systemtechnik Leoben Austria

Deriving the effective material properties of printed circuit board (PCB) layers is a particular challenge due to the intricate patterns of the conductive artwork. In this paper, we develop a convolutional neural network model to predict the effective orthotropic thermo-mechanical properties of the copper conductive layers of PCBs. To ensure the necessary level of detail for the material modeling, the images of the copper-resin distributions are extracted from the real electronic design files as patches of preselected pixel sizes. For each image, the corresponding homogenized material properties are computed using finite element analyses. After the training process on the formed dataset is completed, the developed model is validated using data unseen during training. The obtained results indicate that the considered approach is suitable for the prediction of the effective orthotropic properties of copper-resin patterns, and moreover, is promising for facilitating present-day time-to-market objectives in the industry.

关键词： Training Computational modeling Thermomechanical processes Printed circuits Predictive models Thermal conductivity Convolutional neural networks

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simulation and Analysis of Microparticles Acoustophoretic Separation in Multi-Channel Lab-Chip Device 16

Simulation and Analysis of Microparticles Acoustophoretic Se...

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IEEE 16th International conference on the Experience of designing and Application of CAD Systems (CADSM)

作者： Klymkovych, Tamara Bokla, Nataliia Matviykiv, Oleh Stakhiv, Volodymyr Lviv Polytech Natl Univ Dept Comp Aided Design Lvov Ukraine

ISBN: (纸本)9781665438940

The separation of Suspended Microparticles based on physical and chemical properties is an essential step in numerous microfluidic applications. Recent research of acoustofluidic effects proves that acoustophoresis is an effective and flexible method for continuous sorting and separation of multiple beads, living cells, and suspended microparticles. The following research dedicated to the novel design of a microparticle sorter consisted of two pairs of IDT electrodes and provided precise sorting capabilities for multi-channel microfluidic structures. modeling and FEM simulation of the soot and fly ash microparticles separation in CAD/CAE tools allow visualizing the multiphysical interactions between fluid flow, standing acoustic waves, and suspended microparticles in microfluidic Lab-chip devices.

关键词： microfluidics Lab-Chip sorting separation microparticles acoustofluidics

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A simple modeling of ferroelectric actuator based on phenomenological model

A simple modeling of ferroelectric actuator based on phenome...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： B.H. Nguyen M. Zunic G.B. Torri V. Rochus Sensor and Actuator Technology Department imec Leuven Belgium

This paper proposes a simplified phenomenological macroscopic model of a nonlinear ferroelectric actuator. The key ingredient of the proposed model is based on the assumption of direct relation between the irreversible strain and irreversible electric field, which not only reduces the number of internal variables but also facilitate finite element formulation. The model is implemented into a finite element framework, in which return mapping algorithm is employed to solve the evolution of internal variable, to simulate a micro-size ferroelectric actuator. Numerical results are compared with experimental data, demonstrating robustness of the proposed model for micro-actuator design.

关键词： Micromechanical devices Actuators Thermal variables measurement Mechanical variables measurement Robustness Numerical models Finite element analysis

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Run-time adaptive hardware accelerator for convolutional neural networks 16

Run-time adaptive hardware accelerator for convolutional neu...

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2021 International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design, SMACD 2021 and 16th conference on PhD Research in microelectronics and Electronics, PRIME 2021

作者： Sestito, Cristian Spagnolo, Fanny Corsonello, Pasquale Perri, Stefania Department of Informatics Modeling Electronics and System Engineering University of Calabria Arcavacata di Rende Italy Department of Mechanical Energy and Management Engineering University of Calabria Arcavacata di Rende Italy

ISBN: (纸本)9783800755899

State-of-the-art Convolutional Neural Networks are characterized by heterogeneous convolutional layers to proper balance accuracy and computational complexity. Run-time adaptive convolution architectures able to process feature maps with kernels of various sizes and strides are highly desirable to achieve a favorable speed/power dissipation balance. This paper presents the design of an adaptive architecture able to manage efficiently convolutional layers with different running parameters. In order to guarantee high resources utilization for all the supported kernel sizes and strides, in contrast with existing competitors, the proposed design combines non-uniform basic blocks differently customized from each other. As a further nice characteristic, the hardware architecture here presented efficiently manages both odd and even kernel sizes, useful in models also requiring transposed convolutional layers. When accommodated within a Xilinx XC7Z045 FPGA SoC device, the proposed engine reaches a peak throughput of 217.2 GOPS and dissipates about 2.75 W at the 150 MHz clock frequency. © VDE VERLAG GMBH.

关键词： System-on-chip

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CCacheSim: A Circuit-Architecture Cross-Level simulation Framework for SRAM-Based in-Cache Computing System Evaluation

CCacheSim: A Circuit-Architecture Cross-Level Simulation Fra...

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IEEE International conference on Computer design: VLSI in Computers and Processors, (ICCD)

作者： Baiqing Zhong Mingyu Wang Yicong Zhang Xiaojie Li Zhiyi Yu School of Microelectronics Science and Technology Sun Yat-sen University China

ISBN: (数字)9798350380408

ISBN: (纸本)9798350380415

SRAM-based Compute-In-Memory (CIM) circuits have demonstrated significant performance and energy efficiency advantages. Although numerous frameworks or tools have emerged for simulating CIM-based systems, most frameworks are tailored for specific DNN accelerators and rarely consider SRAM-CIM solutions in general processor systems because it is difficult to establish an effective mechanism to build the CIM data path to integrate the SRAM-CIM module that is tightly coupled with the cache hierarchy into the system. To address this problem, we propose a circuit-architecture cross-level simulation framework named CCacheSim for in-cache computing system. CCacheSim integrates the simulation of SRAM-CIM circuit timing and energy consumption characteristics, providing circuit-level accuracy evaluation support for in-cache computing system simulations. For the circuit level, the SRAM-CIM model can automatically generate a circuit-level netlist and conduct accurate simulation through corresponding configurations, thus balancing accuracy and agility for early design exploration. For the architectural level, to efficiently support the portable integration of SRAM-CIM module to in-cache computing system, a configurable hardware programming interface is implemented within the cache model to manage the interaction of the control stream between processor and cache for CIM tasks. Moreover, a request queue based access mechanism is proposed to ensure the completeness of the operands required by CIM tasks. To validate the proposed framework, CCacheSim is implemented to simulate varying configurations of in-cache computing systems and SRAM-CIM modules. The results prove that CCacheSim can conduct accurate performance and energy consumption evaluation for given processor architecture with given CIM module. CCacheSim can support flexible and effective design space exploration for in-cache computing system.

关键词： Energy consumption Accuracy Computational modeling Circuits Computer architecture In-memory computing Common Information Model (computing) Space exploration Timing Integrated circuit modeling

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Deductive Matrix Synthesis for Fault simulation

Deductive Matrix Synthesis for Fault Simulation

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International conference on CAD Systems in microelectronics (CADSM)

作者： Wajeb Gharibi Vladimir Hahanov David Devadze Abdullayev Vugar Hacimahmud Svetlana Chumachenko Zaza Davitadze Eugenia Litvinova Ivan Hahanov University of Missouri Kansas City MO USA Design Automation Department Kharkiv National University of Radioelectronics Kharkiv Ukraine Department of Computer Sciences Batumi Shota Rustaveli State University Batumi Georgia Computer Engineering Department Azerbaijan State Oil and Industry University Baku Azerbaijan

Elements of logical vector computing are proposed, which are focused on fault simulation in digital devices. The concept of a logical vector is introduced for simulation of a single fault as addresses. For the first time the method of synthesis of deductive matrices on the logical vector of functionality is considered. The deductive matrix is used to generate tests for diagnosing a functional element and simulating faults to verify the quality of tests. A compact vector form for specifying graph structures is proposed. The advantages of fault simulation on logical vectors are shown, which lies in the high parallelism of processing faults as addresses. All models and methods are original, the validity of which is confirmed by numerous examples of the synthesis of the failure simulation matrix.

关键词： Solid modeling Computational modeling Personal digital devices Parallel processing

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Optimized design of Lower Complexity Reversible Toffoli Gate in QCA Technology

Optimized Design of Lower Complexity Reversible Toffoli Gate...

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microelectronics (IICM), Iranian International conference on

作者： Saeid Seyedi Hatam Abdoli Department of Computer Engineering Faculty of Engineering Bu-Ali Sina University Hamedan Iran

ISBN: (数字)9798331511371

ISBN: (纸本)9798331511388

Every time an advancing technology gets close to reaching a dead end, a new technological revolution is required. CMOS technology serves as the foundation for current VLSI technology. Modern technology built on quantum dot cellular automata (QCA) has been established in response to new problems in the field. The field of QCA is fascinating in nanocomputing technology as it offers a different way to overcome the physical constraints CMOS systems encounter as they continue to reduce in size. QCA provides significant advantages at the nanoscale, including increased packing density, reduced area, much lower power consumption, and faster working speed. Since current logic gates aren't reversible by nature, and so dissipate energy, they aren't energy-efficient or energy-saving. Consequently, much work is needed to produce an efficient model for designing circuits that retain information while dissipating no energy. Power-efficient circuits may be built with increased accuracy, increasing the circuit's lifespan and speed. This study explores using QCA as an implementation technique for building reversible logic gates that are both power and area-efficient, including QCA cells, which result in improved performance in the suggested design. With 14 cells and a 0.02 μm 2 area, the proposed QCA reversible Toffoli gate architecture achieves a notable size decrease over earlier designs. Using a single-layer design methodology, the circuit is designed to maximize efficiency and minimize cell usage. The proposed reversible Toffoli gate has been shown to have improved functionality and efficiency based on simulation findings using the QCA designer simulator version 2.0.3. It is therefore a smart choice for anyone interested in studying nanoscale integrated circuit applications.

关键词： Power demand design methodology Quantum dots Logic gates Very large scale integration CMOS technology Nanoscale devices Energy efficiency microelectronics Integrated circuit modeling

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