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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Y. Bulut K. Pandya Vishay Siliconix Inc. Santa Clara CA USA

In DC-to-DC converters, power MOSFETs in through-hole packages have almost completely disappeared as the industry moves toward all-surface-mount implementations. This means increasing demand for power MOSFET packages with smaller footprint, lower profile, and lower thermal resistance. While MOSFETs in the D/sup 2/PAK and DPAK packages could provide the appropriate level of power dissipation for DC-to-DC applications, their physical size constrained converter-packaging density. Surface-mount alternatives such as the SO-8 address size issues, but their thermal performance is limited by a need to dissipate power through the leads and onto the PCB. One of the principal concerns in DC-to-DC power supply design is controlling heat. By increasing the efficiency of the power switch (MOSFET), it is possible to reduce heat generated, reducing size requirements and need for heat sinking. Optimal power design distributes power across the DC-to-DC converter to eliminate (or at least greatly reduce) hotspots on the power board. To achieve this, it is critical early in the design phase to understand the thermal effects of critical components. The provision of a heat flow model for the MOSFET, accurately predicting temperature effects for the switching elements on the PCB, will save time in development and allow for optimal space utilization and power component distribution. Recent major developments in silicon technology have helped power MOSFET manufacturers to reduce on-resistance (r/sub DS(on)/) for a given die size to almost negligible levels. MOSFETs for switching applications are now available with silicon resistances around 1 m/spl Omega/. Having reached this plateau, attention is being turned to ways that innovative packaging can be used to improve overall device thermal performance. A basic measure of a device's thermal performance is the junction-to-case thermal resistance, R/sub TH,JC/, which is the thermal resistance between a power MOSFET junction and a specified refe

关键词： MOSFETs Thermal resistance Packaging DC-DC power converters Heat sinks Space heating Space technology Silicon Power dissipation Surface resistance

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Random Dopant Induced Threshold Voltage Fluctuations in Double Gate MOSFET's

Random Dopant Induced Threshold Voltage Fluctuations in Doub...

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2004 7th International conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Ling Xia,Xuewen Gan~* Institute of microelectronics,Peking University,Beijing 100871,China

A study by means of analytical modeling and simulation analysis on random dopant induced double gate MOSFET threshold voltage fluctuations is presented. Analytical models describing the standard deviation of threshold voltage distribution associated with dopant fluctuation are *** effects of various double gate MOSFET design parameters,including the doping concentration,oxide thickness,silicon thickness on the threshold voltage fluctuations are *** analytical models predict the general trends in threshold voltage *** effect of dopant position fluctuation is also *** models and simulations show that double gate MOSFET can suppress the impact of random dopant fluctuation on threshold voltage variations compared with single gate MOSFET.

关键词： MOSFET Random Dopant Induced Threshold Voltage Fluctuations in Double Gate MOSFET's

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Thermal testing of a 3-die stacked chip scale package including evaluation of simplified and complex package geometry finite element models

Thermal testing of a 3-die stacked chip scale package includ...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： B.A. Zahn ChipPAC Inc. Chandler AZ USA

Thermal performance testing was conducted on a 16/spl times/16 mm, 2-metal layer, 591-ball, 0.50 mm pitch, 1.20 mm overall height chip scale package (CSP) containing an offset pyramid configuration of three stacked Delco thermal test die. Die sizes from bottom-to-top were 10.16/spl times/10.16 mm (Delco PST-6), 6.35/spl times/6.35 mm (Delco PST-4), and 3.81/spl times/0.81 mm (Delco PST-2). Testing was carried out using eight different multi-die power configurations in a natural convection environment to highlight the effects of radiant and convective heat transfer. Measured data was obtained on a sample size of five packages to calculate Theta JA, Psi JT, and Psi JB values at each of the eight different multi-die power configurations. Furthermore, Theta JC and Theta JB cold plate measurements were also obtained. For the purposes of thermal testing, each of the five CSP test samples was mounted on a JEDEC standard 101.5/spl times/114.1/spl times/1.60 mm 1S2P thermal test board. Measured results are used to suggest a methodology for the generation of linear superposition matrix equations as a means to present multi-die package thermal test data such that it may account for changes in. thermal cross talk between die at varying die power configurations. The ANSYS finite element analysis modeling software was used to simulate the eight aforementioned thermal test configurations for the purpose of verifying the acquired test data. Both simplified and complex package substrate metal layer trace patterns were evaluated for simulation accuracy. The simplified patterns consisted of conductor traces that do not follow the detailed routing of the actual design, but instead extend straight outward towards the substrate edge. Alternatively, the complex patterns consisted of the detailed trace layers exactly as they are physically routed on the CSP substrate. In both the complex and simplified metal layer trace pattern finite element models, vias that connect the top and bottom tr

关键词： Chip scale packaging Geometry Finite element methods Solid modeling Thermal conductivity Software testing Heat transfer Power measurement Pressure measurement Size measurement

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Response surface modeling for nonlinear packaging stresses

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JOURNAL OF ELECTRONIC PACKAGING 2003年第4期125卷 490-497页

作者： van Driel, WD Zhang, GQ Janssen, JHJ Ernst, LJ Philips Semicond ATO Innovat NL-6534 AE Nijmegen Netherlands Philips CFT NL-5600 MD Eindhoven Netherlands Delft Univ Technol NL-2600 GA Delft Netherlands

The present study focuses on the development of reliable response surface models (RSM's) for the major packaging processes of a typical electronic package. The major objective is to optimize the product/process designs against the possible failure mode of vertical die cracks. First, the finite element mode (FEM)-based physics of failure models are developed and the reliability of the predicted stress levels was verified by experiments. In the development of reliable thermo-mechanical simulation models, both the process (time and temperature) dependent material nonlinearity and geometric nonlinearity are taken into account. Afterwards, RSM's covering the whole specified geometric design spaces are constructed. Finally, these RSM's are used to predict, evaluate, optimize, and eventually qualify the. thermo-mechanical behavior of this electronic package against the actual design requirements prior to major physical prototyping and manufacturing investments.

关键词： Solders integrated circuit packaging Optimization response surface methodology cracks Packaging finite element analysis design Stress modeling Testing Response surface methodology Finite element model Temperature failure analysis integrated circuit reliability

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SoC design case study using SystemC specifications. 15

SoC design case study using SystemC specifications.

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15th International conference on microelectronics (ICM 2003)

作者： Abbes, F Casseau, E Abid, M ENIS GMS Sfax 3038 Tunisia

ISBN: (纸本)9770520101

Modern systems become more and more complex and tendency turn to the integration on one single chip: System on Chip (SoC). A major constraint consists of "Time-to-Market". Hence, the emergence of SoC is creating many new challenges, especially, the necessity of a unified language for the system level design. SystemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware / software systems. This paper describes a method of stepwise refinement with SystemC, starting from an algorithmic description and progressively adding implementation details. The,method Is described with reference to a Turbo encoder, which is progressively moved from a purely abstract level to a more detailed description. This study is realized to emphasize on the importance of this tendency within the framework of SoC design. We also present the experimental results from specification, refinement and validation with SystemC and simulation effectiveness of the proposed method.

关键词： SoC system level modeling SystemC refinement methodology turbo code

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Application of CAD tools for design and simulation of capacitive microaccelerometers 7

Application of CAD tools for design and simulation of capaci...

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7th International conference of the Experience of designing and Application of CAD Systems in microelectronics

作者： Szaniawski, K Podsiadly, P Napieralski, A Tech Univ Lodz Dept Microelect & Comp Sci PL-93590 Lodz Poland

ISBN: (纸本)9665532782

The paper demonstrates, how CAD design and simulation tools can assist in developing MEMS devices in general, and capacitive accelerometers in particular. Two types of surface-micromachined accelerometers are presented and described. Advantages and disadvantages of particular tools are discussed. The paper also includes sample simulation results, which prove that virtual simulations can provide the designer a lot of information with no need for device fabrication and measurements.

关键词： CAD MEMS accelerometers modeling

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modeling and simulation sigma-delta analog to digital converters using VHDL-AMS 7

Modeling and simulation sigma-delta analog to digital conver...

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7th International conference of the Experience of designing and Application of CAD Systems in microelectronics

作者： Szermer, M Daniel, M Napieralski, A Tech Univ Lodz Dept Microelect & Comp Sci PL-93590 Lodz Poland

ISBN: (纸本)9665532782

The purpose of this paper is. to introduce the approach of modeling and simulation of the sigma-delta modulators using VHDL-AMS. In this paper is stressed that fast and efficient modeling and simulation methodology can be very helpful in the process of microsystem design. A few sigma-delta modulators structures are presented. From 1(st) to 4(th) order sigma-delta modulator and also a triple cascade structures are shown. The advantages and disadvantages of presented structures are discussed. The optimal solution is submitted to use as a part of silicon microsystem. The proposed silicon microsystems are based on two major parts. First part consists of chemical sensors whereas the second part consists of analog to digital converters, registers, buffers, etc. The analog to digital conversion is performed using sigma-delta method. Modulators are modeled and tested with application of VHDL-AMS simulator. In this paper the simulation results are presented, and discussion of the advantages of sigma-delta conversion in this kind of measurement is performed.

关键词： sigma-delta modulator silicon microsystem VHDL-AMS

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A mixed abstraction level co-simulation case study using SystemC for system on chip verification

A mixed abstraction level co-simulation case study using Sys...

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design, Automation and Test in Europe conference and Exhibition (DATE 03)

作者： Sayinta, A Canverdi, G Pauwels, M Alshawa, A Dehaene, W STMicroelectronics Istanbul Turkey

ISBN: (纸本)0769518702

This paper focuses on co-simulation scenarios and their applications as apart of a system-on-chip (SoC) modeling and design methodology developed at Alcatel microelectronics (now part of STmicroelectronics) within a wireless local area network (LAN) SoC project. This methodology proposes to build a SystemC-based executable model of the system to maintain a bridge between the algorithmic and the implementation worlds. The model is used in later phases by means of cosimulation of SystemC, HDL and firmware. SystemC-HDL co-simulation scenario provides a way of checking inter-operability of a single designed HW module with the SystemC model. The SystemC-Instruction Set Simulator (ISS) co-simulation provides a platform to develop and verify the firmware that will run on the selected processor core even before the HW modules are designed. It will be shown that, with sufficient tool support, these design stages reduce the complexity of the SoC design and improve the debugging capabilities.

关键词： Firmware

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The Experience of designing and Application of CAD Systems in microelectronics - Proceedings of the 7th International conference, CADSM 2003

The Experience of Designing and Application of CAD Systems i...

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7th International conference on CAD Systems in microelectronics, CADSM 2003

ISBN: (纸本)9665532782

The proceedings contain 191 papers. The topics discussed include: the problems and challenges of RF analog and wireless systems design using modern CAD tools;teaching system-on-chip design at technical university of Lodz;technique of modeling and defectiveness estimation in structures of integrated circuit;the principles of pattern and marker checking in the production processes;the microchip Q-switched Yb:YAG laser performance analysis;algorithms and VLC-structures for calculus of maximum and minimum values;teleworking in computer-aided circuit design;simulation of dynamic oscillator energy exchange with resistance environment and force source of sinusoidal action and its correlation with spectrum vibrations;amplitude-phase-shift masks for projection lithography of submicron technology;problems of construction of systems of automation of designing of hydrostatic systems by a method of function;and computerized system for assessment of quality of solders.

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Multi-layer behavioral modeling of charge-pump phase-locked loops 5

Multi-layer behavioral modeling of charge-pump phase-locked ...

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5th International conference on ASIC, ASICON 2003

作者： Wennan, Feng Zhongjian, Cheng Ling, Liu Lijiu, Ji Institute of Microelectronics Peking University Post Code 100871 China

ISBN: (纸本)078037889X

A mulli-layer modeling approach is proposed in this paper for creating behavioral models of Charge-Pump Phase-Locked Loops, which offers great flexibility of trading off between the simulation speed and accuracy. Also the approach allows time domain noise simulation with a specific layer. A multilayer Verilog-A Charge-Pump PLL model is created to illustrate the proposed approach. A simulation speed up factor of 12 to 99 is achievcd with reasonable loss of accuracy. © 2003 IEEE

关键词： Locks (fasteners)

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