In this paper, we present a component-based multi-level mixed-signal design and simulation methodology that provides a solution to the problem of accurate modeling and simulation of mixed signal, multi-domain (MSMD) s...
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ISBN:
(纸本)0972842209
In this paper, we present a component-based multi-level mixed-signal design and simulation methodology that provides a solution to the problem of accurate modeling and simulation of mixed signal, multi-domain (MSMD) systems. This is achieved by first, partitioning the system into components that are modeled by analytic expressions at the behavioral level;and second, integrating these expressions into component behavioral solvers using a combination of piecewise linear (PWL) modeling and Modified Nodal Analysis (MNA). At the system level, a discrete event simulator sends composite signals between these components and manages multiple timescales and feedback. simulation speed and accuracy can be tuned by controlling the granularity of the regions of operation of the devices, the sample density of optical wavefronts, and the time resolution of the discrete event simulator. The methodology is specifically optimized for loosely coupled systems of complex components such as the ones found in multi-domain microsystems.
System architects working on SoC design have traditionally been hampered by the lack of a coherente methodology for architecture evaluation and co-verification of hardware and software. SystemC 2.0 facilitates the dev...
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ISBN:
(纸本)0769519237
System architects working on SoC design have traditionally been hampered by the lack of a coherente methodology for architecture evaluation and co-verification of hardware and software. SystemC 2.0 facilitates the development of Transaction-Level Models (TLMs) which are models of the hardware system components at higher level of abstraction than RTL. Due to lower modeling effort yet higher simulation speed, TLMs are useful for architectural exploration, algorithmic evaluation, hardware-software partitioning and software development. The problems posed by SOC design methodologies require development of models at higher abstraction also for the earlier developed IP's. The development time of a TLM IP is already low, so if we can reduce the verification time by re-use of the earlier RTL test benches we can reduce the overall cost of such an IP TLM. This paper focusses on the methodology to use the RTL testbenches for verification of a SvstemC model of the same IP at a higher abstraction level (Transaction level), some tools available in the market to support this testbench reuse and the implementation challenges posed by the mentioned verification technique.
This paper demonstrates, how CAD design and simulation tools can assist in developing MEMS devices in general, and capacitive accelerometers in particular. Two types of surface-micromachined accelerometers are present...
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This paper demonstrates, how CAD design and simulation tools can assist in developing MEMS devices in general, and capacitive accelerometers in particular. Two types of surface-micromachined accelerometers are presented and described. The advantages and disadvantages of particular tools are discussed. The paper also includes sample simulation results, which prove that virtual simulations can provide the designer a lot of information with no need for device fabrication and measurements.
The rapid development of microelectronics results in more complex semiconductor device structures and makes it necessary to use modern computer software. However, high prices and hardware requirements considerably lim...
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ISBN:
(纸本)0972842217
The rapid development of microelectronics results in more complex semiconductor device structures and makes it necessary to use modern computer software. However, high prices and hardware requirements considerably limit the access to these CAD tools by educational institutions, students or small enterprises, and free versions of commercial software usually lack for well-implemented numerical algorithms and device models. In order to overcome these limitations and to make accurate and modern semiconductor device models widely accessible, a website has been designed and made available to Internet users (http://***/dmcs-spice), allowing to perform simulations of electronic circuits. A new distributed model of power diode is included in this package to show that the presented approach can facilitate the design process of power circuits, as accurate power device models can be made available for designers worldwide.
The Department of microelectronics and Computer Science of The Technical University of Lodz, owing to the participation in numerous projects financed by the European Union, has developed over the past decade modern CA...
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The Department of microelectronics and Computer Science of The Technical University of Lodz, owing to the participation in numerous projects financed by the European Union, has developed over the past decade modern CAD design, simulation and testing laboratories. The main goal of this paper is to present the facilities which are at the disposal of both students and scientist at the university. In particular, the paper demonstrates how all the available teaching aids, i.e. hardware and software, are employed in the current curricula for teaching students system-on-chip design. Some of designed ASIC circuits are presented.
In this paper, the preparation to run simulations of electrokinetic phenomena in VHDL-AMS is presented. The authors present fundamentals of these phenomena and also focus on the necessity of such simulation.
In this paper, the preparation to run simulations of electrokinetic phenomena in VHDL-AMS is presented. The authors present fundamentals of these phenomena and also focus on the necessity of such simulation.
The purpose of this paper is to introduce the approach of modeling and simulation of sigma-delta modulators using VHDL-AMS. In this paper is stressed that fast and efficient modeling and simulation methodology can be ...
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The purpose of this paper is to introduce the approach of modeling and simulation of sigma-delta modulators using VHDL-AMS. In this paper is stressed that fast and efficient modeling and simulation methodology can be very helpful in the process of microsystem design. A few sigma-delta modulator structures are presented. From 1/sup st/ to 4/sup th/ order sigma-delta modulators and also a triple cascade structure are shown. The advantages and disadvantages of the presented structures are discussed. The optimal solution is submitted to use as part of a silicon microsystem. The proposed silicon microsystems are based on two major parts. The first part consists of chemical sensors whereas the second part consists of analog to digital converters, registers, buffers, etc. The analog to digital conversion is performed using the sigma-delta method. Modulators are modeled and tested with the application of a VHDL-AMS simulator. In this paper, the simulation results are presented, and discussion of the advantages of sigma-delta conversion in this kind of measurement is performed.
Fast algorithms for structural analysis of large digital devices containing millions of equivalent gates are offered. These algorithms are used in the preprocessing stage for increase of fault simulation and test gene...
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Fast algorithms for structural analysis of large digital devices containing millions of equivalent gates are offered. These algorithms are used in the preprocessing stage for increase of fault simulation and test generation speed. The data structures and program procedures for algorithm realization are described. The ATPG system is offered.
A fast deductive-parallel backtraced fault simulation method uses the superposition procedure, which is oriented on large digital designs. It is proposed processing of RT and gate level design representation. The data...
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A fast deductive-parallel backtraced fault simulation method uses the superposition procedure, which is oriented on large digital designs. It is proposed processing of RT and gate level design representation. The data structure and program are oriented on algorithms for realization of proposed method and integration in automatic test pattern generation systems.
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