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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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A hierarchical block-based modeling methodology for SoC in GENESYS

A hierarchical block-based modeling methodology for SoC in G...

引用

Annual IEEE International ASIC/SOC conference

作者： S. Nugent D.S. Wills J.D. Meindl Microelectronics Research Center School of ECE Georgia Institute of Technology Atlanta GA USA

System-on-a-chip (SoC) designs promise to play a dominant role in the future of gigascale integrated (GSI) systems. Existing chip modeling tools based on technology parameters for projecting physical performance are ill suited for projecting the performance of SoC designs. A new modeling methodology for heterogeneous SoCs has been developed for a technology based simulation tool (GENESYS). The hierarchical block modeling methodology mimics the structure of a SoC design by partitioning the chip into blocks as is typical of megacell based design methodologies. The new model allows for exploration of the impact of technology choices on SoC performance for a wide variety of designs. An example SoC is simulated showing improved accuracy of the heterogeneous compared to the homogeneous model. A percentage error of 18.6% for the die size calculation in the homogeneous model is reduced to 3% with the heterogeneous modeling. In addition, the scaling characteristics of the example SoC are shown for the ITRS technology generations. Results show that the same design implemented in 35 nm technology could achieve a factor of 6 increase in clock frequency while operating at less than 1 W on a 5 mm/sup 2/ die.

关键词： System-on-a-chip Power system modeling design methodology Integrated circuit technology Clocks System performance Logic Frequency estimation microelectronics Character generation

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Comparative study of electrostatically actuated torsion micromirrors: design parameters and performance

Comparative study of electrostatically actuated torsion micr...

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IEEE/LEOS International conference on Optical MEMS

作者： O. Bochobza-Degani S. Feldman Y. Nemirovsky Electrical Engineering Department Kidron Microelectronics Research Center Haifa Israel

This paper will systematically compare the measured results of electrostatic torsion micromirrors with various design parameters, namely: the actuator shape, location of bottom electrode and aspect ratio of the suspending beam. The results of this study are instrumental for the design of torsion micromirrors with new efficient simulation methodology, achieving extended travel range and minimizing the applied voltage required for their operation.

关键词： Micromirrors Actuators Voltage Electrodes Shape measurement Electrostatic measurements Displacement measurement Optical devices Instruments Semiconductor device modeling

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Thermal model of power semiconductor devices for electro-thermal circuit simulations

Thermal model of power semiconductor devices for electro-the...

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International conference on microelectronics, MIEL

作者： P.M. Igic P.A. Mawby M.S. Towers S. Batcup Power Electronics Design Centre University of Wales UK

An electro-thermal (ET) strategy used for ET circuit simulations is described in this paper. An original program for a MATLAB environment based on a deconvolution method is written and used for a determination of the RC dynamic thermal network parameters. An excellent agreement is obtained between experimental thermal transient response function of the device for a step function excitation and simulated one obtained using corresponding RC thermal network.

关键词： Power semiconductor devices Circuit simulation Electronic packaging thermal management Deconvolution Equations Mathematical model Transient response Computational modeling Temperature MOSFET circuits

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A real delay switching activity simulator based on Petri net modeling

A real delay switching activity simulator based on Petri net...

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Asia and South Pacific design Automation conference

作者： A.K. Murugavel N. Ranganathan Center for Microelectronics Research Department of Computer Science and Engineering University of South Florida Tampa USA

ISBN: (纸本)0769514413

Switching activity estimation is an important step in power estimation of digital VLSI circuits. While simulation yields accurate results, it is time consuming. In this paper, we propose a new technique based on Petri nets for real-delay switching activity estimation that yields the same accuracy as simulation, but is significantly faster in computation. We introduce a new type of Petri net called Hierarchical Colored Hardware Petri Net (HCHP-Net). The gate-level circuit is first transformed into a directed acyclic graph called, GSDAG, in which both the gates as well as the signals correspond to the nodes in the graph. The GSDAG is then mapped onto a corresponding HCHP-Net which is then simulated using a Petri net simulator Experimental results for ISCAS '85 circuits are presented. The method replicates exactly the switching activity results for real-delay models produced by HSPICE and PowerMill. However, the per pattern simulation time is about 51 times faster than the Synopsys PowerMill and 8900 times faster than the Avanti HSPICE.

关键词： Circuit simulation Computational modeling Switching circuits Very large scale integration Delay estimation Petri nets Yield estimation Energy consumption Portable computers High performance computing

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NASDAC - A new simulation tool for the electro-thermal analysis of bipolar devices: application to multi-finger AlGaAs/GaAs HBT's

NASDAC - A new simulation tool for the electro-thermal analy...

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International conference on microelectronics, MIEL

作者： M. Macchiaroli V. d'Alessandro N. Rinaldi Department of Electronics and Telecommunications Engineering University of Naples “Federico II” Naples Italy

In this paper a new simulation tool is presented, suitable to describe the electro-thermal behavior in multi-finger AlGaAs/GaAs devices. The program is based on a new analytical formulation to compute the device temperature distribution both for the steady-state and the transient case and incorporates an accurate electro-thermal physically-based model for the elementary transistor. The effect of the geometry of heat dissipating regions is accounted for. Thermal conductivity dependence on temperature and de-biasing effects across metallization layers are also included. Hence the simulator can be efficaciously used to enhance the thermal chip design, by means of illustrative comparisons between different structures.

关键词： Analytical models Gallium arsenide Computational modeling Thermal conductivity Distributed computing Physics computing Temperature distribution Steady-state Transient analysis Geometry

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Switching activity estimation of large circuits using multiple Bayesian networks

Switching activity estimation of large circuits using multip...

引用

Asia and South Pacific design Automation conference

作者： S. Bhanja N. Ranganathan Center for Microelectronics Research Department of Computer Science and Engineering University of South Florida Tampa FL USA

ISBN: (纸本)0769514413

Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In this work, we propose a new strategy for efficient segmentation of large circuits so that they can be mapped to Multiple Bayesian Networks (MBN). The goal here is to achieve higher accuracy while reducing the memory requirements during the computation. In order to capture the correlations among the boundaries of segments, a tree dependent (TD) distribution is proposed between the segment boundaries such that the TD distribution is closest to the actual distribution of switching variable with some distance criterion. We use a Maximum Weight Spanning Tree (MWST) based approximation using mutual information between two variables at the boundary as the weight of the edge between the variables. Experimental results for ISCAS'85 circuits show that the proposed method improves accuracy significantly over other methods.

关键词： Switching circuits Bayesian methods microelectronics Computer science Power engineering and energy Energy consumption Semiconductor device modeling Circuit simulation Statistics Probability

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Modelling, simulation and design sigma-delta converters in silicon microsystems

Modelling, simulation and design sigma-delta converters in s...

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International conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science

作者： M. Szermer M. Daniel K. Slusarczyk A. Napieralski Department of Microelectronics & Computer Science Technical University of Lodz Lodz Poland

The purpose of this paper is the new approach of modeling and designs the sigma-delta converters in silicon microsystems. Microsystem described in this paper bases on two major parts. First part consists of various sensors and the second part consists of analogue to digital converters as well as other standard electronics circuits. The analogue to digital conversion is performed using sigma-delta modulators. Modulators were designed in CAD CADENCE environment and simulated using SPECTRES, and ELDO simulators. In this paper the simulation results were presented, and discussion of the advantages of sigma-delta conversion in this kind of measurement was underlined.

关键词： Delta-sigma modulation Silicon Data processing Analog-digital conversion design automation Circuit simulation Bridge circuits Digital modulation Etching Computational modeling

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VHDL-AMS: a competitor for SPICE in modeling of semiconductor devices

VHDL-AMS: a competitor for SPICE in modeling of semiconducto...

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International conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science

作者： L. Starzak A. Napieralski J.-J. Charlot The Department of Microelectronics and Computer Science Technical University of Łódź Lodz Poland Ecole Nationale Supérieure des TéIécommunications Paris France

In this paper potential merits of the new IEEE VHDL-AMS standard in the field of modeling of semiconductor devices are discussed. Special emphasis is given to the modeling of electro-thermal coupling. A simple example... 详细信息

关键词： SPICE Semiconductor devices Circuit simulation Breakdown voltage Hardware design languages Semiconductor diodes Coupling circuits Integrated circuit modeling Equations Radiative recombination

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Accumulation MOS varactors for 4 to 40 GHz VCOs in SOI CMOS

Accumulation MOS varactors for 4 to 40 GHz VCOs in SOI CMOS

引用

IEEE International SOC conference

作者： Fong Tarr Zamdmer Plouchart Plett Department of Electronics Carleton University Ottawa Ontario Canada IBM Microelectronics Semiconductor Research and Development Center NY IBM Microelectronics Semiconductor Research and Development Center Hopewell Junction NY USA

It has recently been shown that MOS capacitors fabricated in deep submicron CMOS technologies can serve as high-Q varactors for RF circuit design. The devices are often operated with the silicon surface in accumulation to maximize Q, and so have been termed accumulation mode or AMOS varactors. This paper combines MEDICI simulation and experimental results to demonstrate that AMOS varactors fabricated in SOI technology can provide significant advantages over bulk technology devices at the same channel length. A low voltage AMOS varactor with wide tuning range and high Q fabricated in a 0.13 /spl mu/m CMOS technology is reported. The varactors have been employed in VCO circuits operating at frequencies in excess of 40 GHz.

关键词： Varactors MOS capacitors Silicon on insulator technology CMOS integrated circuits Voltage controlled oscillators Semiconductor device modeling

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A Real Delay Switching Activity Simulator based on Petri net modeling 02

A Real Delay Switching Activity Simulator based on Petri net...

引用

Proceedings of the 2002 Asia and South Pacific design Automation conference

作者： Ashok K. Murugavel N. Ranganathan Center for Microelectronics Research Department of Computer Science and Engineering University of South Florida Tampa

ISBN: (纸本)9780769514413

Switching activity estimation is an important step in power estimation of digital VLSI circuits. While simulation yields accurate results, it is time consuming. In this paper, we propose a new technique based on Petri nets for real-delay switching activity estimation that yields the same accuracy as simulation, but is significantly faster in computation. We introduce a new type of Petri net called Hierarchical Colored Hardware Petri Net (HCHP-Net). The gate-level circuit is first transformed into a directed acyclic graph called, GSDAG, in which both the gates as well as the signals correspond to the nodes in the graph. The GSDAG is then mapped onto a corresponding HCHP-Net which is then simulated using a Petri net simulator. Experimental results for ISCAS '85 circuits are presented. The method replicates exactly the switching activity results for real-delay models produced by HSPICE and PowerMill. However, the per-pattern simulation time is about 51 times faster than the Synopsys PowerMill and 8900 times faster than the Avanti HSPICE.

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