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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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design and Optimization of Bump Structures of Large Die Fine Pitch Copper/Low-k FCBGA and Copper Post Interconnections

Design and Optimization of Bump Structures of Large Die Fine...

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Electronics Packaging Technology conference (EPTC)

作者： Kalyan Biswas Shiguo Liu Xiaowu Zhang TC Chai IBIDEN Singapore Private Limited Singapore Singapore Institute of Microelectronics Singapore

This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design, metal cracks at RDL were found for the conventional SnAg bump and Cu post samples. In order to improve the bump structure design a thermo-mechanical modeling was performed to identify the effects of different design parameters and to identify the best solution to achieve reliable assembly performance. simulation has identified few contributing factors: RDL pad thickness, dielectric thickness, UBM via size, UBM size and chip thickness. Then a series of parametric study was performed to identify the set of design points at which the finite element analysis provides the lowest stress level in RDL pad and low-k layer of the chip. Based on the results a guideline for bump configuration is proposed. To confirm the assembly performance of the optimized bump structure, the improved design has been incorporated into final test vehicle, which has a better assembly performance with no RDL pad metal crack found.

关键词： Copper design optimization Assembly Thermomechanical processes Dielectrics Parametric study Finite element methods Performance analysis Stress Guidelines

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design, modeling and simulation of an Anchorless Nano-Electro- Mechanical Nonvolatile Memory

Design, Modeling and Simulation of an Anchorless Nano-Electr...

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2012 International conference on Solid-State and Integrated Circuit(ICSIC 2012)

作者： Ramesh Vaddi Vincent Pott Julius Tsai Ming Lin Tony T. Kim VIRTUS School of Electrical and Electronic Engineering Nanyang Technological University50 Nanyang Avenue Singapore 639798 Institute of Microelectronics A*STAR (Agency for Science Technology and Research) 11 Science Park Road Singapore Science Park ⅡSingapore 117685

Non Volatile Memories (NVMs) based on a storage layer, like FLASH, suffer from poor retention at high temperature, high voltage writing, and wear out while cycling. This paper presents the structure, operation and modeling details of a new NVM based on nano-electromechanical memory (NEM) cell having two stable mechanical positions and actuated by electrostatic forces. Permanent retention is obtained by adhesion forces only, eliminating the leakage observed in all types of storage layers. First part of the work focus on the introduction of single cell of NEM based NVM structure and operation. The second part of the work focus on NEM based NVM modeling and behavior implementation with Verilog-A compact modeling and testing in Cadence environment. The results verify the correct functionality and scalability of the new NEM cell. With the anchorless shuttle, the design is highly eased and scalable, compared to standard anchor based NEM structures.

关键词： Non Volatile memories (NVMs), Nano-electromechanical (NEMs), Verilog-A modeling.

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Molecular simulation of cu-sam adhesion force

Molecular simulation of cu-sam adhesion force

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Haibo Fan C.K.Y. Wong M.M.F. Yuen Department of Mechanical Engineering Hong Kong University of Science and Technology Kowloon Hong Kong China

The interface of Copper-EMC (Epoxy Molding Compound) is known to be the weakest joint in the electronic package design, which causes delamination during reliability test. A prime reason is the poor adhesion between Cu and epoxy compound. To solve the problem, We have used self-assembly monolayer (SAM) to improve adhesion of copper-epoxy system. This paper focuses on simulation of adhesion in Cu-SAM system. In this study, molecular models of bi-material system, which consists of SAM and Cu, were built to evaluate adhesion force of the Cu-SAM system. In order to dramatically reduce the computational time, only the copper tip and SAM substrate were modeled with a limited number of atoms. After energy minimization of the whole structure, tensile stresses were applied to the whole structure to simulate the debonding process, and the ultimate stress was obtained when the two materials delaminates completely. The adhesion force between the copper tip and the SAM can be evaluated from the ultimate tensile stress. The molecular model results were compared with AFM results in which adhesion force between Cu tip and SAM coated copper substrate were measured. Two different types of SAM material were used in this study. The paper intended to relate closely adhesion by using MD simulation, and the underlying physics for the explanation to the adhesion phenomenon for further understanding of failure mechanism of interfacial delamination.

关键词： Adhesives Atomic force microscopy Copper Rough surfaces Surface roughness Tensile stress Delamination Electronics packaging Self-assembly Computational modeling

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Quick generation of temporal power waveforms for RT-level hard macros

Quick generation of temporal power waveforms for RT-level ha...

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IEEE International conference on Innovative Systems in Silicon

作者： L. Benini G. De Micheli E. Macii M. Poncino R. Scarsi Computer Systems Laboratory University of Stanford Stanford CA USA Dip. di Automatica e Informatica Politecnico di Torino Torino Italy

Power characterization of complex macros is essential to enable accurate RT-level power estimation. Existing characterization procedures focus on the average value of power. In this paper, we take a fresh look at this problem. We propose a fast, yet accurate technique to determine a time-dependent power model, i.e., a temporal power waveform, which is able to fully characterize the power behavior of a hard macro in response to a realistic input stream consisting of typical usage patterns. Our approach is simulation-based, and resorts to a mix of high-level, fast cycle-based simulation with low-level, slow accurate simulation of the long set of input patterns. Results are extremely satisfactory, since the average error between the power waveforms generated by our tool and the exact ones is always within 1%, while the reduction in the execution time ranges between one and two orders of magnitude.

关键词： Power generation Libraries Computational modeling Character generation Energy consumption Hardware design languages Laboratories Circuit simulation microelectronics Silicon

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Molecular dynamic simulations of maximum pull-out forces of embedded CNTs for sensor applications and validating nano scale experiments

Molecular dynamic simulations of maximum pull-out forces of ...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Steffen Hartmann Ole Hölck Thomas Blaudeck Sascha Hermann Stefan E. Schulz Thomas Gessner Bernhard Wunderle Technische Universität Chemnitz Chemnitz Germany

We present investigations of pull-out tests on CNTs embedded in palladium by means of molecular dynamics (MD) and compare our results of maximum pull-out forces with values of nano scale in situ pull-out tests inside a scanning electron microscope (SEM). Our MD model allows the investigation of crucial influencing parameters on the interface behaviour, like CNT diameter, intrinsic CNT defects and functional groups. For the experiments we prepared simple specimens using silicon substrates and wafer level compliant technologies. We realised the nano scale experiment with a nanomanipulation system supporting an AFM cantilever with known stiffness as a force sensing element inside a SEM. Greyscale correlation has been used to evaluate the cantilever deflection. From simulations derived maximum pull-out forces are approximately 17 nN and depend on the existence of intrinsic defects or functional groups and weakly on temperature. Experimentally obtained maximum pull-out forces with values between 16-29 nN are in good agreement with the computational predictions. Our results are of significant interest for the design and a failure-mechanistic treatment of future mechanical sensors with integrated single-walled CNTs showing high piezoresistive gauge factor or other nano scale systems incorporating CNT-metal interfaces.

关键词： Abstracts Loading Load modeling

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External field enhancement in coupled polymer microcavities - New options for integrated photonic components

External field enhancement in coupled polymer microcavities ...

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conference on Lasers and Electro-Optics Europe (CLEO EUROPE)

作者： Nicolas Innocenti Sergei Popov Sergey Sergeyev Ari T. Friberg Department of Microelectronics and Applied Physics Royal Institute of Technology Kista Sweden Optics Research Group Waterford Institute of Technology Waterford Ireland Department of Applied Physics Helsinki University of Technology Finland Department of Physics and Mathematics University of Joensuu Joensuu Finland

ISBN: (纸本)9781424440801

Microcavities are key components for integrated optical devices and systems. In this paper, enhancement of the resonance electric field outside a pair of coupled polymeric microcavities of hexagonal shape is investigated. Using numerical simulation, enhancement of outside-cavity field has been demonstrated in different sections of the coupled cavity system depending on particular design. Resonance frequencies are in visible part of electromagnetic spectrum. In reported simulations rigorous models based on solving Maxwell equations for propagating electromagnetic field in polymeric materials commonly used in nano-imprinting lithography is demonstrated.

关键词： Polymers Microcavities Resonance Optical devices Shape Numerical simulation Resonant frequency Electromagnetic spectrum Electromagnetic modeling Maxwell equations

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An Efficient 90nm Technology-Node GHz Transceiver of On-Chip Global Interconnect

An Efficient 90nm Technology-Node GHz Transceiver of On-Chip...

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2011 IEEE 9th International conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

作者： Zaixiao Zheng Zhigang Mao Jianfei Jiang Department of Microelectronics Shanghai JiaoTong University Shanghai 200240. China

Today high speed signal transmission system for on chip global interconnect requires elaborate design of the transceiver. The design goal of transceiver is to ensure the transmission obtains 'an improvement in latency and power, which are the two most important factors in high speed transmission. In this paper, we present an efficient structured transceiver which implements low swing technology based on the differential structure with the accurate modeling of the on chip global interconnect. And we give the principals of the structure and compare the optimized simulation results with the traditional inverter insertion method used to decrease the delay of the global interconnect. Our transceiver design is based on the 90nm CMOS technology and TSMC 90nm interconnect structure on Metal 5. The global interconnect length we focus on is the general length 10mm. Compared to repeater insertion, this system has a latency advantage of 17％ and remarkable advantage in power up to 33.9％.

关键词： 90nm technology Differential transmission Low swing 3-D multi-level modeling

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Verification of transaction-level SystemC models using RTL testbenches 03

Verification of transaction-level SystemC models using RTL t...

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ACM and IEEE International conference on Formal Methods and Models for Co-design (MEMOCODE)

作者： R. Jindal K. Jain CRnD STMicroelectronics India

ISBN: (纸本)9780769519234

System architects working on SoC design have traditionally been hampered by the lack of a coherent methodology for architecture evaluation and co-verification of hardware and software. SystemC 2.0 facilitates the development of transaction-level models (TLMs), which are models of the hardware system components at higher level of abstraction than RTL. Due to lower modeling effort yet higher simulation speed, TLMs are useful for architectural exploration, algorithmic evaluation, hardware-software partitioning and software development. The problems posed by SOC design methodologies require development of models at higher abstraction also for the earlier developed IP's. The development time of a TLM IP is already low, so if we can reduce the verification time by re-use of the earlier RTL test benches we can reduce the overall cost of such an IP TLM. This paper focuses on the methodology to use the RTL testbenches for verification of a SystemC model of the same IP at a higher abstraction level (transaction level), some tools available in the market to support this testbench reuse and the implementation challenges posed by the mentioned verification technique.

关键词： System testing Costs Hardware microelectronics design methodology design engineering Yarn Partitioning algorithms Software algorithms Programming

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modeling of SiC power modules with double sided cooling

Modeling of SiC power modules with double sided cooling

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Klas Brinkfeldt Klaus Neumaier Alexander Mann Olaf Zschieschang Alexander Otto Eberhard Kaulfersch Michael Edwards Dag Andersson Swerea IVF Mölndal Sweden Fairchild Semiconductor GmbH Aschheim Germany Fraunhofer ENAS Chemnitz Germany Berliner Nanotest und Design GmbH Berlin Germany

Silicon Carbide (SiC) based transistor devices have demonstrated higher efficiency switching operation compared to silicon-based, state-of-the-art solutions due to the superior electrical and thermal properties of the SiC material. The improved current density and thermal conductivity allows SiC-based power modules to be smaller than their silicon counterparts for comparable current densities. The active chip area can be reduced further by effectively cooling the devices. In this work, a new power module including SiC bipolar junction transistors (BJT) and diodes and integrated double sided cooling will be introduced. The target application of these modules is a new drive-train system for commercial electric vehicles. The double sided cooling concept (named 2Cool) is a feasibility study with the goal to further compact the inverter system. More efficient removal of heat from the junction leads to a higher power rating per die, which in turn leads to fewer die and reduced system volume. Since temperature is a main driver in expected failure modes an increase in cooling capability will also enhance margins of the SiC device reliability. In addition, the removal of wirebonds on the top side of the die will result in lower electrical inductance. Several geometries of the heat exchanger cooling structures have been modeled in terms of thermal performance. The best geometry was a staggered pin-fin structure, which resulted in a junction temperature increase of 74 K at 400 W thermal loading. Also, thermomechanical modeling was used to make an estimation of stress in the power module materials.

关键词： Heating Abstracts Three-dimensional displays Switches Cooling Pumps Power dissipation

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Multi-scale energy-based failure modeling of bond pad structures

Multi-scale energy-based failure modeling of bond pad struct...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： O. van der Sluis R.B.R. van Silfhout R.A.B. Engelen W.D. van Driel G.Q. Zhang Department of Precision and Microsystem Engineering Delft University of Technology the Netherlands Philips Applied Technologies Eindhoven The Netherlands Department of Precision and Microsystem Engineering Delft University of Technnology Netherlands NXP Semiconductors Nijmegen The Netherlands NXP Semiconductors Nijmegen AE The Netherlands

Thermo-mechanical reliability issues have been identified as major bottlenecks in the development of future microelectronic components. This is caused by the following technology and business trends: (1) increasing miniaturisation, (2) introduction of new materials, (3) shorter time-to-market, (4) increasing design complexity and decreasing design margins, (5) shortened development and qualification times, (5) gap between technology and fundamental knowledge development. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [8]. However, bad mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back end structure when no appropriate development is performed. The scope of this paper is on the development of numerical models that are able to predict the failure sensitivity of complex three-dimensional multi-layered structures while taking into account the details at the local scale of the microelectronic components by means of a multi-scale method. The damage sensitivity is calculated by means of an enhanced version of the previously introduced area release energy (ARE) criterion. This enhancement results in an efficient and accurate prediction of the energy release rate (ERR) at a selected bimaterial interface in any location. Moreover, due to the two-scale approach local details of the structure are readily taken into account. In order to evaluate the efficiency and accuracy of the proposed method, several two-dimensional and three-dimensional benchmarks will be simulated. The paper focusses on the enhanced ARE method, including several two- and three-dimensional benchmarks.

关键词： Bonding Thermomechanical processes microelectronics CMOS technology Dielectric materials Time to market Qualifications Adhesives Integrated circuit packaging Wire

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