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International conference on simulation of Semiconductor Processes and Devices, SISPAD 2000年 204-205页

作者： Schoenmaker, Wim Magnus, Wim Interuniversity Microelectronics Cent Leuven Belgium

A new formulation for gate-leakage currents due to quantum tunneling is presented. The resulting model has been inserted into software modules. The relative importance of various gate stack design parameters is invest... 详细信息

关键词： CMOS integrated circuits

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Efficient ANN-based interconnect delay and crosstalk modeling

Efficient ANN-based interconnect delay and crosstalk modelin...

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International conference on microelectronics, MIEL

作者： A. Ilumoka Dept. of Electr. Eng. Hartford Univ. West Hartford CT USA

The dominance of system performance by interconnect delay in deep-submicron design presents many challenges to physical design tool developers. This paper presents an efficient ANN-based technique for modeling interconnect crosstalk in integrated circuits. ANN models for user-defined interconnect primitives called wirecells are trained and tested using a database created using a suitable simulation package. For fixed wirecell length and geometry, inputs to the ANN include signal frequency, input voltage amplitude, near and far end termination impedances. Outputs derived from the ANN include crosstalk voltage peak and RMS values and spectral composition. Experimental results demonstrate the ability of this approach to successfully predict coupled noise in modest cpu times compared with existing approaches.

关键词： Delay Crosstalk Integrated circuit interconnections Integrated circuit modeling Voltage System performance Circuit testing Spatial databases Circuit simulation Integrated circuit packaging

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A fast cycle-based approach for synthesizable RT level VHDL simulation

A fast cycle-based approach for synthesizable RT level VHDL ...

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International conference on microelectronics, ICM

作者： L. Ghasemzadeh Z. Navabi ECE Department University of Tehran Iran

ISBN: (纸本)9643600572

In this paper, a cycle-based RT level simulation engine is being discussed. Issues treated include component extraction, component ordering and feedback detection from behavioral VHDL descriptions. Proposing new methods in these topics, we try to give solutions for the problems that VHDL register transfer level simulators have to deal with. We also introduce a levelization method that due to its compatibility with the nature of RTL VHDL increases the simulation speed.

关键词： Clocks Discrete event simulation Circuit simulation Computational modeling Logic design Timing Feedback loop Hardware Flip-flops Engines

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A system-level simulation environment for system-on-chip design

A system-level simulation environment for system-on-chip des...

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Annual IEEE International ASIC/SOC conference

作者： T. Schneider J. Mades A. Windisch M. Glesner D. Monjau W. Ecker Corporate Development Infineon Technologies Munich Germany Institute of Microelectronic Systems Darmstadt University of Technology Darmstadt Germany Department of Computer Science Technical University of Chemnitz-Zwickau Chemnitz Germany

ISBN: (纸本)0780365984

This paper presents a mixed-signal/multi-language simulation environment for the languages VHDL-AMS, Java, and C++. The environment is implemented in Java and based upon a previously developed VHDL-AMS design environment consisting of a compiler, an elaborator and a simulator. The latter was extended by open object-oriented Java and C++ interfaces towards system-level simulation capabilities. Obviously, this approach lends itself to a VHDL-centric modeling style. However it also results in a well-defined overall simulation semantics based on the proven semantic principles of VHDL-AMS. Moreover the object-oriented Java and C++ interfaces enforce a much better language modeling style than traditional callback-based procedural language interfaces. The presented open architecture provides good capabilities for research in the field of system-level simulation.

关键词： System-on-a-chip Object oriented modeling Computational modeling Java System-level design Hardware design languages Power system modeling Chemical technology microelectronics Computer simulation

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Partially depleted silicon-on-insulator (SOI): a device design/modeling and circuit perspective

Partially depleted silicon-on-insulator (SOI): a device desi...

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International conference on microelectronics, ICM

作者： F. Assaderaghi G. Shahidi S. Fung M. Sherony L. Wagner J. Sleight S.H. Lo K. Wu T.-C. Chen Development Center IBM Semiconductor Research and Development Center Hopewell Junction NY USA

ISBN: (纸本)9643600572

This paper reviews the evolution of partially depleted (PD) CMOS SOI technology at IBM. Several aspects of this development leading to successful fabrication of high-performance microprocessors are discussed. They include SOI-specific device design and process modifications; creation of compact device models for circuit simulation (SPICE-like models); and development of circuit styles and strategies employed in the design of CMOS VLSI on PD SOI. Since these strategies address issues and problems that arise on PD SOI circuits such as delay hysteresis and noise margin reduction, they are discussed in detail. Although many aspects of CMOS design pertaining to SOI are covered, emphasis is placed on dynamic and static circuits and high-performance SRAMs.

关键词： Silicon on insulator technology CMOS technology Semiconductor device modeling Fabrication Microprocessors Process design Circuit simulation CMOS process Very large scale integration Delay

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An analytical 3-D model for small dimensions MOSFETs' threshold voltage

An analytical 3-D model for small dimensions MOSFETs' thresh...

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International conference on microelectronics, MIEL

作者： D.Z. Pilja R.M. Sasic R.M. Ramovic D.A. Tjapkin Faculty of Technology and Metallurgy University of Belgrade Belgrade Serbia Faculty of Electrical Engineering University of Belgrade Belgrade Serbia

This paper has presented an analytical three-dimensional (3D) model for threshold voltage of small dimensions MOSFETs with an experimental dependence of acceptor concentration in the channel. The corresponding algorit... 详细信息

关键词： Analytical models MOSFETs Poisson equations Performance analysis Integrated circuit modeling Boundary conditions Algorithm design and analysis Circuit simulation Voltage control Ion implantation

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Electro-thermal effects in mixed-mode device simulation

Electro-thermal effects in mixed-mode device simulation

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International conference on Semiconductor

作者： T. Grasser S. Selberherr TU Vienna Institute for Microelectronics Vienna Austria

Due to the ever increasing packaging density of integrated circuits, self-heating and thermal coupling effects become more and more important. For state-of-the-art mixed-mode device simulation the solution of the basic transport equations for the semiconductor devices is directly embedded into the solution procedure for the circuit equations. Compact modeling is thus avoided and much high accuracy is obtained which is especially true for the temperature dependence of the device terminal characteristics. We review the state of the art in mixed-mode device simulation with particular emphases placed on self-heating of individual and thermal coupling effects between different devices.

关键词： Circuit simulation Semiconductor process modeling Medical simulation Nonlinear equations Algorithm design and analysis SPICE MOSFETs Geometry Doping profiles Solid modeling

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SOI at IBM: current status of technology, modeling, design, and the outlook for the 0.1 /spl mu/m generation

SOI at IBM: current status of technology, modeling, design, ...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： F. Assaderaghi G. Shahidi IBM Semiconductor Research and Development Center Hopewell Junction NY USA

This paper reviews the evolution of partially depleted (PD) CMOS SOI technology at IBM. Several aspects of this development leading to successful fabrication of high-performance microprocessors are discussed. They include SOI-specific device design and process modifications; creation of compact device models for circuit simulation (SPICE-like models); and development of circuit styles and strategies employed in the design of CMOS VLSI on PD SOI. Since these strategies address issues and problems that arise on PD SOI circuits such as delay hysteresis, and noise margin reduction, they are discussed in detail. The discussion is focused on the 0.18 /spl mu/m and 0.13 /spl mu/m generations, with some deliberations on the 0.10 /spl mu/m node.

关键词： CMOS technology Semiconductor device modeling Fabrication Microprocessors Process design Circuit simulation CMOS process Very large scale integration Delay Hysteresis

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Thermal characterization of vias using compact models

Thermal characterization of vias using compact models

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Electronics Packaging Technology conference (EPTC)

作者： D. Pinjala M.K. Iyer Chow Seng Guan I.J. Rasiah Institute of Microelectronics Singapore ST Assembly Test Services Private Limited Singapore Honeywell (S) Private Limited Singapore

ISBN: (纸本)0780366441

Thermal vias and balls are key elements in plastic ball grid array (PBGA) package thermal design as they enhance the package performance. simulation is a versatile design optimization tool for characterizing the thermal vias and balls. However, the finer geometric details of the vias require excessive memory and modeling and simulation time. Different modeling concepts are being tried in the industry to include finer geometries in the package. This paper shows a methodology of developing compact thermal via models and validating the same with detailed models. The accuracy of compact thermal via models with respect to the detailed models has been determined using PBGA 352 as the test vehicle. It is found that the accuracy is within 3%. The simulation models of PBGA 352 have been validated by measurements and found that the accuracy of model is within 10%. Two and four layer PBGA 352s with different via configurations have been characterized with compact thermal via models, and design guidelines for PBGA 352 packages have been obtained.

关键词： Electronic packaging thermal management Thermal conductivity Solid modeling Dielectric substrates Testing Copper Electronics packaging Plastic packaging Vehicles Guidelines

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Control and dynamic analysis of a static VAr compensator using a three level inverter topology

Control and dynamic analysis of a static VAr compensator usi...

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International conference on microelectronics, ICM

作者： A. Draou M. Benghanem A. Tahri Applied Power Electronics Laboratory Institute of Electrotechnics University of Sciences and Technology Houari Boumediene Oran Algeria

ISBN: (纸本)9643600572

This paper presents a novel study of the dynamic performance analysis of an advanced static VAr compensator (ASVC) using a three-level voltage source inverter. The analysis is based on the modelling of the system in the d-q axis. The dynamic behaviour of the system is further analysed using MATLAB through a set of simulation tests. The results obtained may lead to correct design of a robust controller for reactive power applications.

关键词： Static VAr compensators Performance analysis Voltage Inverters Mathematical model Power system modeling MATLAB Analytical models System testing Robust control

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