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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1418 条记录，以下是1261-1270 订阅

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A Virtual Platform for Performance Estimation of Many-core Implementations

A Virtual Platform for Performance Estimation of Many-core I...

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Euromicro Symposium on Digital System design

作者： Javier González-Bayón Pablo Sánchez Espeso Pablo González de_Aledo Marugán Microelectron. Eng. Group Univ. of Cantabria Santander Spain Microelectronics Engineering Group University of Cantabria Santander Spain Universidad de Cantabria Santander Cantabria ES

This paper presents a prototype for a virtual platform to estimate performance of OpenMP parallelized programs in shared-memory many-core platforms at early stages of the design flow. This is a challenging problem because, at these stages, the particular details of the final platform are unknown, but early performance estimations are needed to choose between different parallel implementations. The tool presented enables fast modelling of the SW and HW components in a complete platform model and also has the advantage of enabling configurable models of any many-core platform. This can be achieved because of two novel ideas that are explained in this paper: a native simulation framework that enables the modelling of concurrent threads described in OpenMP and a novel use of "shared" and "private" clauses that models the data transfers. The advantages of using the proposed tool are explained with a specific example.

关键词： Estimation Computational modeling Computer architecture Data models Instruction sets Prototypes

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modeling the Thermal Characteristics of Stacked 2T0C Memory Array Based on InGaZnO4 Thin-film Transistors

Modeling the Thermal Characteristics of Stacked 2T0C Memory ...

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International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Song He Haoxin Li Guangwei Xu Xinyi Tang Yuanbiao Li Jaewoo Kim Tingting Gu Xingkun Xue Zelun Li Handong Xu Haiyang Dong Kai Zhou Xianqin Hu Shibing Long School of Microelectronics University of Science and Technology of China Hefei China Changxin Memory Technologies Inc. Hefei China

For the first time, the electrothermal characteristics of the stacked 2T0C memory array were modeled based on the material properties, electron transport mechanism of InGaZnO 4 (IGZO) and basic Fourier heat flow equation utilizing the technology computer-aided design (TCAD) tool. According to the proposed electrothermal model, the multi-layer stacked 2T0C memory array would bring severe self-heating issue from the thermal crosstalk among layers. The temperature rising of stacked 2T0C cells decrease the retention time severely due to the temperature instability of IGZO thin-film transistors TFTs. Furthermore, several advanced device-level strategies were proposed to ameliorate the heat accumulation problem.

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Analysis and Test of Time Difference Measurement IP Based on FIB

Analysis and Test of Time Difference Measurement IP Based on...

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2018 2nd International conference on modeling, simulation and Optimization Technologies and Applications(MSOTA 2018)

作者： Jun DENG Ke-liu HU Tao ZHANG Hao LUO Kun HUANG Sichuan Institute of Solid-state Circuits School of Microelectronics and Communication Engineering Chongqing University

With the development of semiconductor technology, how to locate and verify the problems found in chip testing becomes the key of the chip design. In the test of time difference measurement IP chip, test results find that the phase shift output does not correspond with the design requirements. After analyzing the circuit, the leakage current of refresh circuit is found. The FIB(Focused Ion Beam) technology is adopted to modify the physical circuit. The circuit is tested after FIB. The result shows that the judgement and analysis of the crux of the problem is correct. Through FIB, not only the problem is found, but also the function and performance of the chip are tested rapidly. The purpose of rapid verification is achieved, and the modification time is saved. Using FIB can help to reduce the cost of chip design sometimes.

关键词： IC Test leakage current FIB(Focused Ion Beam) Verification

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design and Optimization of Bump Structures of Large Die Fine Pitch Copper/Low-k FCBGA and Copper Post Interconnections

Design and Optimization of Bump Structures of Large Die Fine...

引用

Electronics Packaging Technology conference (EPTC)

作者： Kalyan Biswas Shiguo Liu Xiaowu Zhang TC Chai IBIDEN Singapore Private Limited Singapore Singapore Institute of Microelectronics Singapore

This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design, metal cracks at RDL were found for the conventional SnAg bump and Cu post samples. In order to improve the bump structure design a thermo-mechanical modeling was performed to identify the effects of different design parameters and to identify the best solution to achieve reliable assembly performance. simulation has identified few contributing factors: RDL pad thickness, dielectric thickness, UBM via size, UBM size and chip thickness. Then a series of parametric study was performed to identify the set of design points at which the finite element analysis provides the lowest stress level in RDL pad and low-k layer of the chip. Based on the results a guideline for bump configuration is proposed. To confirm the assembly performance of the optimized bump structure, the improved design has been incorporated into final test vehicle, which has a better assembly performance with no RDL pad metal crack found.

关键词： Copper design optimization Assembly Thermomechanical processes Dielectrics Parametric study Finite element methods Performance analysis Stress Guidelines

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An Efficient 90nm Technology-Node GHz Transceiver of On-Chip Global Interconnect

An Efficient 90nm Technology-Node GHz Transceiver of On-Chip...

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2011 IEEE 9th International conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

作者： Zaixiao Zheng Zhigang Mao Jianfei Jiang Department of Microelectronics Shanghai JiaoTong University Shanghai 200240. China

Today high speed signal transmission system for on chip global interconnect requires elaborate design of the transceiver. The design goal of transceiver is to ensure the transmission obtains 'an improvement in latency and power, which are the two most important factors in high speed transmission. In this paper, we present an efficient structured transceiver which implements low swing technology based on the differential structure with the accurate modeling of the on chip global interconnect. And we give the principals of the structure and compare the optimized simulation results with the traditional inverter insertion method used to decrease the delay of the global interconnect. Our transceiver design is based on the 90nm CMOS technology and TSMC 90nm interconnect structure on Metal 5. The global interconnect length we focus on is the general length 10mm. Compared to repeater insertion, this system has a latency advantage of 17％ and remarkable advantage in power up to 33.9％.

关键词： 90nm technology Differential transmission Low swing 3-D multi-level modeling

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Quick generation of temporal power waveforms for RT-level hard macros

Quick generation of temporal power waveforms for RT-level ha...

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IEEE International conference on Innovative Systems in Silicon

作者： L. Benini G. De Micheli E. Macii M. Poncino R. Scarsi Computer Systems Laboratory University of Stanford Stanford CA USA Dip. di Automatica e Informatica Politecnico di Torino Torino Italy

Power characterization of complex macros is essential to enable accurate RT-level power estimation. Existing characterization procedures focus on the average value of power. In this paper, we take a fresh look at this problem. We propose a fast, yet accurate technique to determine a time-dependent power model, i.e., a temporal power waveform, which is able to fully characterize the power behavior of a hard macro in response to a realistic input stream consisting of typical usage patterns. Our approach is simulation-based, and resorts to a mix of high-level, fast cycle-based simulation with low-level, slow accurate simulation of the long set of input patterns. Results are extremely satisfactory, since the average error between the power waveforms generated by our tool and the exact ones is always within 1%, while the reduction in the execution time ranges between one and two orders of magnitude.

关键词： Power generation Libraries Computational modeling Character generation Energy consumption Hardware design languages Laboratories Circuit simulation microelectronics Silicon

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LSTM-based ECG Signal Classification with Multi-level One-hot Encoding for Wearable Applications

LSTM-based ECG Signal Classification with Multi-level One-ho...

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IEEE Biomedical Circuits and Systems (BIOCAS)

作者： Jinhai Hu Wang Ling Goh Yuan Gao School of Electrical and Electronic Engineering Nanyang Technological University (NTU) Republic of Singapore Agency for Science Technology and Research (A*STAR) Institute of Microelectronics (IME) Republic of Singapore

ISBN: (数字)9798350354959

ISBN: (纸本)9798350354966

This paper presents an electrocardiogram (ECG) signal classification method using one-hot coding scheme and Long Short-Term Memory (LSTM) neural network. Instead of the conventional analog to digital converter (ADC) with two’s complement binary output, one-hot encoding scheme is adopted in this design to convert the analog signal to 1D vector and then further processed by a LSTM network for classification. Our study shows that one-hot encoding can effectively represent the features of ECG signal with low data bit-width and sampling rate. The proposed method not only simplifies the ADC design, but also improves the classification accuracy. simulation results show that the proposed design only requires 5-bit bit-width with 50 Hz sampling rate to achieve 96.9% validation accuracy on 5-class classification task using MIT-BIH ECG dataset.

关键词： Semiconductor device modeling Accuracy simulation Pattern classification Electrocardiography Encoding Vectors Hardware Long short term memory Analog-digital conversion

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Verification of transaction-level SystemC models using RTL testbenches 03

Verification of transaction-level SystemC models using RTL t...

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ACM and IEEE International conference on Formal Methods and Models for Co-design (MEMOCODE)

作者： R. Jindal K. Jain CRnD STMicroelectronics India

ISBN: (纸本)9780769519234

System architects working on SoC design have traditionally been hampered by the lack of a coherent methodology for architecture evaluation and co-verification of hardware and software. SystemC 2.0 facilitates the development of transaction-level models (TLMs), which are models of the hardware system components at higher level of abstraction than RTL. Due to lower modeling effort yet higher simulation speed, TLMs are useful for architectural exploration, algorithmic evaluation, hardware-software partitioning and software development. The problems posed by SOC design methodologies require development of models at higher abstraction also for the earlier developed IP's. The development time of a TLM IP is already low, so if we can reduce the verification time by re-use of the earlier RTL test benches we can reduce the overall cost of such an IP TLM. This paper focuses on the methodology to use the RTL testbenches for verification of a SystemC model of the same IP at a higher abstraction level (transaction level), some tools available in the market to support this testbench reuse and the implementation challenges posed by the mentioned verification technique.

关键词： System testing Costs Hardware microelectronics design methodology design engineering Yarn Partitioning algorithms Software algorithms Programming

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Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis

Energy Conscious Simultaneous Voltage Scaling and On-chip Co...

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IFIP International conference on Very Large Scale Integration (VLSI-SoC)

作者： Sujan Pandey Tudor Murgan Manfred Glesner Institute of Microelectronics Systems Darmstadt University of Technology Darmstadt Germany

Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of an entire system. However, the resulting architecture may not fulfil the requirements such as the performance, energy, size etc. and the computational cost of simulation based techniques is infeasible when exploring a large design space. This paper presents a simultaneous on-chip communication bus synthesis and voltage scaling approach, which is modeled in NLP (nonlinear programming) and finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The voltages (supply and body bias) are scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 57.1% by scaling its supply and body bias voltages

关键词： Voltage Computer architecture Topology System-on-a-chip Computational modeling Energy consumption Energy efficiency Computational efficiency Libraries Embedded system

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design and optimization of double-gate SOI MOSFETs for low voltage low power circuits

Design and optimization of double-gate SOI MOSFETs for low v...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： L. Wei Z. Chen K. Roy Purdue University West Lafayette IN USA

With the growing use of portable and wireless electronic systems, design of high performance, low-voltage, low-power digital devices and circuits has become an important concern for VLSI applications. The double-gate (DG) fully-depleted (FD) silicon-on-insulator (SOI) MOSFET has an ideal subthreshold slope, high drive current and superb short channel effect immunity, which makes it very attractive in low-voltage, low-power, and high-performance CMOS designs. In this paper, by solving the Poisson equation, we propose a general model which has been verified by SOI-SPICE simulations. Based on this model, DGSOI MOSFETs are compared with conventional single gate FD SOI (SGSOI) MOSFETs, and the design and optimization of DGSOI MOSFETs in terms of circuit delay, power dissipation and power delay product are presented. In our analysis, we focus on FD DGSOI transistors without volume inversion, where the classical method is still valid.

关键词： design optimization MOSFETs Low voltage Semiconductor device modeling Delay Very large scale integration Silicon on insulator technology Poisson equations Circuit simulation Power dissipation

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