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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是1271-1280 订阅

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Optimizing the simulation of bipolar transistor packages using sliding mode techniques

Optimizing the simulation of bipolar transistor packages usi...

引用

conference on design, Characterization, and Packaging for MEMS and microelectronics

作者： Mkrttchian, V Simonyan, A Mkrtchyan, K Stat Engn Univ Armenia Yerevan 375009 Armenia

ISBN: (纸本)0819434949

modeling packaged electronic elements is encumbered by parasitic effects and discontinuities causing enlarged parameters and is done using numerical field simulation in reference to results of on-wafer measurements and calculated emitter inductance. Package simulation has revealed certain problems with discontinuities and disruption of automatic adjustment that can be eliminated using the sliding mode characterized by reduced order of mathematical support and feedback from discontinuities. Analysis of bipolar transistor models shows inadequacies of currently accepted concepts of dynamic systems, with high factors of uncertainty due to unambiguous solutions. RF measurements of prospective transistors can be done using wafer measuring techniques. The smooth RF characteristics of the interior transistor as well as a limited number of parameters yield a model with good agreement for both DC- and RF characteristics. It is our purpose to achieve a model suitable for use with all types of circuit simulations. The ports for chip connection are concentrated or internal ports defined by voltage and current. The resulting S-parameters of the ports are used to extract equivalent circuit elements leading to well define values with physical sense. The essential components of the packaging model are the sliding mode indicator, observer and the anticipatory device.

关键词： simulation sliding mode indicator observer the anticipatory device

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Interconnect modeling in deep submicron design 6

Interconnect modeling in deep submicron design

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6th International conference on VLSI and CAD, ICVC 1999

作者： Oh, Soo-Young Jung, Won-Young Kong, Jeong-Taek Lee, Keun-Ho Verilux Design Technol. 830 E. Arques Avenue SunnyvaleCA94086 United States Samsung Electronics Co. LTD. San #24 Neungseo-Ri Kiheung-Eup Yongin-City Kyungki-Do Korea Republic of

ISBN: (纸本)0780357272

As scaling has continued for more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 μm as proposed in the SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multimillion transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed, including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. Then advanced topics of interconnect modeling in deep submicron are reviewed;statistical interconnect modeling, 3-D Monte Carlo simulation for global nets, and 3-D inductance modeling. © 1999 IEEE.

关键词： Monte Carlo methods

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A large signal elements' simulation of GaAs MESFET using neural network model

A large signal elements' simulation of GaAs MESFET using neu...

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1999 International conference on Computational Electromagnetics and its Applications. ICCEA 1999

作者： Gao, Yifan Gu, Cong Xi'An Highway Univ. China China Shannxi Lishan Microelectronics Institute Xi'an Shaanxi710054 China

ISBN: (纸本)0780358023

Neural networks are important as fast and flexible tools for microwave modeling, simulation, optimization and design. A new approach of a neural-network based model is proposed to determine the large signal elements of a GaAs MESFET. To conveniently implement this in standard circuit simulators, we extracted the single-cell GaAs MESFET's bias-dependent behavior in terms of conventional small signal equivalent circuit elements. We represented seven intrinsic elements with a four-layered neural network whose inputs are the gate-to-source bias and drain-to-source bias. A »well-trained» neural network shows excellent accuracy and generates good extractions. The results of calculation between the new neural model and improved optimization are in good agreement. © 1999 IEEE.

关键词： Gallium arsenide

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A model of a 300 mm wafer fabrication line

A model of a 300 mm wafer fabrication line

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simulation Winter conference

作者： P.L. Campbell D. Rohan E.A. MacNair IBM Microelectronics Division East Fishkill NY USA IBM Thomas J. Watson Research Center Yorktown Heights NY USA

Semiconductor factories are very expensive to build and operate. It is critical to understand how to design and operate them efficiently. We describe a simulation model of a planned 300-mm wafer fabrication line that ... 详细信息

关键词： Semiconductor device modeling Fabrication Materials handling Routing Production facilities Sampling methods Metrology Vehicles microelectronics Virtual manufacturing

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A computationally efficient method for three-dimensional simulation of ion implantation

A computationally efficient method for three-dimensional sim...

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International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： A. Burenkov K. Tietzel A. Hossinger J. Lorenz H. Ryssel S. Selberherr Bauelemente Technologie Fraunhofer Institut für Integrierte Schaltungen Erlangen Germany Institute for Microelectronics Technische Universitat Vienna Vienna Austria

The high accuracy which is necessary for modern process simulation often requires the use of Monte-Carlo ion implantation simulation methods, with the disadvantage of very long simulation times especially for three-dimensional applications. In this work a new method for an accurate and CPU time efficient three-dimensional simulation of ion implantation is suggested. The approach is based on a combination of the algorithmic capabilities of fast analytical and the Monte-Carlo simulation methods.

关键词： Computational modeling Ion implantation Analytical models Distribution functions Algorithm design and analysis Ion beams Crystallization Doping profiles microelectronics Convolution

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Implementation of statistical characterisation and design techniques for an industrial 0.5 /spl mu/m CMOS technology

Implementation of statistical characterisation and design te...

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IEEE International conference on Microelectronic Test Structures

作者： S. Healy E. Horan K. McCarthy A. Mathewson Zhenqiu Ning E. Rombouts W. Vanderbauwhede M. Tack National Microelectronics Research Centre Cork Ireland Alcatel Microelectronics Oudenaarde Belgium

This paper presents a methodology for statistical worst-case simulation using the BSIM3v3 model within commercially available tools. Statistical techniques such as principal component analysis and Box-Behnken designs are used to generate a subset of models which reflect the variation of measured device performance. These worst-case corners can be used in circuit simulation to account for the effects of statistical fluctuation on circuit performance. An indication of key process parameters that need to be monitored and controlled is also provided.

关键词： Tellurium Data mining Semiconductor device modeling Parameter extraction MOS devices CMOS technology microelectronics Circuit simulation CMOS process Performance analysis

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Computer aided optimum design of broadband microwave VCO's

Computer aided optimum design of broadband microwave VCO's

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International conference on microelectronics, ICM

作者： C. Ghennai M.J. Howes Institute of Electrical Eng University of Batna Algeria Department of Electronic & Electrical Eng University of Leeds UK

Microwave solid-state voltage-controlled oscillators (VCOs) are the keystone components in various microwave systems. Thus far, achievements in practical realisation of such circuits rely on measured data or approximate equivalent circuit models of the solid-state devices. In this contribution, a new overall computer aided optimum design program for transferred electron VCOs is presented. The established program is based on the optimisation of the coupling between the transferred-electron device (TED) and the tuning device for wide tuning bandwidth. Practical realisation has been carried out at J-band and comparison between simulation and experimental results shows excellent agreement.

关键词： Microwave devices Solid state circuits Circuit optimization Tuning Voltage-controlled oscillators Equivalent circuits Solid modeling Electrons Coupling circuits Bandwidth

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Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits

Detailed analysis of the gate delay variability in partially...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： I. Aller K.E. Kroell IBM Entwicklung GmbH Boeblingen Germany

Circuit design using partially depleted (PD) SOI FETs must take into account a variable gate delay which is dependent on the switching history of the circuits (Gautier et al, 1997; Houston and Unnikrishnan, 1998). In order to fully exploit the advantages of SOI, it is important to understand and analyze such 'history effects' and consider them for an optimized design strategy. In this paper, we describe a methodology suitable to analyze PD SOI CMOS circuits, including a new algorithm for dynamic equilibrium computations, a task that is not practicable with standard circuit simulators because of the very slow evolution of the body potential (time constants up to ms (Assaderaghi et al., 1996)). simulation results for a 0.2 /spl mu/m technology are given, showing the importance of design and application parameters with regard to the history effect.

关键词： Delay History Computational modeling Circuit simulation Circuit synthesis FETs Switching circuits design optimization Algorithm design and analysis Heuristic algorithms

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A two stages MMIC CDMA power amplifier using harmonic load pull simulation technique

A two stages MMIC CDMA power amplifier using harmonic load p...

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Asia-Pacific conference on Microwave

作者： Jiang Cao R. Singh Bo Liang Xinwei Wang Khoo Ee Sze H. Nakamura Institute of Microelectronics Singapore Oki Techno Centre Singapore Private Limited Singapore

This paper reports a two stages MMIC power amplifier with low quiescent current and high power added efficiency (PAE) for PCS CDMA application. Based on an accurate large signal PHEMT model, a systematic load (source) pull simulation scheme was developed to design the linear power amplifier. The two stages PCS CDMA PA attained over 40% PAE, 28.5 dBm output power and 18.5 dB gain at -45 dBc adjacent channel power rejection (ACPR) under a supply voltage of 3.6 V. The total quiescent current is only 110 mA. The chip size of the amplifier is 0.86/spl times/1.24 mm and assembled in 16 pins HS-SSOP plastic package.

关键词： MMICs Multiaccess communication Power amplifiers Power system harmonics Personal communication networks High power amplifiers PHEMTs Load modeling Power system modeling Signal design

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Operational simulation of an X-ray lithography cell: comparison of 200 mm and 300 mm wafers

Operational simulation of an X-ray lithography cell: compari...

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simulation Winter conference

作者： K.P. White W.J. Trybula Department of Systems Engineering Institute for Microelectronics University of Virginia Charlottesville VA USA International Sematech Inc. Austin TX USA

We review progress on a project to evaluate prospective operations in a semiconductor wafer fab that employs next generation, proximity X-ray lithography to pattern the critical dimensions of computer chips. A simulation model is developed that captures the processing of wafers through an X-ray lithography cell using a synchrotron as the source of exposure radiation. The model incorporates the best current information on unit-cell design and processing times and implements a range of events that interrupt the flow of wafers processing on the cell. Performance measures estimated from the simulation include the weekly throughput for the cell and the frequency of SEMI E-10 equipment states for the corresponding exposure tool. simulation experiments are conducted to compare the performance of a cell fabricating 200 mm wafers with that of a cell fabricating 300 mm wafers, for each of three different chip sizes. Results illustrate the anticipated dependence of average wafer throughput on wafer size and assumptions regarding the number of chips per wafer, with a maximum of approximately 3400 wafers/week for 200 mm wafers with 25/spl times/25 mm field size. Ignoring wafer-sort losses, however, a maximum throughput of approximately 410,000 chips/week is realized for 300 mm wafers with 11/spl times/22 mm fields. Remarkably, the distribution of equipment states remains relatively unchanged across simulation experiments.

关键词： X-ray lithography Synchrotrons Throughput Production Costs Semiconductor device modeling Frequency estimation Ultraviolet sources Systems engineering and theory microelectronics

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