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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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design of a Low-Dropout Linear Regulator

Design of a Low-Dropout Linear Regulator

引用

Artificial Intelligence and Information Systems (ICAIIS), 2020 IEEE International conference on

作者： Enyu Xu Xuehong He School of Microelectronics Shanghai Jiao Tong University Shanghai China Shanghai Integrated Circuit Research and Development Center Ltd. Shanghai China

ISBN: (数字)9781728165905

ISBN: (纸本)9781728165912

This paper introduces a low-dropout linear regulator with an operating voltage of 2.5V. An anti-overshoot circuit is added to the error amplifier, and the regulator module is optimized based on circuit stability performance; Add trim function to feedback resistance network so that LDO can output different voltage values such as 1.1V, 1.8V and 2.2V according to various needs. The circuit is simulated by Cadence based on HLMC 40nm CMOS process. The results show that the LDO has a minimum rejection ratio of -35dB and a maximum of -56dB.

关键词： Regulators Circuit stability Voltage control Transistors simulation Photonic band gap Integrated circuit modeling

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Fracture mechanics based crack and delamination risk evaluation and RSM/DOE concepts for advanced microelectronics applications

Fracture mechanics based crack and delamination risk evaluat...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： J. Auersperg B. Seiler E. Cadalen R. Dudek B. Michel Department Mechanical Reliability and Micro Materials Fraunhofer Institute of Reliability and Microintegration (IZM) Berlin Germany AMIC Angewandte Micro-Messtechnik GmbH Berlin Germany CWM Chemnitzer Werkstoffmechanik GmbH Chemnitz Germany THALES Microelectronics S. A. Chateaubourg France

Fatigue and failure of advanced electronic packages and related systems is often caused by their increasing use under harsh environmental conditions - extreme temperatures, in particular. As a result, its thermomechanical reliability becomes more and more one of the most important preconditions for adopting it in industrial applications. Residual stresses from several steps of the manufacturing process, thermal and static and dynamic mechanical loading conditions along with the fact that microelectronic packages are basically compounds of materials with quite different Young's modules and thermal expansion coefficients contribute to interface delamination, chip cracking and fatigue of interconnects. Consequently, numerical investigations by means of nonlinear parameterized FEA, fracture mechanics concepts are frequently used for design optimizations using sensitivity analyses (Auersperg et al., 2001). So, numerical design studies can help to optimize designs of electronics applications at the earlier phase of the product development processes. Unfortunately, this methodology typically accounts for classical stress/strain evaluation or life-time estimations of solder interconnects using modified Coffin-Manson approaches. Delamination or bulk fracture mechanisms usually remain unconsidered. This contribution intends to figure out and discuss ways of using fracture mechanics numerical approaches in connection with parameterized FEA based DOE/RSM. For improving such methods, the evaluation of mixed mode interface delamination phenomena of several ceramics/encapsulant-specimens under bending has been combined with experimental deformation measurements. Measured force vs. deflection curves, deformation fields as results of optical inspection and deformation analysis as well as crack tip vs. deflection curves determined using constitute the input for the delamination modeling by means of FEM. Major goal of the study is to make such a way determined interface toughness para

关键词： Delamination US Department of Energy microelectronics Electronic packaging thermal management Fatigue Thermal expansion Thermal loading Thermal stresses design optimization Force measurement

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Predictive fatigue life equation for CBGA electronic packages based on design parameters

Predictive fatigue life equation for CBGA electronic package...

引用

Intersociety conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM)

作者： A. Perkins S.K. Sitaraman Computer Aided Simulation for Package Reliability (CASPaR) Laboratory The George W. W&ff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA

Finite-element simulations in combination with experimental data have been used extensively by researchers to predict the solder joint fatigue life in microelectronic packages. Such simulations often require good understanding of finite-element modeling, physics-based failure models, and time-, temperature-, and direction-dependent material constitutive behavior. Also, such simulations are computationally expensive and time-consuming. Microelectronic package designers do not have the time and the expertise to perform such simulations. Therefore, this work aims to develop predictive equations that are easy to use and are based on physics-based modeling. Using experimental data and finite-element simulations, this work has developed a polynomial predictive equation for solder fatigue life in a ceramic ball grid array (CBGA) package. The developed equation has been validated with other experimental data with good success. Efforts are underway to develop similar equations for other packages.

关键词： Fatigue Equations Electronics packaging Computational modeling Finite element methods Predictive models microelectronics Soldering Polynomials Ceramics

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Analyse of Protection Devices' Speed Performance against ESD under CDM Using TCAD

Analyse of Protection Devices' Speed Performance against ESD...

引用

IEEE conference on Electron Devices and Solid-State Circuits

作者： Qiang Cui Yan Han Juin J. Liou Shurong Dong Institute of Microelectronics and Photoelectronics University of Zhejiang Hangzhou China Department of Electrical and Computer Engineering University of Central Florida Orlando FL USA

ISBN: (纸本)9781424406364

Speed performance plays a critical role in protection devices against ESD (Electro-Static Discharge) overstress under CDM (Charged Device Model). It is too demanding to obtain speed performance of protection devices under CDM accurately by testing. Therefore we have to resort to TCAD (Technology Computer Aided design) method to evaluate speed performance under CDM. This TCAD methodology is based on mix-mode transient circuit simulation, which depicts ESD events better. Two time constants, T trigger and T recover , and two key coefficients, F trigger and C recover , are provided to characterize and evaluate speed performance of ESD protection devices. The results show that this TCAD methodology has a good ability of convergence and is a good tool to evaluate speed performance of ESD protection devices quantificationally. Anlayse results show that speed performance of SCR is superior over ggNMOS in not only triggering but also bypassing ESD currents to recover the voltage towards a safe level.

关键词： Performance analysis Protection Electrostatic discharge Circuit simulation Thyristors Biological system modeling Integrated circuit modeling Impact ionization Voltage Anodes

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Modernization of Low-Temperature JFET Models Built into LTspice CAD Systems, Taking into Account the Results of their Experimental Study

Modernization of Low-Temperature JFET Models Built into LTsp...

引用

Latin American Electron Devices conference (LAEDC)

作者： Oleg V. Dvornikov Valentine L. Dziatlau Vladimir A. Tchekhovski Nikolay N. Prokopenko Alexey A. Zhuk Anna V. Bugakova Plc. “Minsk Research Instrument-Making Institute” (MNIPI) Kolas's str. 73 Minsk Belarus Institute for Nuclear Problems of Belarussian State University Bobruiskaya str. 11 Minsk Belarus Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Sovetskaya st. 3 Zelenograd Russia Don State Technical University Gagarin's sq. 1 Rostov-on-Don Don State Technical University Rostov-on-Don (RR) Russia

ISBN: (数字)9781728110448

ISBN: (纸本)9781728110455

The results of experimental studies of the current-voltage characteristics (CVC) of silicon n-JFET and p-JFET manufactured at JSC INTEGRAL (Minsk, Belarus) at temperatures from minus 195°C up to 30°C are considered. A hardware-software complex and a JFET automated measurement technique are created. Refined approximations of the temperature dependences of the Spice parameters of JFETs are given, which provide a good agreement between the results of measurements and simulation of the CVC. The created models are intended primarily for computer simulation of low-temperature effects in analog ICs in the LTspice CAD.

关键词： Temperature measurement JFETs Solid modeling Semiconductor device measurement Logic gates Integrated circuit modeling Temperature

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IR drop analysis in mobile IC package with consideration of self-heating and leakage power

IR drop analysis in mobile IC package with consideration of ...

引用

Electronic Components and Technology conference (ECTC)

作者： Zheng Qin Zhi Wang He Ma Shuqiang Zhang Daquan Yu Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Science Beijing China Apache Design Solutions Inc. Shanghai China

ISBN: (纸本)9781479986101

Due to the high integration and high speed, Power-Ground (P/G) network design becomes a critical challenge in mobile IC package. As accurate IR-drop analysis provides important reference for P/G network design, an electro-thermal coanalysis flow is presented in this paper to obtain accurate IRdrop distribution of a low-power mobile IC package. In this analysis process, the change of temperature-dependent leakage power caused by device heating and self-heating is considered when IR-drop analysis is performed, which has seriously impact on IR-drop. In this paper, a two-layer high-density FCBGA (Flip Chip Ball Grid Array) package is used for analysis and the simulation result shows that the IR-drop on package increases by 16.1% when considering leakage power and self-heating.

关键词： Thermal analysis Heating Electronic packaging thermal management Integrated circuit modeling Metals Mobile communication

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Parity Generator & Parity Checker Using Sub-threshold Adiabatic Logic

Parity Generator & Parity Checker Using Sub-threshold Adiaba...

引用

IEEE UP Section conference on Electrical Computer and Electronics (UPCON)

作者： Prashant Gaurav Prashant Sangeeta Singh Saurabh Kumar Pandey Microelectronics and VLSI design NIT Patna Bihar India Sensors and Optoelectronics Research Group (SORG) Indian Institute of Technology Patna Bihta Bihar India

ISBN: (数字)9781665403733

ISBN: (纸本)9781665447478

Power dissipation becomes an essential criterion in VLSI system in the current ultra-low power applications scenario. Sub-threshold adiabatic logic designing has shown its potential as more efficient logic for ultra low energy-consuming circuits. Parity generator and parity checker are important combination circuit for error-free transmission of data. Both of these circuits are widely used for communication to encode the data. These circuits are realized using sub-threshold adiabatic logic (SAL) by deploying CADENCE 45nm technology. Extensive simulation study has been carried out to validate the mathematical expressions. Our study validates the enhanced circuit performance using sub-threshold adiabatic logic. The present work will facilitate researchers for circuit realization for energy applications.

关键词： Semiconductor device modeling Adiabatic Very large scale integration Generators Power dissipation Recycling Integrated circuit modeling

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Characterization and simulation of LTCC/adhesive and alloy 42/adhesive interface strength for automotive applications

Characterization and simulation of LTCC/adhesive and alloy 4...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： B. Öztürk P. Lou P. Gromala C. Silber K.M.B. Jansen L.J. Ernst Robert Bosch GmbH Automotive Electronics Reutlingen Germany Delft University of Technology Delft The Netherlands Ernst Consultant Schoonhoven Schoonhoven The Netherlands Emeritus Professor of Delft University of Technology The Netherlands

Thermoset-based adhesives are used as thermal and electrical interfaces. In automotive applications, they are required to have excellent adhesion since delamination may precipitate other electrical, thermal or mechanical failure mechanisms. A vast amount of literature is available on the investigation of molding compounds and various material interfaces. However, only very few studies focus on delamination of adhesive interfaces. The reason is that apparently it was not possible to initiate an interface crack in a delamination sample. In various attempts, random cracking in the adhesive was obtained instead. Yet interface cracks are found in real products and really form a reliability issue. But so far the absence of adequate interface strength data makes it hardly possible to design for reliability of products with adhesive interfaces. The present paper solves the above problem. We succeeded to get an interface delamination between the adhesive and two different materials (e.g. Low temperature cofrred ceramic (L TCC) and alloy 42). The specimens are made by identical fabrications processes as during the fabrication of the electronic control unit under study. The interface to be investigated is preconditioned for delamination initiation, by adding a single step to the fabrication process, thus enabling the investigation of different interfaces that have the same processing conditions as the real product. The presented specimen preparation method and the testing methodology can be used for determination of critical adhesion properties of different interfaces (including brittle materials like L TCC) in electronic control units. Specimens are investigated by delamination experiments near Mode-I loading conditions at room temperature. The obtained interface data is interpreted via image processing and finite element modeling of the J-integral method. In particular, cohesive zone modeling is used to validate the critical energy release rates for different interfaces.

关键词： Thermomechanical processes Materials reliability Iron Numerical models Electromagnetic compatibility Heating

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A Compact Model of Resistive Switching Devices

A Compact Model of Resistive Switching Devices

引用

2010 10th IEEE International conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： B. Chen J.F. Kang R.Q. Han Y.S. Chen K.L. Wei Q.Y.Jun X.Y. Liu B. Gao F.F. Zhang L.F. Liu Peking University Shenzhen Graduate School Shenzhen 518055 China Institute of Microelectronics Pe Institute of Microelectronics Peking University Beijing 100871 China

In this paper a compact model both for bipolar and unipolar resistive switching device is proposed. Basic I-V characteristics of RRAM are easily and correctly represented by this model. The model is verified by the bi... 详细信息

ISBN: (纸本)9781424457977

关键词： Switches Integrated circuit modeling Resistance Process control Fluctuations Voltage control Circuit simulation

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A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits 03

A CAD framework for co-design and analysis of CMOS-SET hybri...

引用

IEEE International conference on Computer-Aided design

作者： S. Mahapatra K. Banerjee F. Pegeon A.M. Ionescu Electronics Laboratory (LEG) Institute of Microelectronics and Microsystems (IMM) Swiss Federal Institute of Technology Lausanne Switzerland Electronics Laboratory (LEG) Swiss Federal Institute of Technology Lausanne (EPFL) Lausanne Switzerland Department of Electrical & Computer Engineering University of California Santa Barbara CA USA Silvaco Data Systems Inc. Grenoble France Silvaco Data Systems Grenoble France

ISBN: (纸本)9781581137620

This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. Particularly, the extension of the recent MIB model for single/multi gate symmetric/asymmetric device for a wide range of drain to source voltage and temperature is addressed. Circuit level co-simulations are successfully performed by implementing the SET analytical model in Analog Hardware Description Language (AHDL) of a professional circuit simulator SMARTSPICE. Validation at device and circuit level is carried out by Monte-Carlo simulations. Some novel functionality hybrid CMOS-SET circuit characteristics: (i) SET neuron, (ii) Multiple valued logic circuit and (iii) a new Negative Differential Resistance (NDR) circuit, are also predicted by the proposed SET model and analyzed using the new hybrid simulator.

关键词： Hybrid integrated circuits Analytical models Circuit simulation Predictive models Single electron transistors Semiconductor device modeling Voltage Temperature distribution Hardware design languages Neurons

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