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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Defect-oriented testing of analogue and mixed signal ICs

Defect-oriented testing of analogue and mixed signal ICs

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IEEE International conference on Electronics, Circuits and Systems (ICECS)

作者： M.B. Santos F.M. Goncalves M. Ohletz J.P. Teixeira IST INESC Lisboa Portugal Alcatel Microelectronics Brussels Belgium

The high costs of testing analogue and mixed-signal Integrated Circuits (ICs) are driving a large research effort on test preparation in the IC design environment. In this paper, we highlight the usefulness of using a Defect-Oriented (DO) approach for test preparation, in order to generate and validate low-cost, high-quality tests. DO fault modeling is carried out using an Inductive Fault Analysis (IFA) strategy. Analogue fault simulation feasibility is analyzed. Analog Test Stimuli (ATS) generation for mixed-signal ICs is performed using digital BIST test hardware, available on-chip. A DO test environment and tools are presented. simulation results are described, showing also how layout-driven design-For-Testability (DFT) can enhance product quality and reliability, while cutting test costs.

关键词： Circuit testing Circuit faults Costs Integrated circuit testing Mixed analog digital integrated circuits Analog integrated circuits Analytical models Performance evaluation Built-in self-test Hardware

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Physical model for GaN HEMT design optimization in high frequency switching applications

Physical model for GaN HEMT design optimization in high freq...

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European conference on Solid-State Device Research (ESSDERC)

作者： D. Cucak M. Vasic O. Garcia Y. Bouvier J. Oliver P. Alou J. A. Cobos A. Wang S. Martin-Horcajo F. Romero F. Calle Center for Industrial Electronics (CEI) Universidad Politecnica de Madrid (UPM) Madrid Spain Institute for Optoelectronics Systems and Microelectronics (ISOM) Universidad Politecnica de Madrid (UPM) Madrid Spain

In this paper, physical modeling of a GaN HEMT is proposed, with the objective of device design optimization for application in a high frequency DC/DC converter. From the point of view of a switching application, physical model for input, output and reverse capacitance as well as for channel resistance is very important, since the aforementioned parameters determine power losses in the circuit. The obtained physical model of the switching device can be used for simulation models such as PSpice or hybrid behavioral power loss models for high frequency DC/DC converters. In this work, extrinsic model for I d (V ds , V gs ) output characteristics of a depletion mode GaN HEMT with a field plate structure was obtained, as well as physical model for input, output and reverse capacitance in the subthreshold regime. The model was implemented in Simplorer simulation model and verified by the measured efficiency curves of the buck converter prototype, using the GaN HEMT that was analyzed. With the increase of the switching frequency, precision of the model increases, especially in the low power area, which is the area of interest in our application.

关键词： HEMTs Gallium nitride Capacitance MODFETs Logic gates Aluminum gallium nitride Integrated circuit modeling

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A modified CMOS nano-power resistorless current reference circuit

A modified CMOS nano-power resistorless current reference ci...

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Shailesh Singh Chouhan Kari Halonen SMARAD-II Department of Micro and Nano Sciences Aalto University School Of Electrical Engineering Finland

In this work, all MOS current reference circuit is proposed using a standard 0.18 μm technology and the simulations were performed using the Cadence Spectre simulator. The proposed current reference circuit is based on, the resistorless current reference circuit suggested by Oguey and Aebishcher. The Oguey's circuit is capable of generating the reference current in a nanoampere range, but with the high temperature coefficient (TC). The reason for high TC, that we found, is the lack of control over the gate-source voltage of an active resistor used in the design. This gate-source voltage is one of the controlling parameters responsible to obtain adequate thermal compensation for the reference current. In the proposed work, we modified the architecture to limit the variation of the gate-source voltage with the temperature and hence controls the thermal behaviour of the reference current. The working supply voltage of the proposed circuit ranges from 1.25 V to 2 V. The temperature coefficients of the reference current generated from the proposed and conventional architectures are 39.8 ppm/°C and 545.12 ppm/°C respectively at a supply voltage of 1.25V for the temperature ranging from -60°C to 85°C. The maximum power consumption of proposed and conventional architecture is 624.8nW and 468.59nW at a supply voltage of 2 V with the layout area of 0.0013μm 2 and 0.001μm 2 respectively.

关键词： Threshold voltage Logic gates Temperature distribution Resistors CMOS integrated circuits Integrated circuit modeling simulation

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A low bandwidth pulse-based neural recording system

A low bandwidth pulse-based neural recording system

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Sheng-Feng Yen John G. Harris Department of Electrical and Computer Engineering University of Florida Gainesville FL USA

This research investigates a novel data reduction scheme using adaptive leaky refractory integrate-and-fire (ALRIF) neurons to generate pulses for an implanted neural recording system in wireless transmission applications. The wireless implanted multi-channel recording system imposes many constraints on the system but the major constraint is on low bandwidth. Other constraints including low bandwidth transmission, large dynamic range, low power consumption, small device size and noise robustness, though serious, can be more easily met. This proposed scheme promises to dramatically reduce the required communication bandwidth via three versatile neuron circuit strategies: adaptive, leaky and refractory neurons. This system consists of both front-end hardware and a back-end signal processing. Analog VLSI circuitry (AMI 0.6μm CMOS) was chosen to implement the front-end hardware to transform the signal to a pulse representation with ultra-low bandwidth. On the back-end, the system can either reconstruct the original signal and run traditional spike sorting or run spike sorting directly in the pulse domain. The ALRIF neuron circuit can reduce the bandwidth efficiently to support the pulse-based spike sorting. MATLAB simulation results for the neuron models are proof of concept. Circuit design for each building block has been presented and simulated in Cadence. Bench-top hardware system testing shows feasibility of in vivo neural recording applications.

关键词： Neurons Bandwidth Wireless communication Threshold voltage Sorting Integrated circuit modeling Hardware

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Analyse of Protection Devices' Speed Performance against ESD under CDM Using TCAD

Analyse of Protection Devices' Speed Performance against ESD...

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IEEE conference on Electron Devices and Solid-State Circuits

作者： Qiang Cui Yan Han Juin J. Liou Shurong Dong Institute of Microelectronics and Photoelectronics University of Zhejiang Hangzhou China Department of Electrical and Computer Engineering University of Central Florida Orlando FL USA

ISBN: (纸本)9781424406364

Speed performance plays a critical role in protection devices against ESD (Electro-Static Discharge) overstress under CDM (Charged Device Model). It is too demanding to obtain speed performance of protection devices under CDM accurately by testing. Therefore we have to resort to TCAD (Technology Computer Aided design) method to evaluate speed performance under CDM. This TCAD methodology is based on mix-mode transient circuit simulation, which depicts ESD events better. Two time constants, T trigger and T recover , and two key coefficients, F trigger and C recover , are provided to characterize and evaluate speed performance of ESD protection devices. The results show that this TCAD methodology has a good ability of convergence and is a good tool to evaluate speed performance of ESD protection devices quantificationally. Anlayse results show that speed performance of SCR is superior over ggNMOS in not only triggering but also bypassing ESD currents to recover the voltage towards a safe level.

关键词： Performance analysis Protection Electrostatic discharge Circuit simulation Thyristors Biological system modeling Integrated circuit modeling Impact ionization Voltage Anodes

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Development and application of a macro model for flash EEPROM design

Development and application of a macro model for flash EEPRO...

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Annual IEEE International ASIC/SOC conference

作者： M. O'Shea A. Concannon K. McCarthy B. Lane A. Mathewson M. Slotboom National Microelectronics Research Centre Cork Ireland Philips Research Laboratories Eindhoven Netherlands

The inclusion of embedded flash memory in systems-on-chip designs enables the addition of many new features. However to enable designers to embed flash memory in an efficient and competent manner, they must have the capability to simulate full circuit operation. Therefore a flexible flash EEPROM model is required. An accurate and numerically efficient model for the transient and DC characteristics of Fowler Nordheim (FN) based Flash EEPROM cells has been developed. The model has been extensively validated, using read, program and erase operations. The model has also been applied to several applications, in a typical structure. These display the ability of the model to accelerate the design cycle for applications which require flash memory.

关键词： EPROM Nonvolatile memory Flash memory Electrons Semiconductor device modeling Circuit simulation Acceleration CMOS process Costs Threshold voltage

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A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits 03

A CAD framework for co-design and analysis of CMOS-SET hybri...

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IEEE International conference on Computer-Aided design

作者： S. Mahapatra K. Banerjee F. Pegeon A.M. Ionescu Electronics Laboratory (LEG) Institute of Microelectronics and Microsystems (IMM) Swiss Federal Institute of Technology Lausanne Switzerland Electronics Laboratory (LEG) Swiss Federal Institute of Technology Lausanne (EPFL) Lausanne Switzerland Department of Electrical & Computer Engineering University of California Santa Barbara CA USA Silvaco Data Systems Inc. Grenoble France Silvaco Data Systems Grenoble France

ISBN: (纸本)9781581137620

This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. Particularly, the extension of the recent MIB model for single/multi gate symmetric/asymmetric device for a wide range of drain to source voltage and temperature is addressed. Circuit level co-simulations are successfully performed by implementing the SET analytical model in Analog Hardware Description Language (AHDL) of a professional circuit simulator SMARTSPICE. Validation at device and circuit level is carried out by Monte-Carlo simulations. Some novel functionality hybrid CMOS-SET circuit characteristics: (i) SET neuron, (ii) Multiple valued logic circuit and (iii) a new Negative Differential Resistance (NDR) circuit, are also predicted by the proposed SET model and analyzed using the new hybrid simulator.

关键词： Hybrid integrated circuits Analytical models Circuit simulation Predictive models Single electron transistors Semiconductor device modeling Voltage Temperature distribution Hardware design languages Neurons

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Signal integrity study of high density through silicon via (TSV) technology

Signal integrity study of high density through silicon via (...

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Electronics Packaging Technology conference (EPTC)

作者： Bok Eng Cheah Jackson Kong Chee Kit Chew Kooi Chi Ooi Shanggar Periaman Intel Microelectronics (M) Sdn Bhd Halaman Kampung Jawa Penang Malaysia

This paper explores the electrical performance of several multi-channel TSV designs i.e. cross-etched full-plated TSV and cross-etched partial-plated TSV to further improve data transmission bandwidth among the vertically stacked silicon devices. The electrical characteristics of the multi-channel TSV designs were investigated and compared against the conventional TSV design in terms of return loss, insertion loss, near-end (NEXT) and far-end (FEXT) crosstalk. Fullwave electromagnetic simulation data showed the insertion loss performance of the multi-channel TSV designs are at par with the conventional TSV design up-to 50GHz. Meanwhile, the multi-channel TSV designs were found yielding improved NEXT and FEXT crosstalk performance. Transient analyses of respective TSV designs are also included in this paper for more conclusive discussions.

关键词： Through-silicon vias Insertion loss Capacitance Three-dimensional displays Silicon Solid modeling

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Multi-scale energy-based failure modeling of bond pad structures

Multi-scale energy-based failure modeling of bond pad struct...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： O. van der Sluis R.B.R. van Silfhout R.A.B. Engelen W.D. van Driel G.Q. Zhang Department of Precision and Microsystem Engineering Delft University of Technology the Netherlands Philips Applied Technologies Eindhoven The Netherlands Department of Precision and Microsystem Engineering Delft University of Technnology Netherlands NXP Semiconductors Nijmegen The Netherlands NXP Semiconductors Nijmegen AE The Netherlands

Thermo-mechanical reliability issues have been identified as major bottlenecks in the development of future microelectronic components. This is caused by the following technology and business trends: (1) increasing miniaturisation, (2) introduction of new materials, (3) shorter time-to-market, (4) increasing design complexity and decreasing design margins, (5) shortened development and qualification times, (5) gap between technology and fundamental knowledge development. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [8]. However, bad mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back end structure when no appropriate development is performed. The scope of this paper is on the development of numerical models that are able to predict the failure sensitivity of complex three-dimensional multi-layered structures while taking into account the details at the local scale of the microelectronic components by means of a multi-scale method. The damage sensitivity is calculated by means of an enhanced version of the previously introduced area release energy (ARE) criterion. This enhancement results in an efficient and accurate prediction of the energy release rate (ERR) at a selected bimaterial interface in any location. Moreover, due to the two-scale approach local details of the structure are readily taken into account. In order to evaluate the efficiency and accuracy of the proposed method, several two-dimensional and three-dimensional benchmarks will be simulated. The paper focusses on the enhanced ARE method, including several two- and three-dimensional benchmarks.

关键词： Bonding Thermomechanical processes microelectronics CMOS technology Dielectric materials Time to market Qualifications Adhesives Integrated circuit packaging Wire

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Modernization of Low-Temperature JFET Models Built into LTspice CAD Systems, Taking into Account the Results of their Experimental Study

Modernization of Low-Temperature JFET Models Built into LTsp...

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Latin American Electron Devices conference (LAEDC)

作者： Oleg V. Dvornikov Valentine L. Dziatlau Vladimir A. Tchekhovski Nikolay N. Prokopenko Alexey A. Zhuk Anna V. Bugakova Plc. “Minsk Research Instrument-Making Institute” (MNIPI) Kolas's str. 73 Minsk Belarus Institute for Nuclear Problems of Belarussian State University Bobruiskaya str. 11 Minsk Belarus Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Sovetskaya st. 3 Zelenograd Russia Don State Technical University Gagarin's sq. 1 Rostov-on-Don Don State Technical University Rostov-on-Don (RR) Russia

ISBN: (数字)9781728110448

ISBN: (纸本)9781728110455

The results of experimental studies of the current-voltage characteristics (CVC) of silicon n-JFET and p-JFET manufactured at JSC INTEGRAL (Minsk, Belarus) at temperatures from minus 195°C up to 30°C are considered. A hardware-software complex and a JFET automated measurement technique are created. Refined approximations of the temperature dependences of the Spice parameters of JFETs are given, which provide a good agreement between the results of measurements and simulation of the CVC. The created models are intended primarily for computer simulation of low-temperature effects in analog ICs in the LTspice CAD.

关键词： Temperature measurement JFETs Solid modeling Semiconductor device measurement Logic gates Integrated circuit modeling Temperature

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