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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1413 条记录，以下是121-130 订阅

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Characterization and modeling of Cure-Induced Thermo Mechanical Properties and Chemical Shrinkage of Epoxy Resins

Characterization and Modeling of Cure-Induced Thermo Mechani...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Venu Prakash Kasinikota Wolfgang Muehleisen Markus Grinschgl Alexander Steiner Siegfried Hasil Margit Christa Lang Polymer Competence Center Leoben GmbH (PCCL) Leoben Austria Institute of Mechanics Montanuniversität Leoben Leoben Austria Silicon Austria Labs GmbH (SAL) Villach Austria GIPRO GmbH Peggau Austria

Epoxy resins are widely used in molding electrical insulators and electronic components due to their superior dielectric properties and mechanical strength. However, due to poor process control along with the complex geometry of their components, parts can entail air pockets, cracks, or deformations driven by residual stresses. To address these challenges, this research uses the Computational Fluid Dynamics (CFD) software Autodesk Moldflow Synergy 2023 to visualize epoxy resin flow behavior and predict the curing behavior as it flows through the mold using respective models. When simulating the mold-filling behavior, comprehensive thermo-mechanical data are required for both uncured and cured states of cycloaliphatic epoxy resins. Therefore, it was crucial to thoroughly characterize the material to obtain precise material parameters for using them in simulations, as these parameters play a vital role in the accuracy of the simulations. Python-based formulations of the Prout-Tompkins cure kinetic and Cross-Castro-Macosko viscosity models are used to comprehensively analyze the flow front and curing behavior during an Automatic Pressure Gelation (APG) process. This research provides valuable insights into the behavior of epoxy resin when molded in complex scenarios. It enables the design of optimized molds while allowing for fast and efficient evaluation and optimization of process parameters, ultimately reducing high rejection rates as safety critical parts, like insulators, need to be flawless.

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Electromigration simulation of Copper-Pillar Bump in 3D Integration

Electromigration Simulation of Copper-Pillar Bump in 3D Inte...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Zhoubang Du Leiming Du GuoQi Zhang EEMCS Faculty Delft University of Technology Delft the Netherlands

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

The continuous trend toward miniaturization and increased integration density in semiconductor devices has exacerbated electromigration (EM) issue, making it a significant reliability concern in advanced packaging technologies, especially in copper (Cu)-pillar bumps used in 3D integration. This study investigates the EM phenomenon in a Cu-pillar bump structure using the birth/death element method in ANSYS. The model incorporates electro-thermal-structural-diffusion coupling transient simulations to analyze the time-dependent evolution of atomic concentration and resistance under varying experimental durations, model sizes, temperatures and current. The simulation results indicate that increased current and temperature significantly accelerate the formation of voids, leading to earlier EM failure. A comparative study between forward and inverse current reveals differences in the evolution of EM-induced damage, where inverse currents exhibiting lower resistance growth over time. These findings provide valuable insights into the design of Cu-pillar bump structures to enhance EM resistance in advanced packaging technologies.

关键词： Resistance Electromigration Solid modeling Analytical models simulation Packaging Predictive models Finite element analysis Current density Three-dimensional integrated circuits

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LSTM-based ECG Signal Classification with Multi-level One-hot Encoding for Wearable Applications

LSTM-based ECG Signal Classification with Multi-level One-ho...

引用

IEEE Biomedical Circuits and Systems (BIOCAS)

作者： Jinhai Hu Wang Ling Goh Yuan Gao School of Electrical and Electronic Engineering Nanyang Technological University (NTU) Republic of Singapore Agency for Science Technology and Research (A*STAR) Institute of Microelectronics (IME) Republic of Singapore

ISBN: (数字)9798350354959

ISBN: (纸本)9798350354966

This paper presents an electrocardiogram (ECG) signal classification method using one-hot coding scheme and Long Short-Term Memory (LSTM) neural network. Instead of the conventional analog to digital converter (ADC) with two’s complement binary output, one-hot encoding scheme is adopted in this design to convert the analog signal to 1D vector and then further processed by a LSTM network for classification. Our study shows that one-hot encoding can effectively represent the features of ECG signal with low data bit-width and sampling rate. The proposed method not only simplifies the ADC design, but also improves the classification accuracy. simulation results show that the proposed design only requires 5-bit bit-width with 50 Hz sampling rate to achieve 96.9% validation accuracy on 5-class classification task using MIT-BIH ECG dataset.

关键词： Semiconductor device modeling Accuracy simulation Pattern classification Electrocardiography Encoding Vectors Hardware Long short term memory Analog-digital conversion

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Microvia Homogenised Behaviour for the Mechanical Modelling of PCB with Embedded Components

Microvia Homogenised Behaviour for the Mechanical Modelling ...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Flora Dailland Gautier Girard Mounira Bouarroudj Marion Martiny Sébastien Mercier LEM3 CNRS Arts et Métiers Université de Lorraine Metz France SATIE Université Paris Est Créteil Université Paris-Saclay CNRS Gif-sur-Yvette France

ISBN: (数字)9798350393002

ISBN: (纸本)9798350393019

Driven by the development of e-mobility, printed circuit boards with active embedded components are seen as potential design to increase interconnect density. One way to increase the lifetime of printed circuits boards is to investigate the response of the interconnect layers of embedded components, areas that can be subject to various types of failure. Chip interconnection by numerous microvias is a highly developed industrial technique. Nowadays numerical studies are realised on the reliability of microvias on embedded components. The numerical modelling problem arises from the very large number of microvias connecting the chip surface to the rest of the printed circuit board. To overcome this problem, a homogenisation method is proposed. Once defined, the equivalent homogeneous material may replace the real microvia in a larger design. It is seen in this work that models with homogenised and real microvias provide consistent predictions for averages. Nevertheless, local stresses and strains are not accessible in homogeneous models. Thus it is necessary to combine fully discretised patterns and homogenised ones. This will enable the detection of crack initiation zones in microvia interconnect layers in the context of embedded component printed circuit board technology.

关键词： Accuracy Printed circuits Integrated circuit interconnections Predictive models Numerical models Finite element analysis Integrated circuit modeling Stress Load modeling Strain

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modeling and Assessment of Atomic Precision Advanced Manufacturing (APAM) Enabled Vertical Tunneling Field Effect Transistor 26

Modeling and Assessment of Atomic Precision Advanced Manufac...

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International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Gao, Xujiao Mendez, Juan P. Lu, Tzu-Ming Anderson, Evan M. Campbell, DeAnna M. Ivie, Jeffrey A. Schmucker, Scott W. Grine, Albert Lu, Ping Tracy, Lisa A. Arghavani, Reza Misra, Shashank Sandia Natl Labs 1515 Eubank SE Albuquerque NM 87123 USA

ISBN: (纸本)9781665406857

The atomic precision advanced manufacturing (APAM) enabled vertical tunneling field effect transistor (TFET) presents a new opportunity in microelectronics thanks to the use of ultra-high doping and atomically abrupt doping profiles. We present modeling and assessment of the APAM TFET using TCAD Charon simulation. First, we show, through a combination of simulation and experiment, that we can achieve good control of the gated channel on top of a phosphorus layer made using APAM, an essential part of the APAM TFET. Then, we present simulation results of a preliminary APAM TFET that predict transistor-like current-voltage response despite low device performance caused by using large geometry dimensions. Future device simulations will be needed to optimize geometry and doping to guide device design for achieving superior device performance.

关键词： atomic precision advanced manufacturing (APAM) tunneling field effect transistor (TFET) band-to-band tunneling TCAD Charon

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D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in Large-Scale M3D 2TOC DRAM Bit Cell Evaluation via Statistical modeling Methodology

D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in L...

引用

International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yue Zhao Yong Yu Jingrui Guo Lingfei Wang Nan Yang Jianpeng Jiang Yanan Lu Menglong Zhou Shijie Huang Lihua Xu Zhenhua Wu Guanhua Yang Di Geng Guilei Wang Bryan Kang Chao Zhao Ling Li Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China Beijing Superstring Academy of Memory Technology Beijing China

ISBN: (数字)9798331516352

ISBN: (纸本)9798331516369

Device nonuniformity of ultra-scaled novel vertical a-IGZO-FETs is induced by multi-sources, such as dimension variation and material disorder, limiting large-scale DRAM design. Particularly, fluctuation of disorders in an amorphous channel exhibits a great impact on density of states (DOS) contributing to statistical effects on gate controllability and transport mechanisms. To clarify this issue, TCAD simulations are conducted by adjusting geometric dimensions and DOS, and corresponding statistical characteristics (e.g., on-voltage and on-current etc.) are extracted from up to 80 samples of down to channel length of 50nm. Such effects are further incorporated into a surface-potential based physics compact model via calibration to experiments. Using this model, the vertical a-IGZO-FET-based 2TOC DRAM is firstly investigated with the statistical analysis of Write/Read performances, supporting device variation aware DTCO flow of future extremely large-scale and high-density M3D memory.

关键词： Semiconductor device modeling Performance evaluation Solid modeling Analytical models Statistical analysis Random access memory Feature extraction Semiconductor process modeling Device-to-device communication Three-dimensional integrated circuits

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Studying Asymmetric Warpage Behavior of Panel-Level Packages Using Process modeling Techniques and Viscoelasticity Theory

Studying Asymmetric Warpage Behavior of Panel-Level Packages...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Z. Shu K. N. Chiang Advanced Microsystem Packaging and Nano-Mechanics Research Lab Dept. of Power Mechanical Engineering National Tsing Hua University Hsinchu Taiwan R.O.C

Panel Level Packaging (PLP) is an integrated circuit (IC) packaging technology that is mainly used in fields such as mobile communications, consumer electronics, and industrial automation. Compared to wafer-level packaging, the advantages of panel-level packaging include improving manufacturing efficiency, reducing costs, and improving product quality. However, because the overall area of panel-level packaging is larger, there may be some problems in the manufacturing process, such as insufficient flatness of the substrate surface, poor adhesion between the substrate and the components, and incorrect component positioning. These problems may lead to poor product quality, asymmetric warpage, and even packaging *** paper aims to discuss the factors that may cause warpage in the panel-level packaging (PLP) process, including material non-uniformity, thermal stress, and mechanical stress. To address these issues, design and optimization of the packaging, selection of appropriate materials and process parameters, and stress analysis and simulation of the packaging are required. Through simulation, the warpage variation and stress distribution during the manufacturing process can be analyzed more efficiently. Our research will investigate the effects of different process parameters, such as the temperature of the molding process and the heating/cooling rate, as well as the thickness, size, and distribution of the encapsulant chips and other layers on warpage.

关键词： Heating systems Manufacturing processes Packaging Predictive models Product design Quality assessment Behavioral sciences

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simulation of moisture-induced plasticization in transfer-molded optical sensor packages using a time - temperature - moisture concentration superposition 71

Simulation of moisture-induced plasticization in transfer-mo...

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IEEE 71st Electronic Components and Technology conference (ECTC)

作者： Huber, Fabian Etschmaier, Harald Hadley, Peter Ams AG AOS Packaging Design Premstaetten Austria Graz Univ Technol Inst Solid State Phys Graz Austria

ISBN: (纸本)9780738145235

Moisture sorption of microelectronics packages may lead to plasticization of materials such as epoxide-based transfer-molding compounds. This does not only result in a reduction of the modulus but also to a change in the frequency response of the materials. In this work, moisture-induced plasticization effects of unfilled transparent molding compounds are modeled using finite-element reliability simulations of an optical sensor package. Storage modulus data from humidity-controlled dynamic mechanical analysis is used to extend the temperature-dependent linear viscoelastic constitutive model, usually applied using a Prony series and time - temperature superposition, to apply a previously presented time - temperature - moisture concentration superposition of viscoelastic relaxation time-constants. Eventually, stress fields at the die-to-mold compound interface resulting from thermal and hygroscopic strains are compared, applying different complexity of the constitutive model of the compound.

关键词： microelectronics packaging modeling of moisture plasticization time - temperature - moisture concentration superposition

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A RISC-V-based system on chip for high-speed control in safety-critical 650 V GaN-applications 16

A RISC-V-based system on chip for high-speed control in safe...

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2021 International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design, SMACD 2021 and 16th conference on PhD Research in microelectronics and Electronics, PRIME 2021

作者： Richter, Mike Lüdecke, André Lee, Yoon-Cue Stanitzki, Alexander Utz, Alexander Grau, Günter Kappert, Holger Kokozinski, Rainer Finkenstr. 61 Duisburg47057 Germany advICo Microelectronics GmbH Münsterstr. 13-15 Recklinghausen45657 Germany Department of Electronic Components and Circuits University of Duisburg-Essen Bismarckstr. 81 Duisburg47057 Germany

ISBN: (纸本)9783800755899

In power electronics applications, Gallium Nitride (GaN)-based transistors generally offer benefits in efficiency and switching speed, but come at the cost of harder controllability and thus more complex control circuits. As a contribution towards easier and safer control for GaN-devices, we present a new system-on-chip (SoC) specifically dedicated to the control of GaN-based power modules. The main processing unit is compliant with the RISC-V specification and implements the RV32IMC instruction set. Major parts of a control algorithm may be performed by peripheral modules that reduce workload on the processor and enable low-latency reactions towards safety-critical events in the GaN-circuit. The output is generated by a PWM-unit that supports sub-nanosecond resolution. The processor achieves a benchmark score of 2.03 CoreMark per MHz. The SoC reacts to threshold violations on measurement inputs within 25 ns. Future steps will involve expanding the SoC with more safety features and the coupling of several SoCs for multiphase synchronization. © VDE VERLAG GMBH.

关键词： System-on-chip

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Physics-Informed Compact Model for SF6/O2 Plasma Etching

Physics-Informed Compact Model for SF6/O2 Plasma Etching

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International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Lado Filipovic Josip Bobinac Julius Piso Tobias Reiter CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors Institute for Microelectronics TU Wien Vienna Austria

We propose a process simulation/emulation flow which incorporates the generation and application of compact models for fast geometry generation, suitable for design-technology co-optimization (DTCO). The methodology is applied to develop a compact model for etching in a SF 6 /O 2 plasma using 35 data points from experimental measurements and results from a calibrated physical model. The compact model is tested against physical simulations using 80 random points in the input parameter domain consisting of varying the oxygen content and pressure in the plasma chamber. The model is shown to produce highly accurate geometries with an average error for the depth and width at half depth (WAHD) of 2.0% and 1.0%, respectively. The simulation speedup is more than three orders of magnitude, when compared to the physical model; it should also be noted that the parallelized physical model was executed on 40 cores, while the compact model was run on a single core.

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