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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1418 条记录，以下是121-130 订阅

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Variation- and Degradation-Aware Stochastic Behavioral modeling of Analog Circuit Components 14

Variation- and Degradation-Aware Stochastic Behavioral Model...

引用

13th conference on Ph.D. Research in microelectronics and Electronics (PRIME) / 14th International conference on Synthesis, modeling, Analysis and simulation Methods and Application to Circuit design (SMACD)

作者： Taddiken, Maike Hillebrand, Theodor Paul, Steffen Peters-Drolshagen, Dagmar Univ Bremen Inst Electrodynam & Microelect ITEM Me Bremen Germany

ISBN: (纸本)9781509050529

Process variation and aging effects influence the performances of integrated circuits in modern technology nodes. In this paper, a method is proposed to build a behavioral model to represent the influences of process variation, aging and operational parameters on circuit performances. The variability of performance is represented using distribution functions while Response Surface Models (RSM) are used to describe the dependence of the distribution's moments on operational parameters. Compared to other approaches, less parameters have to be included in the RSM therefore reducing the complexity. This enables a fast Monte-Carlo analysis with aging analysis on a behavioral level. The method is evaluated for a voltage reference circuit and an operational amplifier showing a good representation of the variability and reaching a very good speedup of simulation time.

关键词： Integrated circuit modeling Aging Computational modeling Analytical models Standards Monte Carlo methods Transistors

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A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit simulation on GPUs 15

A Combinatorial Multigrid Preconditioned Iterative Method fo...

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15th International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD) / 14th conference on PhD Research in microelectronics and Electronics (PRIME)

作者： Garyfallou, Dimitrios Evmorfopoulos, Nestor Stamoulis, Georgios Univ Thessaly Dept Elect & Comp Engn Volos Greece

ISBN: (纸本)9781538651537

Efficient large scale circuit simulation is among the most challenging problems facing the EDA industry today, since it is the only feasible way to verify a circuit's behaviour prior to manufacturing. In recent years, the emphasis has been placed on preconditioning methods which reduce the number of iterations for solving large Symmetric Diagonally Dominant systems resulting after the Modified Nodal Analysis. This paper presents a GPU-accelerated Preconditioned Conjugate Gradient (PCG) iterative method preconditioned by the Combinatorial Multigrid (CMG) for fast DC and transient analysis of large-scale linear circuits. Experimental results on IBM industrial power grids demonstrate speedups up to 4.69x and 4.50x for the PCG method and the CMG preconditioning algorithm, respectively, over the optimized CPU implementations.

关键词： Iterative methods Integrated circuit modeling RLC circuits Linear systems Graphics processing units Circuit simulation Convergence"

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modeling of Low-dropout Regulator to Optimize Power Supply Rejection in System-on-Chip Applications 16

Modeling of Low-dropout Regulator to Optimize Power Supply R...

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16th International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD) / 15th conference on PhD Research in microelectronics and Electronics (PRIME)

作者： Tan, Jun Sommer, Ralf IMMS Inst Mikroelekt & Mechatron Syst Gemeinnutzi Ilmenau Germany

ISBN: (纸本)9781728112015

This paper presents a methodology to model and optimize the power supply rejection (PSR) for a low-dropout regulator (LDO) in system-on-chip (SoC) applications. Since SoC designs integrate multiple functions on a single chip, the Power Management Unit (PMU) becomes crucial to meet the requirements for multiple sub-blocks. The supply ripple, which has a significant impact on sensitive analog/RF sub-blocks, needs to be reduced by achieving optimized PSR performance in LDO designs. This paper begins by modeling the conventional LDO topology. The transfer function of the model is calculated, so that the system behaviour can be remapped to the parameters of the sub-blocks. Additionally, the verification is done by comparing the model and a transistor level design. Finally, the methodologies are discussed in two cases, namely a PSR of -50 dB@100 kHz and a full-spectrum PSR of -50 dB. The results show that different design strategies generate practical design trade-offs, although all strategies can theoretically achieve the cases. With the proposed methodologies, the design parameters can be clearly and efficiently optimized to achieve optimum PSR performance.

关键词： System-on-chip

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Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation 15

Tunable Floating-Point for Embedded Machine Learning Algorit...

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作者： Franceschi, Marta Nannarelli, Alberto Valle, Maurizio Univ Genoa DITEN Cosm Lab Genoa Italy Tech Univ Denmark DTU Compute Lyngby Denmark

ISBN: (纸本)9781538651537

The development of embedded and real-time systems for Machine Learning data processing is challenging (e.g. IoT). Low latency, low power consumption and reduced hardware complexity should be the characteristics of such systems. Considering prosthetic applications, which are error-tolerant, a technique that tunes the precision of operands and operations has been chosen for a Machine Learning algorithm used for tactile data processing. This paper presents the implementation of a Tunable Floating-Point (TFP) representation into a Singular-Value Decomposition (SVD) algorithm based on the One-Sided Jacobi method. The TFP representations demonstrate high performance and efficiency improvements of the SVD algorithm.

关键词： simulation power efficiency SVD algorithm

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Comparing Code Coverage Metrics for Analog Behavioral Models 14

Comparing Code Coverage Metrics for Analog Behavioral Models

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作者： Fuertig, Andreas Paschke, Moritz Hedrich, Lars Goethe Univ Frankfurt aM Inst Comp Sci Frankfurt Germany

ISBN: (纸本)9781509050529

In current applications Analog/Mixed-Signal (AMS) circuits gets increasingly demanding. To speed up the design process parts of the design were implemented in hardware description languages. Besides positive aspects like simulation processing times these models need to be checked in terms of verification run set completeness, i.e. input stimuli, parameter setting, and test bench circuitry. For this purposes we present a methodology to adopt code coverage metrics on Verilog-A models. A public domain analog circuit simulator automatically instruments and executes the behavioral description. The coverage results are automatically annotated and compared to a coverage metric based on the reachable analog state-space of the circuit. We discuss the methodology on several examples and sketch a path to improve the completeness of a verification run set.

关键词： Measurement Hardware design languages Computational modeling Analog circuits Mathematical model Instruments Software

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Analysis, Optimization, and modeling of Analog Multi-Tone Serial Data Transceivers 13

Analysis, Optimization, and Modeling of Analog Multi-Tone Se...

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作者： Kim, Gain Gharibdoust, Kiarash Leblebici, Yusuf Ecole Polytech Fed Lausanne Dept Elect Engn Lausanne Switzerland Kandou Bus SA Lausanne Switzerland

ISBN: (纸本)9781509065080

This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, which is not straightforward to model and hard to optimize with conventional serial link modeling tools. A method to limit the computing system's memory usage when simulating a data transmission of a long bit-stream, e.g., greater than 10 Mbits, is also described. The reliability of the modeling framework is proven by some comparisons with a highly-trusted commercial tool for a conventional TRX architecture.

关键词： Mixers Integrated circuit modeling Computational modeling Time-domain analysis Jitter Modulation Tools

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Micro coil modeling - benefit and implementation of a permeable layer

Micro coil modeling - benefit and implementation of a permea...

引用

conference on design, modeling, and simulation in microelectronics

作者： Rehfuss, S Marschner, C Peters, D Bolte, H Laur, R Univ Bremen Inst Electromagnet Theory & Microelect D-28334 Bremen Germany

ISBN: (纸本)0819439002

Rectangular micro coils which are used in a wide range of applications (e.g. medical or automotive area) are the main components of appropriate wireless transmission systems for frequencies up to 20 MHz. As shown in previous works the self-inductance of micro coils has to be maximized to achieve a higher working distance. This can be done by the usage of a permeable layer underneath the micro coil. The existing model of the micro coil is extended by the use of the magnetic image method to include the inductance yield caused by the permeable layer. The underlying permeable layer or substrate is also modeled accurately to include eddy current phenomena and parasitic elements. To do this, the layer and the substrate respectively are divided into segments analog to the structure of the micro coil. Each segment is described by lumped elements, All elements are connected together to build up a network, which will be used to calculate the terminal impedance. The model and first results will be presented. (C) 2002 Elsevier Science Ltd. All rights reserved.

关键词： micro coil modeling telemetry permeable layer simulation

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Thermal aging modeling of Molding Compound under High-Temperature Storage and Temperature Cycling Conditions 19

Thermal aging modeling of Molding Compound under High-Temper...

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19th International conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in microelectronics and Microsystems (EuroSimE)

作者： Zhang, Bingbing Johlitz, Michael Lion, Alexander Ernst, L. J. Jansen, K. M. B. Vu, Duc-Khoi Weiss, Laurens Univ Bundeswehr Munchen Inst Mech Neubiberg Germany Ernst Consultant Schoonhoven Netherlands Guilin Univ Elect Technol Guilin Peoples R China Delft Univ Technol Dept Design Engn Delft Netherlands Infineon Technol AG Munich Germany

ISBN: (纸本)9781538623596

In microelectronic packages, generally the chip is encapsulated by a molding compound (MC). The MC provides a mechanical support for the chip and isolates it from the environment and as a result protects the encapsulated chip. It is well known that MC's are polymer-based materials. When packages are exposed to a harsh environment such as to high-temperature storage or to thermal cycling, the mechanical properties of the MC's can change significantly. Consequently this could result into reliability issues of these packages. For a long time, there was no simple and efficient model method available to simulate the mechanical behavior of these packages under thermal aging conditions. As a result, it was hard to forecast the package reliability after a period of thermal aging. Since in our previous work [1,2] the thermomechanical properties of MC's before and after thermal aging were systematically characterized, the above problem was merely solved. A simple and efficient modeling method was proposed to simulate the thermal aging effects on MC's [2]. In this paper, a bi-material sample consisting of a MC layer on a Copper substrate is prepared and used to verify the proposed modeling method at two different thermal conditions: High-temperature storage (HTS) and Temperature cycling (TC). Based on the proposed modeling method the mechanical behavior of the bi-material sample after aging under these (different) thermal conditions are established throug FEM simulation. The simulation results match the experiment results quite well.

关键词： Aging High-temperature superconductors Temperature measurement microelectronics Ovens Electronic packaging thermal management Compounds

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On Closing the Gap Between Pre-simulation and Post-simulation Results in Nanometer Analog Layouts 15

On Closing the Gap Between Pre-simulation and Post-simulatio...

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作者： Pan, Po-Cheng Huang, Hung-Wen Huang, Chien-Chia Patyal, Abhishek Chen, Hung-Ming Yang, Tsun-Yu Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan Taiwan Semicond Mfg Co Ltd Hsinchu Taiwan

ISBN: (纸本)9781538651537

In order to generate analog layout in advanced technology, it still remains lots of challenges due to the imprecise estimation of critical performance parameters. We propose an upgraded decision making framework, PEDefer, to decompose existing layout into decisive components for performance estimation. In this work, the objective is to synthesize layout solutions based on the performance estimation of user-defined constraints and existing templates. The constraints of the circuit are priorly tackled in the partition and layout enumeration stage. In addition, we attempt to have partial layout pieces as exchangeable blocks to perform pseudo-post-simulation, thus to put simulation factors in the evaluation during layout enumeration strategy. The experiments show that this flow guarantees valid analog layout results whose performances are closer to netlist-level simulation than manual designed or migrated layouts with minimal overhead.

关键词： Layout Estimation Shape Decision making Routing Performance evaluation"

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design considerations of an SRAM array for the statistical validation of time-dependent variability models 15

Design considerations of an SRAM array for the statistical v...

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作者： Saraza-Canflanca, P. Malagon, D. Passos, F. Toro, A. Nunez, J. Diaz-Fortuny, J. Castro-Lopez, R. Roca, E. Martin-Martinez, J. Rodriguez, R. Nafria, M. Fernandez, F. V. Univ Seville CSIC Inst Microelect Sevilla IMSECNM Seville Spain UAB REDEC Grp Elect Engn Dept Barcelona Spain

ISBN: (纸本)9781538651537

modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

关键词： Transistors SRAM cells Stress Power supplies Degradation Integrated circuit modeling"

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