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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1418 条记录，以下是1291-1300 订阅

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Reduction of empiricism in the solder joint reliability assessment of QFN packages by using thermo-mechanical simulations

Reduction of empiricism in the solder joint reliability asse...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： M. van Soestbergen R. Roucou M. Rebosolan J.J. M Zaal NXP Semiconductors Package Innovation Gerstweg 2 Nijmegen Netherlands NXP Semiconductors Corporate Quality Gerstweg 2 Nijmegen Netherlands dep. of Aerospace Engineering Delft University of Technology Kluyverweg 1 Netherlands

To ensure sufficient field life of solder joints, standardized stress tests are performed during the development phase of products, where calibrated thermo-mechanical simulations are frequently used to ensure a potentially sufficient robustness margin. In this work we show how simulations are calibrated for the QFN (Quad Flat No leads) package family. Using thorough failure analysis, we found that for QFN packages two types of solder joint failure modes can occur. The first failure mode is a brittle fracture through the intermetallic region near the solder interface, the other mode is a crack through the bulk of the solder. In the simulations we handle both failure modes using two different failure metrics. For the brittle fractures we analyzed the volumetric strain energy density in a thin region near the interface. For bulk fails we computed the volume-averaged inelastic strain energy density across the whole solder joint. Using both metrics we found a correlation between simulation and experimental results, where Miner’s rule was used to correlate the results of any non-functional anchor joint to the experimental results of the functional joints. The correlation can be used to predict the solder performance upfront in the design phase, and thus reduce the experimental effort during product development.

关键词： Measurement Correlation Computational modeling Thermomechanical processes Failure analysis Fatigue Intermetallic

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Parity Generator & Parity Checker Using Sub-threshold Adiabatic Logic

Parity Generator & Parity Checker Using Sub-threshold Adiaba...

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IEEE UP Section conference on Electrical Computer and Electronics (UPCON)

作者： Prashant Gaurav Prashant Sangeeta Singh Saurabh Kumar Pandey Microelectronics and VLSI design NIT Patna Bihar India Sensors and Optoelectronics Research Group (SORG) Indian Institute of Technology Patna Bihta Bihar India

ISBN: (数字)9781665403733

ISBN: (纸本)9781665447478

Power dissipation becomes an essential criterion in VLSI system in the current ultra-low power applications scenario. Sub-threshold adiabatic logic designing has shown its potential as more efficient logic for ultra low energy-consuming circuits. Parity generator and parity checker are important combination circuit for error-free transmission of data. Both of these circuits are widely used for communication to encode the data. These circuits are realized using sub-threshold adiabatic logic (SAL) by deploying CADENCE 45nm technology. Extensive simulation study has been carried out to validate the mathematical expressions. Our study validates the enhanced circuit performance using sub-threshold adiabatic logic. The present work will facilitate researchers for circuit realization for energy applications.

关键词： Semiconductor device modeling Adiabatic Very large scale integration Generators Power dissipation Recycling Integrated circuit modeling

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Development of thermal solutions for high performance laptop computers

Development of thermal solutions for high performance laptop...

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Intersociety conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM)

作者： H.Y. Zhang D. Pinjala O.K. Navas M.K. Iyer P.K. Chan X.P. Liu H. Hayashi J.B. Han Institute of Microelectronics Singapore DSO National Laboratories Singapore Fujikura Limited Tokyo Japan Optical Communication Operation Agilent Technologies Inc. Singapore

In this research project, advanced thermal solutions for high performance laptop computer have been developed. This development involves design and implementation of a heat sink assembly, application of a heat pipe and thermal evaluation by modeling and measurement. The heat sink assembly has been designed and the thermal performance has been examined by measurements. A heat pipe assembly with two heat spreaders has been designed as the heat transport medium from microprocessor to the heat sink. In the system modeling, a compact model for the flip chip BGA package has been developed. Implementation of the compact model for the packages in the system modeling greatly reduces the grid size and thus makes the system simulation feasible. System measurements are performed with thermal solutions. Measurement results show that present thermal solutions are able to dissipate a power of 25 to 30 W from the microprocessor. The predicted junction temperatures by system simulation are compared with measurements and an agreement within 4% has been attained. Parametric studies have been conducted with the validated system level model.

关键词： Portable computers High performance computing Heat sinks Semiconductor device measurement Assembly Microprocessors Packaging Power system modeling Application software Flip chip

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Characterization and modeling of Cure-Induced Thermo Mechanical Properties and Chemical Shrinkage of Epoxy Resins

Characterization and Modeling of Cure-Induced Thermo Mechani...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Venu Prakash Kasinikota Wolfgang Muehleisen Markus Grinschgl Alexander Steiner Siegfried Hasil Margit Christa Lang Polymer Competence Center Leoben GmbH (PCCL) Leoben Austria Institute of Mechanics Montanuniversität Leoben Leoben Austria Silicon Austria Labs GmbH (SAL) Villach Austria GIPRO GmbH Peggau Austria

Epoxy resins are widely used in molding electrical insulators and electronic components due to their superior dielectric properties and mechanical strength. However, due to poor process control along with the complex geometry of their components, parts can entail air pockets, cracks, or deformations driven by residual stresses. To address these challenges, this research uses the Computational Fluid Dynamics (CFD) software Autodesk Moldflow Synergy 2023 to visualize epoxy resin flow behavior and predict the curing behavior as it flows through the mold using respective models. When simulating the mold-filling behavior, comprehensive thermo-mechanical data are required for both uncured and cured states of cycloaliphatic epoxy resins. Therefore, it was crucial to thoroughly characterize the material to obtain precise material parameters for using them in simulations, as these parameters play a vital role in the accuracy of the simulations. Python-based formulations of the Prout-Tompkins cure kinetic and Cross-Castro-Macosko viscosity models are used to comprehensively analyze the flow front and curing behavior during an Automatic Pressure Gelation (APG) process. This research provides valuable insights into the behavior of epoxy resin when molded in complex scenarios. It enables the design of optimized molds while allowing for fast and efficient evaluation and optimization of process parameters, ultimately reducing high rejection rates as safety critical parts, like insulators, need to be flawless.

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Live Thermal simulation Using Digital Twin for Efficient Semiconductor Layout design

Live Thermal Simulation Using Digital Twin for Efficient Sem...

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Electronics Packaging Technology conference (EPTC)

作者： Bin He Gongyue Tang Institute of Microelectronics (IME) Agency for Science Technology & Research (A*STAR) Singapore Republic of Singapore

ISBN: (数字)9798331522001

ISBN: (纸本)9798331522018

This paper presents a novel approach for rapid thermal assessment of electronic devices using a Reduced-Order Model (ROM) based digital twin, with specific application to Electric Vehicle (EV) drivetrain inverters. The method utilizes Singular Value Decomposition (SVD) to construct a computationally efficient model that enables real-time manipulation of chip layouts and instant visualization of thermal impacts. Tested on both homogeneous and heterogeneous chip configurations, the approach demonstrates high accuracy with maximum temperature differences of ~3 K compared to Computational Fluid Dynamics (CFD) simulations and significant computational efficiency (results generated in ~1 second). This technology offers a powerful tool for balancing increased power density demands with effective thermal management, potentially accelerating the development of high-performance EV drivetrain inverters.

关键词： Power system measurements Accuracy Density measurement Computational modeling Computational fluid dynamics Electric vehicles Inverters Digital twins Computational efficiency Read only memory

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Thermal modeling and simulation of a package-on-package embedded micro wafer level package (EMWLP) structure at the package and system-level

Thermal modeling and simulation of a package-on-package embe...

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Electronics Packaging Technology conference (EPTC)

作者： Yen Yi Germaine Hoe Chong Ser Choong Vempati Srinivasa Rao Gaurav Sharma Zhang Xiaowu D. Pinjala Institute of Microelectronics Agency for Science Technology and Research Singapore Singapore STATS ChipPAC Singapore

In the embedded wafer-level packaging field, the embedded micro wafer level package (EMWLP) technology leverages on fan-out redistribution connections, keeping the reliance on wire-bonding and flip-chip bump connections to a minimum, thus streamlining the packaging process. As the embedded micro wafer level packaging (EMWLP) technology evolves to capitalize on package-on-package (POP) technology, this study's parametric thermal modeling focuses on analyzing the thermal impact of increased density in a low thermal conductivity packaging material. The package design in this work has the following specifications: the memory EMWLP (die size: 7×7×0.2mm) on logic EMWLP structure (die size : 8×8×0.2mm), sized 12×12×0.9mm in total. The POP structure, furthermore, incorporates through-mold-interconnects (TMI) in the bottom logic package to provide short electrical connection from the top package to the board level. The impact on multi-package thermal resistance is then studied as the following parameters vary: power dissipation (in both packages); mold conductivity; number of TMIs; number of solder ball connections; inclusion and size of an interpackage heatslug; inclusion and thermal conductivity of a top heatspreader. The thermal management of the dies are also studied based on the above measures and was found to accommodate under 4W of total POP power. Finally, simulation results for a general system-level thermal modeling of the EMWLP POP in a cellphone scenario are also conducted with passive thermal management solutions proposed.

关键词： Thermal conductivity Conductivity Electronic packaging thermal management Heating Arrays Cooling Junctions

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A Modified Inter-Stage Binary Comparator Based on Parallel Prefix for Low Power and High-Density Applications

A Modified Inter-Stage Binary Comparator Based on Parallel P...

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IEEE UP Section conference on Electrical Computer and Electronics (UPCON)

作者： Rahul Kumar Shaleen Sangeeta Singh Microelectronics and VLSI Lab NIT Patna Bihar India

ISBN: (数字)9781665403733

ISBN: (纸本)9781665447478

A recently reported parallel prefix tree approach is used to realize the N-bit comparator. The sub-circuit is modified to achieve the same functionality for a comparator with a lesser number of transistors, power and power delay product. To achieve maximum swing at the output, a modification technique is introduced to overcome the effect of weak zero. An extra path is provided between the output and ground to overcome the effect of poor noise margin in the circuit. The implemented circuit is based on the pass transistor logic. The pre-layout simulation of the design is performed using the Cadence EDA tool of 180 nm standard CMOS technology. The proposed XNOR-AND cell element of comparator shows improvement in the number of transistors, area, and average power.

关键词： Semiconductor device modeling Power demand Tools CMOS technology Transistors Transient analysis Standards

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Numerical modeling of through silicon via (TSV) stacked module with micro bump interconnect for biomedical device

Numerical modeling of through silicon via (TSV) stacked modu...

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Electronics Packaging Technology conference (EPTC)

作者： Chee Houe Khong Xiaowu Zhang Navas Khan Soon Wee Ho Ying Ying Lim Leong Ching Wai Sharon Lim V. Kripesh D. Pinjala Andy Fenner Institute of Microelectronics A*STAR (Agency for Science Technology and Research) Singapore Science Park II Singapore Institute of Microelectronics A*STAR (Agency for Science Technology and Research) Singapore SG Memorial Medical Center Tempe AZ USA

A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-dimensional plane strain analysis using the global-local technique, based on St. Venant's principle, is performed on the diagonal cross-section of the wafer. The thermal-mechanical modeling has shown that the shear stress S xy at the micro-bump, compressive stress S y at the interconnection and shear stress S xy at the TSV are reduced for off-pad via as compared to on-pad via. This is because the CTE mismatch between the micro-bump and TSV is no longer effective when the TSV is offset. Also the work presented that the offset distance of the off-pad via does not have an impact to the compressive stress S y and shear stress S xy at the interconnection. There are also no significant changes in the shear stress S xy at the TSV as the off-pad via moves outward to the die edge. As we knows that the bending stress S x is a major factor contributing to die cracking due to coefficient of thermal expansion (CTE) mismatch. Our simulation results showed that the bending stress S x of the top die and bottom die was not affected by increasing the offset distance of the off-pad via even to the die edge. Thus it is an advantage to plate the through-silicon-via away from the micro-bump to avoid stresses complication arises from CTE mismatch.

关键词： Through-silicon vias Load modeling Computational modeling Copper Compressive stress Materials

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Infocommunication Networks design with Self-Similar Traffic

Infocommunication Networks Design with Self-Similar Traffic

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International conference on CAD Systems in microelectronics (CADSM)

作者： Dmytro Ageyev Aram Mohsin Tamara Radivilova Lyudmyla Kirichenko Infocommunication Engineering Department Kharkiv National University of Radio Electronics Kharkiv Ukraine Applied Mathematics Department Kharkiv National University of Radio Electronics Kharkiv Ukraine

The parametric synthesis is one of the planning stages of infocommunication networks. Recent studies of network traffic properties have shown that models of self-similar processes (self-similar traffic) describe traffic in networks more accurately. In this study, based on previously known studies of self-similar traffics, infocommunication network synthesis methods have been proposed. Using the proposed models and calculation expressions allow to solve the problems of parametric synthesis by the known characteristics of the input traffic flows. The solution method involves the distribution of traffic along the routes, determining the parameters of aggregated traffic in the communication channels, determining the bandwidth of the communication channels. The correctness of the results obtained by this method was verified using modeling by comparing them with estimated values, and also measured in segments of real networks. As a result of the simulation the reliability of the proposed method for determining the parameters of aggregated self-similar traffic and the method of parametric synthesis has been proven.

关键词： Communication channels Fractals Dispersion Mathematical model Telecommunication traffic Load modeling

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simulation and experimental research on the multi-band slot-loaded printed antenna

Simulation and experimental research on the multi-band slot-...

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International conference on Communication Technology (ICCT)

作者： Run-nan Cai Shu Lin Guan-long Huang Jin-xiang Wang School of Electronics and Information Engineering Harbin Institute of Technology Harbin China Electronic Science and Technology post-doctoral research center Harbin Institute of Technology Harbin China Department of Microelectronics Science and Technology Harbin Institute of Technology Harbin China

Slots which are parallel with the bottom side are loaded at the two equilateral sides of the monopole isosceles triangle printed antenna to achieve multi-band in the operating frequency. The antenna is simulated by CST MICROWAVE STUDIO®, a 3-dimentional full wave electromagnetic simulation software, the simulated results indicate that the central frequency of the pass-band, as well as the bandwidth and the number of the pass-band can be controlled by the slots' length and width, loading position and the number of the slots. The resonant frequencies have certain relation with parameters of the antenna structure, and the interaction between pass-bands is week. A monopole multi-band antenna synchronously operating in three pass-bands, 2.4/3.5/5.5 GHz, is designed and fed by coplanar waveguide. The simulated results also show that the antenna has omnidirectional radiation in H plane. Based on the simulation, prototype of the antenna is manufactured and measured. Finally, the measured results well match the simulated, which verify the design idea is feasible. The antenna size is just 27.74% of the corresponding wavelength of the first resonant frequency, and this compact antenna can be applied in WLAN and WiMAX systems.

关键词： Frequency measurement Load modeling Antennas Resonant frequency Microwave measurements Microwave communication

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