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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1418 条记录，以下是1301-1310 订阅

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Quantum correction simulation of random dopant-induced threshold voltage fluctuations in nanoscale metal-oxide-semiconductor structures

Quantum correction simulation of random dopant-induced thres...

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IEEE conference on Nanotechnology

作者： Yiming Li Shao-Ming Yu Microelectronics and Information Systems Research Center National Chiao Tung University Hsinchu Taiwan Department of Computational Nanoelectronics National Nano Device Laboratories Hsinchu Taiwan Department of Computer and Information Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)0780391993

In this paper, we explore random dopant-induced threshold voltage fluctuations by directly solving quantum correction model for nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs). To calculate the variance of the threshold voltage of nanoscale MOSFETs, quantum correction model at equilibrium conditions is expanded and numerically solved with perturbation and monotone iterative methods. Fluctuations of threshold voltage resulting from the random dopant, variations of gate oxide thickness and epitaxial layer, and the device width are calculated. Classical and quantum mechanical results are provided to support the conclusions drawn from the theoretical findings. In contrast to traditional quantum Monte Carlo approach and small signal analysis of the Schrodinger-Poisson equations, this approach shows good accuracy and computational efficiency, and is ready for industrial technology computer-aided design application.

关键词： Threshold voltage Fluctuations Nanostructures Semiconductor process modeling MOSFETs FETs Iterative methods Epitaxial layers Quantum mechanics Quantum computing

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W-band Broadband Frequency Multiplier

W-band Broadband Frequency Multiplier

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IEEE Asia-Pacific conference on Antennas and Propagation (APCAP)

作者： Xi Fang Bo Zhang Zhongqian Niu Yuanbo Wen Lei Wang School of Optoelectronic Engineering Chongqing University of Posts and Telecommunications Chongqing China Chongqing Institute of Microelectronics Industry Technology UESTC Chongqing China School of Electronic Science and Engineering University of Electronic Science and Technology of China Chengdu China

The W-band frequency range has garnered considerable attention among researchers, necessitating the development of efficient frequency doubling techniques. This paper introduces a novel W-band broadband frequency doubler employing a Schottky diode-based approach. A varactor diode, specifically the M4AE1310 model, serves as the crucial nonlinear element in the frequency doubler design. To streamline the model structure, the biased DC ground structure is eliminated. The frequency doubler comprises a waveguide-microstrip probe, a ground-matched direct, a CMRC (compact microstrip resonant cell) low-pass filter, and an input-output matching section. The modeling simulation is conducted using a combined ADS and HFSS. The simulation results demonstrate exceptional frequency doubling efficiency, yielding an output power of approximately 10 dBm when driven with a power of 20 dBm within the W-band frequency range.

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Investigation of Mechanical Reliability of Cu/low-k Multi-layer Interconnects in Flip Chip Packages

Investigation of Mechanical Reliability of Cu/low-k Multi-la...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Chihiro J. Uchibori Xuefeng Zhang Sehyuk Im Paul S. Ho Tomoji Nakamura Fujitsu Laboratories of America Inc. Sunnyvale CA USA Microelectronics Research Center University of Texas Austin Austin TX USA Fujitsu Laboratories Limited Akiruno Tokyo Japan

The impact of chip-package interaction (CPI) on the reliability of Cu/low-k interconnects in a flip-chip package for high performance ULSI was investigated using finite element analysis (FEA). A 3D four-level sub-modeling approach was used to analyze the CPI to link the deformation from the package level to the interconnect level. The energy release rate (ERR) and fracture mode at critical interface were calculated using a A modified virtual crack closure technique (MVCC). The simulation was focused on the die attach process for Pb- free process before underfilling where the maximum CPI effect is expected. First the general characteristics of CPI were analyzed for interfaces in two metal-layer interconnects. The ERR was found to increase rapidly with decreasing modulus of Inter Layer Dielectric (ILD) although the effect of CTE of ILD was found to be small. Next, the CPI for a four metal-layer structure was investigated. Here the ERR for upper M3 and M4 levels were consistently higher than those of lower Ml and M2 levels. If the same low-k ILD is used for all layers, the M4 interfaces show 2.5 times higher ERR than the lower levels. However, when TEOS is used in the M4 level, the ERR at M3 interfaces becomes 35% higher than the M4 level. The wiring dimensions and ILD properties were found to be important in controlling CPI. The CPI impact on ultra low-k reliability and interconnect design rules for the 65 nm technology and beyond are discussed.

关键词： Flip chip Packaging Integrated circuit interconnections Wiring Ultra large scale integration Finite element methods Thermal stresses Materials reliability Wafer scale integration Performance analysis

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Numerical simulation for Flow Boiling in Microchannels with Different Pin Fin Arrays

Numerical Simulation for Flow Boiling in Microchannels with ...

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Electronics Packaging Technology conference (EPTC)

作者： Li Hongying Pan Lunsheng Lou Jing Zhang Xiaowu Le Ducvinh Cheng Ming Li Jun Kang Chang Wei Chui King Jien Feng Huicheng A*STAR Institute of High Performance Computing Connexis Singapore A*STAR Institute of Microelectronics Connexis Singapore

ISBN: (纸本)9798350398861

The rapid development of technology in the past years brings unprecedent challenges in the cooling of electronic devices. Densely packed electronic systems require more efficient ways to dissipate the heat generated by the electronic components. The present study develops a numerical model to investigate flow boiling in micro-channels. Volume of Fluid method is adopted to capture the interface between the liquid and vaporized gas. The results from the developed model are validated against the existing published data. Upon this achieved, we then applied the model to simulate flow boiling in micro-channels with different pin-fin structures. The effects of pitch for the pin-fins are investigated and the optimized design of pin-fin structure is proposed. (“***”)

关键词： Heating systems Solid modeling Three-dimensional displays Predictive models Thermal management Electronic packaging thermal management Numerical simulation

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Board level FEA reliability and stress modeling for chip-to-wafer bonded chiplet package

Board level FEA reliability and stress modeling for chip-to-...

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Electronic Components and Technology conference (ECTC)

作者： Rathin Mandal Chai Tai Chong Institute of Microelectronics Agency for Science Technology and Research (A*STAR) Innovis Singapore

Chip-to-wafer interconnect approach is to produce denser and smaller dies, while improving inter-chip bandwidth and power dissipation. In this work a vertical system integration is done by copper pillar and solder interconnects. Three-dimensional (3D) integration technology uses chip-to-wafer bonding to achieve effective chip integration. By structural simulation and modeling a reliable package selection is made from different package designs, epoxy mold compounds (EMC), polymer dielectric (PD) materials and different other package parameters. In this simulation and modeling an approach has been taken to model two levels of solder interconnects namely copper pillar solder micro-bump and BGA (ball grid array) solder in the same FEA (finite element analysis) model. FEA mesh densities in 1 st and 2 nd interconnects are joined by contact pair definition. Parametric studies are done for three different EMC and three different PD materials. 1 st level solder interconnect or micro-bump temperature cycling (TC) reliability life is significantly higher than 2 nd level solder interconnect due to presence of EMC around the 1 st level interconnect. High CTE (coefficient of thermal expansion) of EMC shows very poor solder life for 1 st level solder interconnect. PD material CTE shows significant impact on component side solder life for 2 nd level interconnect. Also, higher PD material CTE shows worsening 1 st level interconnect life. Stress analysis shows pad diameter smaller than UBM (under bump metallization) opening is a better design.

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Applied modeling Framework in Integrated Circuit design and Reliability

Applied Modeling Framework in Integrated Circuit Design and ...

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Electronic Components and Technology conference (ECTC)

作者： Papa Momar Souare Cedrick Bouchard Eric Duchesne James Zaccardi David Pettit Francois Vachon Advanced Packaging &amp Modeling IBM Systems Bromont Canada Semiconductor Packaging Engineer Manager Viasat Inc RF / Microwaye Viasat Inc Business Development Manager IBM Systems Bromont Canada

A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure modes in microelectronics packaging such as module warpage, solder fatigue cracking, TIM tearing or delamination and underfill corner cracking causing chip circuits delamination and increased flip chip solder joint fatigue. The numerical simulations were performed using a specialized cloud software infrastructure named PACK using a one-way macro to micro model approach. Model validation was split into two main aspects. First, the linear behavior of the macro model was based on bottom surface metallurgy (BSM) warpage. BSM module warpage of several packages from ICOS data was used to validate the numerical model, and both room temperature warpage as well as the shape predicted by the FEM model agreed with the ICOS data. Second, the fatigue modeling accuracy was evaluated based on data issued from devices built and subjected to thermal cycles akin to the models. The non-linear simulation of creep was then performed using Norton’s creep model, using SAC material properties obtained from experimental sources. The strain energy density (SEND) was used as a metric to quantify solder creep and interconnect fatigue. The SEND was averaged over a few layers of elements at the top and bottom of the interconnects, forming a normalized volume where creep (and failure probability) was the highest. Early thermal cycles solder fatigue fails were detected electrically on the prototypes, located on the memory module’s corners. These observations were confirmed with dye and pry which corresponded with the computed SEND map and distribution given by the numerical model. Failure analysis (FA) showed that cracks initiated near the bottom side pad neck and propagating along the BGA which was also in agreement with the modeled metric’s distribution across critical BGAs. Finally, l

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D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in Large-Scale M3D 2TOC DRAM Bit Cell Evaluation via Statistical modeling Methodology

D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in L...

引用

International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yue Zhao Yong Yu Jingrui Guo Lingfei Wang Nan Yang Jianpeng Jiang Yanan Lu Menglong Zhou Shijie Huang Lihua Xu Zhenhua Wu Guanhua Yang Di Geng Guilei Wang Bryan Kang Chao Zhao Ling Li Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China Beijing Superstring Academy of Memory Technology Beijing China

ISBN: (数字)9798331516352

ISBN: (纸本)9798331516369

Device nonuniformity of ultra-scaled novel vertical a-IGZO-FETs is induced by multi-sources, such as dimension variation and material disorder, limiting large-scale DRAM design. Particularly, fluctuation of disorders in an amorphous channel exhibits a great impact on density of states (DOS) contributing to statistical effects on gate controllability and transport mechanisms. To clarify this issue, TCAD simulations are conducted by adjusting geometric dimensions and DOS, and corresponding statistical characteristics (e.g., on-voltage and on-current etc.) are extracted from up to 80 samples of down to channel length of 50nm. Such effects are further incorporated into a surface-potential based physics compact model via calibration to experiments. Using this model, the vertical a-IGZO-FET-based 2TOC DRAM is firstly investigated with the statistical analysis of Write/Read performances, supporting device variation aware DTCO flow of future extremely large-scale and high-density M3D memory.

关键词： Semiconductor device modeling Performance evaluation Solid modeling Analytical models Statistical analysis Random access memory Feature extraction Semiconductor process modeling Device-to-device communication Three-dimensional integrated circuits

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Signal Integrity simulation for SiP Using GTLE

Signal Integrity Simulation for SiP Using GTLE

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2011 12th International conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

作者： Jia Jia liqiang Cao lixi Wan Institute of Microelectronics Chinese Academy of Science Beijing 100029 China

Signal integrity (SI) simulation for system-in-package (SiP) is a bottleneck in SiP design flow. This paper presents a novel numerical algrothm for SI simulation in packaging structure. This algorithm is based on 2D Generalized Transmission Line Equation (GTLE), Finite Difference Time Domain (FDTD) and mesh division technique. SI is simulated using mesh division technique where the model of SI is obtained by regarding each cell as a 2D transmission line. 2D GTLE is a group partial equation about voltage and current density distribution on a power/ground plane pair. After reduction, the voltage equation for 2D GTLE is obtained, which is a wave equation. One method to solve the wave equation is by the finite-difference scheme. In this paper, the fringe effect and absorbing boundary condition is applied to implement the wave equation efficiently and easily. Three test cases are presented to explain the solution of the wave equation. The methodology described in prior section has been implemented in a CAD tools. The results from our method were compared to those from the full-wave simulator to show efficiently in signal integrity simulation.

关键词： Mathematical model Solid modeling Equations Time domain analysis Finite difference methods Numerical models Integrated circuit modeling

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Thermal modeling for power MOSFETs in DC/DC applications

Thermal modeling for power MOSFETs in DC/DC applications

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Y. Bulut K. Pandya Vishay Siliconix Inc. Santa Clara CA USA

In DC-to-DC converters, power MOSFETs in through-hole packages have almost completely disappeared as the industry moves toward all-surface-mount implementations. This means increasing demand for power MOSFET packages with smaller footprint, lower profile, and lower thermal resistance. While MOSFETs in the D/sup 2/PAK and DPAK packages could provide the appropriate level of power dissipation for DC-to-DC applications, their physical size constrained converter-packaging density. Surface-mount alternatives such as the SO-8 address size issues, but their thermal performance is limited by a need to dissipate power through the leads and onto the PCB. One of the principal concerns in DC-to-DC power supply design is controlling heat. By increasing the efficiency of the power switch (MOSFET), it is possible to reduce heat generated, reducing size requirements and need for heat sinking. Optimal power design distributes power across the DC-to-DC converter to eliminate (or at least greatly reduce) hotspots on the power board. To achieve this, it is critical early in the design phase to understand the thermal effects of critical components. The provision of a heat flow model for the MOSFET, accurately predicting temperature effects for the switching elements on the PCB, will save time in development and allow for optimal space utilization and power component distribution. Recent major developments in silicon technology have helped power MOSFET manufacturers to reduce on-resistance (r/sub DS(on)/) for a given die size to almost negligible levels. MOSFETs for switching applications are now available with silicon resistances around 1 m/spl Omega/. Having reached this plateau, attention is being turned to ways that innovative packaging can be used to improve overall device thermal performance. A basic measure of a device's thermal performance is the junction-to-case thermal resistance, R/sub TH,JC/, which is the thermal resistance between a power MOSFET junction and a specified refe

关键词： MOSFETs Thermal resistance Packaging DC-DC power converters Heat sinks Space heating Space technology Silicon Power dissipation Surface resistance

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An Automatic Chip-Package Co-design Flow for Multi-core Neuromorphic Computing SiPs

An Automatic Chip-Package Co-Design Flow for Multi-core Neur...

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Electronics Packaging Technology conference (EPTC)

作者： Jingjing Lan Vishnu P. Nambiar Rheeshaalaen Sabapathy Rahul Dutta Chai Tai Chong Mihai Dragos Rotaru Kuang Kuo Lin Surya Bhattacharya Kevin Tshun Chuan Chai Anh Tuan Do Institute of Microelectronics Agency for Science Technology and Research Singapore

ISBN: (数字)9781728189116

ISBN: (纸本)9781728189123

The complexity and cost of system-on-chip (SoC) designs keep increasing every year, which has progressively led to more opportunities for 2.5D System-in-Package (SiP) design. While 2.5D integration technology offers advantages for heterogeneous chiplet-based systems, it also poses challenges of a more complex overall design flow with limited EDA tools support, physical design optimization issues, interposer floor-planning difficulties and complex system-level verification. Furthermore, accurate inter-chiplet connection modeling, chiplet characterization and top-level simulation activities are also needed for comprehensive verification of SiPs. To tackle these challenges, we share an automated chiplet-based codesign flow: built on the backbone with standard EDA design tools, an automatic SiP register transfer language (RTL) generator is developed for top-level SiP netlist generation; inter-chiplet connection routing with chip assembly router and parasitic extraction tools; interposer design and bumps placement with the foundry defined redistribution layer (RDL).

关键词： Wires Generators Tools Routing Two dimensional displays Transistors Multicore processing

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