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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"
1418 条 记 录,以下是1301-1310 订阅
排序:
Quantum correction simulation of random dopant-induced threshold voltage fluctuations in nanoscale metal-oxide-semiconductor structures
Quantum correction simulation of random dopant-induced thres...
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IEEE conference on Nanotechnology
作者: Yiming Li Shao-Ming Yu Microelectronics and Information Systems Research Center National Chiao Tung University Hsinchu Taiwan Department of Computational Nanoelectronics National Nano Device Laboratories Hsinchu Taiwan Department of Computer and Information Science National Chiao Tung University Hsinchu Taiwan
In this paper, we explore random dopant-induced threshold voltage fluctuations by directly solving quantum correction model for nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs). To calculate the ... 详细信息
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W-band Broadband Frequency Multiplier
W-band Broadband Frequency Multiplier
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IEEE Asia-Pacific conference on Antennas and Propagation (APCAP)
作者: Xi Fang Bo Zhang Zhongqian Niu Yuanbo Wen Lei Wang School of Optoelectronic Engineering Chongqing University of Posts and Telecommunications Chongqing China Chongqing Institute of Microelectronics Industry Technology UESTC Chongqing China School of Electronic Science and Engineering University of Electronic Science and Technology of China Chengdu China
The W-band frequency range has garnered considerable attention among researchers, necessitating the development of efficient frequency doubling techniques. This paper introduces a novel W-band broadband frequency doub...
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Investigation of Mechanical Reliability of Cu/low-k Multi-layer Interconnects in Flip Chip Packages
Investigation of Mechanical Reliability of Cu/low-k Multi-la...
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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE
作者: Chihiro J. Uchibori Xuefeng Zhang Sehyuk Im Paul S. Ho Tomoji Nakamura Fujitsu Laboratories of America Inc. Sunnyvale CA USA Microelectronics Research Center University of Texas Austin Austin TX USA Fujitsu Laboratories Limited Akiruno Tokyo Japan
The impact of chip-package interaction (CPI) on the reliability of Cu/low-k interconnects in a flip-chip package for high performance ULSI was investigated using finite element analysis (FEA). A 3D four-level sub-mode... 详细信息
来源: 评论
Numerical simulation for Flow Boiling in Microchannels with Different Pin Fin Arrays
Numerical Simulation for Flow Boiling in Microchannels with ...
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Electronics Packaging Technology conference (EPTC)
作者: Li Hongying Pan Lunsheng Lou Jing Zhang Xiaowu Le Ducvinh Cheng Ming Li Jun Kang Chang Wei Chui King Jien Feng Huicheng A*STAR Institute of High Performance Computing Connexis Singapore A*STAR Institute of Microelectronics Connexis Singapore
The rapid development of technology in the past years brings unprecedent challenges in the cooling of electronic devices. Densely packed electronic systems require more efficient ways to dissipate the heat generated b... 详细信息
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Board level FEA reliability and stress modeling for chip-to-wafer bonded chiplet package
Board level FEA reliability and stress modeling for chip-to-...
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Electronic Components and Technology conference (ECTC)
作者: Rathin Mandal Chai Tai Chong Institute of Microelectronics Agency for Science Technology and Research (A*STAR) Innovis Singapore
Chip-to-wafer interconnect approach is to produce denser and smaller dies, while improving inter-chip bandwidth and power dissipation. In this work a vertical system integration is done by copper pillar and solder int...
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Applied modeling Framework in Integrated Circuit design and Reliability
Applied Modeling Framework in Integrated Circuit Design and ...
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Electronic Components and Technology conference (ECTC)
作者: Papa Momar Souare Cedrick Bouchard Eric Duchesne James Zaccardi David Pettit Francois Vachon Advanced Packaging &amp Modeling IBM Systems Bromont Canada Semiconductor Packaging Engineer Manager Viasat Inc RF / Microwaye Viasat Inc Business Development Manager IBM Systems Bromont Canada
A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure mod...
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D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in Large-Scale M3D 2TOC DRAM Bit Cell Evaluation via Statistical modeling Methodology
D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in L...
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International conference on simulation of Semiconductor Processes and Devices (SISPAD)
作者: Yue Zhao Yong Yu Jingrui Guo Lingfei Wang Nan Yang Jianpeng Jiang Yanan Lu Menglong Zhou Shijie Huang Lihua Xu Zhenhua Wu Guanhua Yang Di Geng Guilei Wang Bryan Kang Chao Zhao Ling Li Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China Beijing Superstring Academy of Memory Technology Beijing China
Device nonuniformity of ultra-scaled novel vertical a-IGZO-FETs is induced by multi-sources, such as dimension variation and material disorder, limiting large-scale DRAM design. Particularly, fluctuation of disorders ... 详细信息
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Signal Integrity simulation for SiP Using GTLE
Signal Integrity Simulation for SiP Using GTLE
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2011 12th International conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)
作者: Jia Jia liqiang Cao lixi Wan Institute of Microelectronics Chinese Academy of Science Beijing 100029 China
Signal integrity (SI) simulation for system-in-package (SiP) is a bottleneck in SiP design flow. This paper presents a novel numerical algrothm for SI simulation in packaging structure. This algorithm is based on 2D G... 详细信息
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Thermal modeling for power MOSFETs in DC/DC applications
Thermal modeling for power MOSFETs in DC/DC applications
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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE
作者: Y. Bulut K. Pandya Vishay Siliconix Inc. Santa Clara CA USA
In DC-to-DC converters, power MOSFETs in through-hole packages have almost completely disappeared as the industry moves toward all-surface-mount implementations. This means increasing demand for power MOSFET packages ... 详细信息
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An Automatic Chip-Package Co-design Flow for Multi-core Neuromorphic Computing SiPs
An Automatic Chip-Package Co-Design Flow for Multi-core Neur...
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Electronics Packaging Technology conference (EPTC)
作者: Jingjing Lan Vishnu P. Nambiar Rheeshaalaen Sabapathy Rahul Dutta Chai Tai Chong Mihai Dragos Rotaru Kuang Kuo Lin Surya Bhattacharya Kevin Tshun Chuan Chai Anh Tuan Do Institute of Microelectronics Agency for Science Technology and Research Singapore
The complexity and cost of system-on-chip (SoC) designs keep increasing every year, which has progressively led to more opportunities for 2.5D System-in-Package (SiP) design. While 2.5D integration technology offers a... 详细信息
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