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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1418 条记录，以下是1311-1320 订阅

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Channel noise scan by using simulations of voltage regulator noise to signals

Channel noise scan by using simulations of voltage regulator...

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International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT)

作者： Jimmy Hsu Patt Chang Thonas Su Gong Ouyang Kai Xiao Falconee Lee Y L Li DCG Intel Microelectronics Asia Ltd. Taipei Taiwan DCG Intel Corporation DuPont WA USA

In this paper, channel noise scan approach (CNS) is proposed to efficiently analyze the potential VR-signal coupling issue in the pre-silicon design and the post-silicon debug of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction between the two. The goal of this simulation methodology is to help platform developer to quantify the VR-signal coupling risk and find the outliers of the victim signal nets according to the board layout and the VR design. This methodology can also provide the ability for the designer to do performance/cost tradeoff, layout optimization. To systematically analyze the VR-signal coupling problems, both the frequency and time domain approaches have been developed to characterize the VR-signal coupling in different levels. The frequency domain approach can quickly point out potential issues and the time domain approach is proved to be consistent with the frequency domain but with more detail and intuitive information. A design flow is given to efficiently identify the outliers of victim signals by VR noise coupling impact. designers can improve the layout based on channel noise scan results from the simulations.

关键词： Couplings Noise Layout Integrated circuit modeling Switches Frequency-domain analysis Voltage control

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Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate

Accurate electrical simulation and design optimization for s...

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Electronic Components and Technology conference (ECTC)

作者： Jing Zhou Lixi Wan Fengwei Dai Huijuan Wang Chongshen Song Tianmin Du Yanbiao Chu Maoyun Pan Daniel Guidotti Liqiang Cao Daquan Yu Institute of Microelectronics Chinese Academy of Sciences Beijing China

In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.

关键词： Silicon Through-silicon vias Transmission line measurements Substrates Insertion loss Power transmission lines Permittivity measurement

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Random Dopant Induced Threshold Voltage Fluctuations in Double Gate MOSFET's

Random Dopant Induced Threshold Voltage Fluctuations in Doub...

引用

2004 7th International conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Ling Xia,Xuewen Gan~* Institute of microelectronics,Peking University,Beijing 100871,China

A study by means of analytical modeling and simulation analysis on random dopant induced double gate MOSFET threshold voltage fluctuations is presented. Analytical models describing the standard deviation of threshold voltage distribution associated with dopant fluctuation are *** effects of various double gate MOSFET design parameters,including the doping concentration,oxide thickness,silicon thickness on the threshold voltage fluctuations are *** analytical models predict the general trends in threshold voltage *** effect of dopant position fluctuation is also *** models and simulations show that double gate MOSFET can suppress the impact of random dopant fluctuation on threshold voltage variations compared with single gate MOSFET.

关键词： MOSFET Random Dopant Induced Threshold Voltage Fluctuations in Double Gate MOSFET's

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A modified CMOS nano-power resistorless current reference circuit

A modified CMOS nano-power resistorless current reference ci...

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Shailesh Singh Chouhan Kari Halonen SMARAD-II Department of Micro and Nano Sciences Aalto University School Of Electrical Engineering Finland

In this work, all MOS current reference circuit is proposed using a standard 0.18 μm technology and the simulations were performed using the Cadence Spectre simulator. The proposed current reference circuit is based on, the resistorless current reference circuit suggested by Oguey and Aebishcher. The Oguey's circuit is capable of generating the reference current in a nanoampere range, but with the high temperature coefficient (TC). The reason for high TC, that we found, is the lack of control over the gate-source voltage of an active resistor used in the design. This gate-source voltage is one of the controlling parameters responsible to obtain adequate thermal compensation for the reference current. In the proposed work, we modified the architecture to limit the variation of the gate-source voltage with the temperature and hence controls the thermal behaviour of the reference current. The working supply voltage of the proposed circuit ranges from 1.25 V to 2 V. The temperature coefficients of the reference current generated from the proposed and conventional architectures are 39.8 ppm/°C and 545.12 ppm/°C respectively at a supply voltage of 1.25V for the temperature ranging from -60°C to 85°C. The maximum power consumption of proposed and conventional architecture is 624.8nW and 468.59nW at a supply voltage of 2 V with the layout area of 0.0013μm 2 and 0.001μm 2 respectively.

关键词： Threshold voltage Logic gates Temperature distribution Resistors CMOS integrated circuits Integrated circuit modeling simulation

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A new parameter extraction method for ultra-thin oxide SOI MOSFET's

A new parameter extraction method for ultra-thin oxide SOI M...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： O. Faynot S. Cristoloveanu P. McLarty C. Raynaud J. Gautier LETI (CEA-Technologies Avancées)-DMEL-CEN/G Grenoble France Laboratoire de Physique des Composants à Semiconducteurs (UA-CNRS) ENSERG Grenoble France Department Electrical and ComputerEngineering State University Raleigh NC USA

Parameter extraction stands as a critical issue for the modeling, simulation and design of CMOS transistors and circuits. Over the years, many methods have been proposed, refined and optimized until they became unable to account for new device characteristics brought about by technological progress. Such a situation applies to ultra-thin oxides, where the transconductance may exhibit negative values. The aim of this paper is: (1) to propose an adequate method for the extraction of the threshold voltage V/sub T/, field effect mobility /spl mu//sub 0/, effective channel length (L-/spl Delta/L), gate-induced mobility attenuation factors /spl theta//sub 1,2/; and (2) to demonstrate its superiority over standard techniques used in thicker oxides (>10 nm). Our test devices were n-channel (partially and fully depleted) SOI MOSFET's with silicon thicknesses ranging from 30 to 150 nm, with LDD configuration and various gate oxides from 4.5 to 17.5 nm thick. The device width was 25 /spl mu/m and the gate length varied from 0.4 to 25 /spl mu/m.

关键词： Parameter extraction Semiconductor device modeling Circuit simulation MOSFETs Optimization methods CMOS technology Transconductance Threshold voltage Attenuation Testing

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A low bandwidth pulse-based neural recording system

A low bandwidth pulse-based neural recording system

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Sheng-Feng Yen John G. Harris Department of Electrical and Computer Engineering University of Florida Gainesville FL USA

This research investigates a novel data reduction scheme using adaptive leaky refractory integrate-and-fire (ALRIF) neurons to generate pulses for an implanted neural recording system in wireless transmission applications. The wireless implanted multi-channel recording system imposes many constraints on the system but the major constraint is on low bandwidth. Other constraints including low bandwidth transmission, large dynamic range, low power consumption, small device size and noise robustness, though serious, can be more easily met. This proposed scheme promises to dramatically reduce the required communication bandwidth via three versatile neuron circuit strategies: adaptive, leaky and refractory neurons. This system consists of both front-end hardware and a back-end signal processing. Analog VLSI circuitry (AMI 0.6μm CMOS) was chosen to implement the front-end hardware to transform the signal to a pulse representation with ultra-low bandwidth. On the back-end, the system can either reconstruct the original signal and run traditional spike sorting or run spike sorting directly in the pulse domain. The ALRIF neuron circuit can reduce the bandwidth efficiently to support the pulse-based spike sorting. MATLAB simulation results for the neuron models are proof of concept. Circuit design for each building block has been presented and simulated in Cadence. Bench-top hardware system testing shows feasibility of in vivo neural recording applications.

关键词： Neurons Bandwidth Wireless communication Threshold voltage Sorting Integrated circuit modeling Hardware

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DAC technologist panel "the IC nanometer race - what will it take to win"

DAC technologist panel "the IC nanometer race - what will it...

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design Automation conference

作者： W.C. Rhines L. Parker G. Singer P. Magarshack D. Buss Fu-Chieh Hsu Ho-Kyu Kang Mentor Graphics Corporation Wilsonville OR USA Intel Corporation Santa Clara CA USA ST Microelectronics S.r.L. Crolles France Texas Instruments Inc. Dallas TX USA Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Samsung Electronics Company Limited Seoul South Korea

Creating ICs in the nanometer age is a high-stakes race that few companies can afford to compete in - and even fewer can win. Hear how senior technologists from the world's top technology companies are striving to improve their chances of success. Will leakage constraints force power-sensitive applications to stay with older technologies, or will there be a bifurcation to a new process technology? Will ballooning capital equipment expenses delay new capacity or price out design rules for mainstream applications? Will silicon-on-insulator and new device structures like FinFETs force rethinking of design, modeling and simulation methodologies? And which EDA technologies, delivered when, will be critical for victory? These senior technologists, from some of the biggest companies in the high tech industry, will discuss and debate how they think the overall industry will successfully transition to the nanometer age. Specific examples from the technologists' broad exposure to industry trends and competitors will help illustrate their forecasts and predictions

关键词： Application specific integrated circuits Costs Silicon on insulator technology Graphics Economic forecasting Instruments Semiconductor device manufacture Bifurcation Delay FinFETs

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A MEMS resonator tank for an RF VCO application

A MEMS resonator tank for an RF VCO application

引用

IEEE International conference on Electronics, Circuits and Systems (ICECS)

作者： Daniel Zammit Owen Casha Ivan Grech Edward Gatt Joseph Micallef Department of Microelectronics and Nanoelectronics University of Malta Msida Malta

This paper presents the design and study of a MEMS tapped-inductor LC resonator tank, proposed to evaluate the improved performance over that generally achieved in standard CMOS passive component integration. The resonator tank, consisting of a fixed-value inductor and a variable capacitor, was implemented in the MetalMUMPs process and was targeted for a VCO intended for telemetry applications. A geometrically optimized 1.25 nH horseshoe inductor was designed and results show that it exhibits a Q-factor of 63 at 7.3 GHz and a self-resonating frequency of 17.6 GHz. In addition, an improved π-inductor model is proposed for design and simulation purposes. The variable capacitor was designed in a parallel-plate topology, using four serpentine springs. The capacitance can be varied from 0.183 pF to 0.245 pF with an actuation voltage in the range of 0 V-to-11.7 V. A Q-factor of 62 at 1.1 GHz and a self-resonating frequency above 10 GHz were achieved. The designed inductor and capacitor were configured in a resonator tank topology yielding an overall Q-factor of 22 at 4.9 GHz.

关键词： Inductors Q-factor Micromechanical devices Capacitors Substrates Integrated circuit modeling Voltage-controlled oscillators

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Flexible system model and architectural exploration for HIPERLAN 2 DLC wireless LAN protocol

Flexible system model and architectural exploration for HIPE...

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IEEE International conference on Communications (ICC)

作者： V. Nema B.V. Poucke M. Glassee S. Vernalde Interuniversity Microelectronics Center (IMEC) Leuven Belgium Interuniversitair Micro-Elektronica Centrum Leuven Vlaams-Brabant BE IMEC Leuven Belgium

Modern wireless communication protocols like HIPERLAN 2, IEEE 802.11a etc. support high data rates of the order of 54 Mbps and have strict timing requirements. Although protocols define the communication rules, they do not address critical design issues like hardware/software (HW/SW) partitioning and the implementation of different algorithms, which have a critical impact on the system performance. We have developed a platform independent flexible system model based on the HIPERLAN 2 data link control (DLC) protocol that allows easy experimenting with HW/SW partitioning and different algorithms. Our design methodology allows performance evaluation at the system level as well as path to HW/SW implementation. The simulation results presented give good information on the computational complexity of different components and on the HW/SW partitioning of the HIPERLAN 2 DLC layer. The HW/SW partitioning results have been verified with a working demonstrator and the object oriented model can be easily extended for future protocols.

关键词： Wireless LAN Wireless application protocol Object oriented modeling Partitioning algorithms Wireless communication Timing Algorithm design and analysis Hardware Communication system software Software performance

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Pragmatic approaches to implement self-checking mechanism in UVM based TestBench

Pragmatic approaches to implement self-checking mechanism in...

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International conference on Advances in Computer Engineering and Applications (ICACEA)

作者： Raghav Madan Nishant Kumar Sujay Deb ECE IIIT-Delhi Delhi India ST Microelectronics Greater Noida India

ISBN: (纸本)9781467369121

Functional Verification of today's highly complex designs cannot rely simply on static verification techniques as these techniques are incapable of verifying modern complex digital designs. However, simulation-Based Verification (SBV) which comes under dynamic verification approach can handle these complex systems. Among the various modern SBV approaches, Universal Verification Methodology (UVM) provides well established and flexible solution for complex system design verification. Flexibility of UVM lies in the fact that the verification environment developed using UVM consists of reusable components and is supported by tools of all major vendors of the industry. UVM provides a complete framework to achieve coverage driven verification that includes automatic test generation, self-checking testbenches and coverage metrics [1]. The self-checking capability provided by UVM is not very well defined and, hence, forces verification engineer to develop complex checking mechanism even for very small designs and also provides less resources for thorough checking of complex designs. In this paper, we will discuss implementation details of different kind of checking mechanisms that can be used along with UVM based verification environment to improve its capability of functional checking, protocol checking and reaching hidden bugs of the design Under Verification (DUV).

关键词： Monitoring Ports (Computers) Computational modeling Protocols Hardware design languages IP networks Computers

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