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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Laser attacks on integrated circuits: From CMOS to FD-SOI

Laser attacks on integrated circuits: From CMOS to FD-SOI

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International conference on design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Jean-Max Dutertre Stephan De Castro Alexandre Sarafianos Noémie Boher Bruno Rouzeyre Mathieu Lisart Joel Damiens Philippe Candelier Marie-Lise Flottes Giorgio Di Natale ENSM.SE Centre Microlectronique de Provence-Georges Charpak France ST Microelectronics Avenue Clestin Coq France STMicroelectronics LIRMM (CNRS UMR N5506) France

The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model permitted us to draw the laser sensitivity map of a SRAM cell. It demonstrates a very close correlation with experimental measures. We also introduce the preliminary results we gathered to build a similar electrical model for FD-SOI circuits. FD-SOI technology is expected to be less sensitive to laser than CMOS.

关键词： Semiconductor lasers Laser modes Transistors Integrated circuit modeling Photoconductivity Junctions Measurement by laser beam

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Lead-free solder material characterization for thermo-mechanical modeling

Lead-free solder material characterization for thermo-mechan...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Edith S. W. Poh W. H. Zhu X. R. Zhang C. K. Wang Anthony Y. S. Sun H. B. Tan Packaging Analysis & Design Center United Technologies Research Center Inc. Singapore Singapore

Systematic mechanical characterization has been done on lead-free solder alloys, i.e., SAC105, SAC205, SAC305, SAC105Ni0.02, and SAC105Ni0.05 as promising alternatives of SnPb solder. Solder joints in service stay in high homologous temperatures that have profound effects on mechanical properties such as creep and the apparent elastic modulus. Mechanical deformation behaviors of bulk solder alloys at temperatures between 298 K and 398 K, as well as strain rates between 10 -5 to 10 -1 under isothermal conditions, have been studied for the above 5 solder alloys with a designed bulk test vehicle. Isostress loading conditions on the solders were also conducted to study creep behaviour. Based on substantial experimental measurement results, the elastic modulus, yield stress and UTS of the various SAC solder alloys show direct relationships with Ag content at temperatures between 298 K and 398 K. The relationships of strain rate, temperature, Ag content and material properties were developed and material constants are presented. Basic material parameters with viscoplastic constitutive relations for solders encompassing temperature and strain rate dependence have been obtained through curve fitting with experimental data. The creep constitutive model has also been established. By implementing the developed creep or viscoplastic constitutive models of solders into FEA models, the life of an electronic package under thermal cycling and drop performance in board level tests can be evaluated. Material compositions such as Ag content and Ni dopant effect are also studied for their influence on mechanical properties. It was reported that Ni dopant could improve solder joint drop performance by changing the microstructure of the material.

关键词： Environmentally friendly manufacturing techniques Lead Thermomechanical processes Temperature Creep Semiconductor process modeling Soldering Mechanical factors Capacitive sensors Strain measurement

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Characterization and modeling of Thin Film Interface Strength Considering Mode Mixity

Characterization and Modeling of Thin Film Interface Strengt...

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Electronic Components and Technology conference (ECTC)

作者： A. Xiao L. G. Wang W. D. van Driel L. J. Ernst O. van der Sluis D. G. Yang G. Q. Zhang Delft University of Technnology Delft Netherlands NXP Semiconductors Research Nijmegen Netherlands

Interfacial delamination is a common cause of failure in microelectronic packages. Characterization and prediction of interface behavior in manufacturing, testing and application conditions is demanded in order to reduce development times and costs of IC packages. In the design processes of microelectronics, possible interface delamination is evaluated by the critical energy release rate to detach the materials. This critical energy release rate can be obtained experimentally using various approaches. However, its measurement is complicated due to the fact that adhesion strength is not only temperature and moisture dependent but also stress state (mode mixity [1]) dependent. This paper describes our efforts on interface characterization as a function of mode dependency. A new test setup is designed and built. It allows transferring two separated loads on a single specimen. The test methodology that is developed in this paper is also able to evaluate the interfacial fracture toughness as function of temperature and moisture. The crack length, necessary for calculation of the energy release rate is measured by means of an optical microscope. Finite element simulation is used to interpret the experimental results and thus to establish the critical energy release rates and mode mixities.

关键词： Transistors Delamination microelectronics Packaging Moisture Optical microscopy Manufacturing Integrated circuit testing Costs Application specific integrated circuits

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A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper)

A Method of Estimating FD Capacitance with Large Size Photod...

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IEEE International conference on Integrated Circuits, Technologies and Applications (ICTA)

作者： Chao Gu Zhenhua Guo Shuangming Yu Liyuan Liu Jian Liu Peng Feng Nanjian Wu State Key Laboratory of Superlattices and Microstructures Institute of Semiconductors Chinese Academy of Sciences Beijing China School of Microelectronics University of Chinese Academy of Sciences Beijing China Center of Materials Science and Optoelectronics Engineering University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9781728180328

ISBN: (纸本)9781728180335

This work proposes a simple method of calculating FD capacitance in 2-dimensional (2D) TCAD simulation that combines with pixel layout, simplifying the estimation of CIS FD design. Approximate per unit FD junction capacitance can be extracted by few TCAD simulations. This method has been verified using an image sensor chip with 10um-size pixel fabricated in 180nm CIS process. The testing results show that the error percentage of FD capacitance between test and calculation is approximately 5.90%.

关键词： Image sensors Two dimensional displays Layout Photodiodes Integrated circuit modeling Testing Parasitic capacitance

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Live Thermal simulation Using Digital Twin for Efficient Semiconductor Layout design

Live Thermal Simulation Using Digital Twin for Efficient Sem...

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Electronics Packaging Technology conference (EPTC)

作者： Bin He Gongyue Tang Institute of Microelectronics (IME) Agency for Science Technology & Research (A*STAR) Singapore Republic of Singapore

ISBN: (数字)9798331522001

ISBN: (纸本)9798331522018

This paper presents a novel approach for rapid thermal assessment of electronic devices using a Reduced-Order Model (ROM) based digital twin, with specific application to Electric Vehicle (EV) drivetrain inverters. The method utilizes Singular Value Decomposition (SVD) to construct a computationally efficient model that enables real-time manipulation of chip layouts and instant visualization of thermal impacts. Tested on both homogeneous and heterogeneous chip configurations, the approach demonstrates high accuracy with maximum temperature differences of ~3 K compared to Computational Fluid Dynamics (CFD) simulations and significant computational efficiency (results generated in ~1 second). This technology offers a powerful tool for balancing increased power density demands with effective thermal management, potentially accelerating the development of high-performance EV drivetrain inverters.

关键词： Power system measurements Accuracy Density measurement Computational modeling Computational fluid dynamics Electric vehicles Inverters Digital twins Computational efficiency Read only memory

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A Modified Inter-Stage Binary Comparator Based on Parallel Prefix for Low Power and High-Density Applications

A Modified Inter-Stage Binary Comparator Based on Parallel P...

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IEEE UP Section conference on Electrical Computer and Electronics (UPCON)

作者： Rahul Kumar Shaleen Sangeeta Singh Microelectronics and VLSI Lab NIT Patna Bihar India

ISBN: (数字)9781665403733

ISBN: (纸本)9781665447478

A recently reported parallel prefix tree approach is used to realize the N-bit comparator. The sub-circuit is modified to achieve the same functionality for a comparator with a lesser number of transistors, power and power delay product. To achieve maximum swing at the output, a modification technique is introduced to overcome the effect of weak zero. An extra path is provided between the output and ground to overcome the effect of poor noise margin in the circuit. The implemented circuit is based on the pass transistor logic. The pre-layout simulation of the design is performed using the Cadence EDA tool of 180 nm standard CMOS technology. The proposed XNOR-AND cell element of comparator shows improvement in the number of transistors, area, and average power.

关键词： Semiconductor device modeling Power demand Tools CMOS technology Transistors Transient analysis Standards

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simulation and experimental research on the multi-band slot-loaded printed antenna

Simulation and experimental research on the multi-band slot-...

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International conference on Communication Technology (ICCT)

作者： Run-nan Cai Shu Lin Guan-long Huang Jin-xiang Wang School of Electronics and Information Engineering Harbin Institute of Technology Harbin China Electronic Science and Technology post-doctoral research center Harbin Institute of Technology Harbin China Department of Microelectronics Science and Technology Harbin Institute of Technology Harbin China

Slots which are parallel with the bottom side are loaded at the two equilateral sides of the monopole isosceles triangle printed antenna to achieve multi-band in the operating frequency. The antenna is simulated by CST MICROWAVE STUDIO®, a 3-dimentional full wave electromagnetic simulation software, the simulated results indicate that the central frequency of the pass-band, as well as the bandwidth and the number of the pass-band can be controlled by the slots' length and width, loading position and the number of the slots. The resonant frequencies have certain relation with parameters of the antenna structure, and the interaction between pass-bands is week. A monopole multi-band antenna synchronously operating in three pass-bands, 2.4/3.5/5.5 GHz, is designed and fed by coplanar waveguide. The simulated results also show that the antenna has omnidirectional radiation in H plane. Based on the simulation, prototype of the antenna is manufactured and measured. Finally, the measured results well match the simulated, which verify the design idea is feasible. The antenna size is just 27.74% of the corresponding wavelength of the first resonant frequency, and this compact antenna can be applied in WLAN and WiMAX systems.

关键词： Frequency measurement Load modeling Antennas Resonant frequency Microwave measurements Microwave communication

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Investigation on the Radiation Emission Characteristics of Printed Circuit Boards with Integrated Isolation Chip

Investigation on the Radiation Emission Characteristics of P...

引用

Electronic Information Engineering and Computer Technology (EIECT), International conference on

作者： Fang Liu Tianmeng Zhang Tianting Zhao Yiming Chen Yue Zhuo Jianyu Feng Mengjiao Li Jinchun Gao Beijing Smart-chip Microelectronics Technology Co. Ltd. Beijing China Beijing Key Laboratory of Work Safety Intelligent Monitoring Beijing University of Posts and Telecommunications Beijing China

ISBN: (数字)9798331528850

ISBN: (纸本)9798331528867

Isolation technology is widely used in high-low voltage transformation and long-distance transmission to effectively improve the reliability of the system. However, the imperfect design of the transformer inside the isolation chip may lead to an interference path between the primary and secondary coils of the transformer, which causes radiation emission. Accordingly, in this current work, the radiation emission characteristic of the printed circuit board (PCB) was investigated by simulation analysis and experimental tests. The main radiation sources in isolation chip were extracted, and the electromagnetic interference (EMI) radiation model was developed in electromagnetic simulation software to analyze the maximum radiation intensity of the PCB. A series of experimental tests are conducted to validate the electromagnetic field model. The results of this study provide a better understanding of the radiation emission characteristic of isolation chips and theorical support for improving the electromagnetic compatibility in the electronic system.

关键词： Coils Analytical models Printed circuits Electromagnetic interference Voltage Transformers Three-dimensional printing Numerical models Electromagnetic fields Integrated circuit modeling

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Fabrication and characterization of a 83 MHz high temperature /spl beta/-SiC MESFET operational amplifier with an AlN isolation layer on

Fabrication and characterization of a 83 MHz high temperatur...

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Device Research conference

作者： K.K. Diogu G.L. Harris A. Mahajan I. Adesida D.F. Moeller R.A. Bertram Materials Science Research Center of Excellence School of Engineering Howard University College of Medicine Washington D.C. DC USA Center for Compound Semiconductor Microelectronics University of Illinois Urbana IL USA MOS Digita-Analog Integrated Circuits Division Motorola Inc. Austin TX USA

Summary form only given. The fabrication of a high temperature analog integrated operational amplifier implemented in /spl beta/-SiC technology using depletion-only MESFETs is presented. The operational amplifier is implemented with 1 /spl mu/m gate geometries using direct write e-beam lithography to achieve high frequency operation. For the first time, compound MESFETs have been used as current sources and sinks at the various stages of the operational amplifier to provide high output impedance and hence increased circuit gain, while maintaining a reasonable unity gain frequency. Circuit design/simulation methods, circuit layout, device modeling, device parameter extraction methods and operational amplifier circuit fabrication techniques used to achieve excellent operational amplifier characteristics will be discussed in detail.

关键词： Fabrication Temperature Operational amplifiers MESFETs Frequency Geometry Lithography Impedance Circuit synthesis Circuit simulation

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A phase-shift compensation technique for radiation detection readout circuit to improve stability

A phase-shift compensation technique for radiation detection...

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2010 10th IEEE International conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Jing Li Ya-Cong Zhang Zhong-Jian Chen Department of Microelectronics Peking University Beijing 100871 China

Stability is a critical design issue for radiation detection readout circuit when high counting rate together with low power property is simultaneously required. In this letter a novel method which increases the phase margin of the pulse shaper is presented. A readout circuit using this compensation technique has been implemented in 0.35 urn CMOS technology. simulation and test results show that this method gives a significant improvement on stability margins. This readout circuit can process 1MHz injecting rate and provide a conversion gain of about 167.7mV/fC at the power consumption of 0.33mW.

关键词： Circuit stability Stability analysis Preamplifiers Integrated circuit modeling simulation Capacitance Power demand

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