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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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A new parameter extraction method for ultra-thin oxide SOI MOSFET's

A new parameter extraction method for ultra-thin oxide SOI M...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： O. Faynot S. Cristoloveanu P. McLarty C. Raynaud J. Gautier LETI (CEA-Technologies Avancées)-DMEL-CEN/G Grenoble France Laboratoire de Physique des Composants à Semiconducteurs (UA-CNRS) ENSERG Grenoble France Department Electrical and ComputerEngineering State University Raleigh NC USA

Parameter extraction stands as a critical issue for the modeling, simulation and design of CMOS transistors and circuits. Over the years, many methods have been proposed, refined and optimized until they became unable to account for new device characteristics brought about by technological progress. Such a situation applies to ultra-thin oxides, where the transconductance may exhibit negative values. The aim of this paper is: (1) to propose an adequate method for the extraction of the threshold voltage V/sub T/, field effect mobility /spl mu//sub 0/, effective channel length (L-/spl Delta/L), gate-induced mobility attenuation factors /spl theta//sub 1,2/; and (2) to demonstrate its superiority over standard techniques used in thicker oxides (>10 nm). Our test devices were n-channel (partially and fully depleted) SOI MOSFET's with silicon thicknesses ranging from 30 to 150 nm, with LDD configuration and various gate oxides from 4.5 to 17.5 nm thick. The device width was 25 /spl mu/m and the gate length varied from 0.4 to 25 /spl mu/m.

关键词： Parameter extraction Semiconductor device modeling Circuit simulation MOSFETs Optimization methods CMOS technology Transconductance Threshold voltage Attenuation Testing

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Mechanical modeling study for fan-out wafer level package parameters to enhance BGA TCoB life

Mechanical modeling study for fan-out wafer level package pa...

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Electronics Packaging Technology conference (EPTC)

作者： Rathin Mandal Chai Tai Chong Institute of Microelectronics 2 Fusionopolis Way #08-02 Innovis Singapore

ISBN: (纸本)9781665416207

Fan-Out Wafer Level Package (FOWLP) is experiencing a significant growth due to its thinner thickness, higher I/Os in smaller chip area, better thermal and electrical performance. Due to the shorter, finer and simpler interconnection as compare to flip chip, FOWLP shows superior performance. On the other hand this package is vulnerable due to its higher warpage and package stress concentration. This paper will explore different options to enhance board level reliability performance during temperature cycling for FOWLP. The mechanical simulation has been performed for board level temperature cycling reliability test on a uniform ball pitch, with/without UBM (under bump metallization), BGA with underfill, SACQ (bismuth bearing SnAgCu alloy) solder material and different package design factors (pad diameter, solder resist opening, silicon chip thickness, BGA height, etc). Our aim from this mechanical simulation is to find ways to enhance TCoB (temperature cycling on board) solder joint life performance for FOWLP to be used for antenna-in-package (AiP) automotive radar application. Among the different package parameters, UBM, SACQ solder, solder resist opening and larger BGA height are the few packaging parameters which significantly enhancing the BGA solder joint life. The most noticeable factor bismuth bearing SACQ shows more than 2x performance improvement whereas underfilling the BGA layer in the FOWLP package reduces solder join life significantly.

关键词： Semiconductor device modeling Temperature Thermomechanical processes Resists Bismuth Reliability engineering Silicon

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designing a New Biological Function in Synthetic Biology

Designing a New Biological Function in Synthetic Biology

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2011 2ND International conference on Innovative Computing and Communication and 2011 Asia-Pacific conference on Information Technology and Ocean Engineering(CICC-ITOE 2011)

作者： Qun Wei Chemical Engineering Institute Northeast dianli University

Synthetic biology is a science resulting from the connection between biotechnology and engineering sciences. It aims to design and build new biological systems and *** this paper, models of biologic gates using different abstraction levels have been presented. For each kind of model, its advantages and drawbacks were discussed. The high-level model will be used during the first step of the design to validate the concept. It allows fast simulation, even for big systems, and can be completed by mathematical tools in order to automatism the process. An intermediate model, using templates(like in microelectronics), gives some indications about concentration and timing which allows to validate a system in a worst- case situation without complex simulations. Finally, the low- level model, which uses biological ODEs, can be used to predict accurately the timedependent evolution of protein concentration in the cell. Two types of low-level model are presented: the signal flow model, which consists in explicit ODEs and the conservative model which is based on implicate ODEs coming from matter conservation principle. For the latter, we developed a formalism that permits to represent a biological mechanism by an electronic circuit using voltage and current sources, resistances and capacities.

关键词： Index Terms—Biological Function Synthetic Biology modeling

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A comparative study of stress-based and fracture mechanics-based finite element simulation approaches for RDL based wafer level package

A comparative study of stress-based and fracture mechanics-b...

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Electronics Packaging Technology conference (EPTC)

作者： Sasi Kumar Tippabhotla Lin Ji Tai Chong Chai Institute of Microelectronics A*STAR (Agency for Science Technology and Research) 2 Fusionopolis Way Innovis Tower A Singapore

ISBN: (纸本)9781665416207

Conventional stress analysis (CSA) and fracture mechanics using cohesive zone modelling (CZM) approaches are currently available in the finite element analysis framework for virtual design evaluation of microelectronic packages. CSA exists for a long time and the CZM is currently being adopted widely, especially by the universities and R&D institutes. Both the approaches have their own advantages and challenges. In this scenario, a comparison of relative merits and limitations need to be evaluated to make efficient use of both the approaches in the package development process. Such a comparison aids the simulation engineers to gage the requirements of each approach and plan an affordable simulation strategy while maximizing the output. In this study we present a comparative evaluation of CSA approach and fracture mechanics approach using CZM for design evaluation of a simple fan-out wafer level package. We show the requirements (mechanical properties and mechanical and fracture strength details of materials) and merits (prediction capabilities) of both the approaches and thus gauge their viability and suitability for different design stages. We also show the specific advantages and challenges of CZM approach. We conclude that the CZM method enhances the virtual product development process through its capability of predicting the likeliness of delamination and damage. However, this approach has the prerequisite of fracture properties of the material interfaces. The initial (conceptual/preliminary) development phases of a new package require evaluation of a large number of candidate materials, processes and designs and the fracture strength (interface/bulk) data for all the material/process combinations are seldom available. The CSA approach is more suitable for such situation to narrow down the product parameters by comparative analysis. The candidate designs thus narrowed down can be simulated using CZM approach to evaluate the likeliness of delamination and modific

关键词： Semiconductor device modeling Analytical models Temperature Systematics Product development Finite element analysis Delamination

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Thermal modelling, characterization and optimization of 2.5D heterogeneous integrated platform for RF front end

Thermal modelling, characterization and optimization of 2.5D...

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Electronics Packaging Technology conference (EPTC)

作者： Haoran Chen Teck Guan Lim Gongyue Tang System in Package Institute of Microelectronics A*STAR Singapore Singapore

ISBN: (纸本)9798350398861

This paper studies the thermal characteristics of a compact 2.5D heterogeneous integrated platform by numerical simulation. The platform contains a silicon interposer carrying high-density power amplifiers made of gallium nitride on silicon carbide (GaN-on-SiC) and temperature sensitive passive filter dies. Comparing with traditional wire bonding method, the flip chip method suspended by metal stub enjoys greater benefits on RF performance. However, thermal issue becomes more challenging in this configuration due to the improper thermal transferring path. This work numerically studies the metal casing as a cooling solution and explores the potential capabilities in 2.5D heterogeneous integrated platform based on a full-scale 3D finite element model. Temperature distributions across the package in different conditions are presented to reveal the effect of the casing. And the parametric study results guide the thermal design of such casing in practice. The information in this paper could be helpful in the thermal design of 2.5D heterogeneous integrated platform for RF front end.

关键词： Radio frequency Solid modeling Three-dimensional displays Cooling Parametric study Wires Metals

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LSTM-RNN Based Analog IC Automated Sizing Model for Operational Amplifier and VCO

LSTM-RNN Based Analog IC Automated Sizing Model for Operatio...

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International conference on Integrated Circuits and Microsystems (ICICM)

作者： Zihan Yang Wensi Wang Zhijie Chen Qianhui Fan Xuanchong Chen College of Microelectronics University of Technology Faulty of Information Technology Beijing Beijing China

ISBN: (数字)9781728189789

ISBN: (纸本)9781728189796

Artificial intelligence and machine learning have been widely used to replace human work. Analog integrated circuit design needs to adjust a large number of circuit parameters to satisfy the balance between various performance metrics, which now mostly rely on the experience of designers and sometimes of the intuitions. Machine learning has demonstrated the potential to aid the design of analog integrated circuits in the literature, whilst most of them adopted particle swarm intelligence and Bayesian optimization. However, the model training time and simulation run time are substantial when any circuit structure modification occurs. In this paper, Recurrent Neural Network (RNN) was used to automatically optimize the parameters sizing by giving requested performance. Training data sets for the RNN of component parameters and circuit performance were simulated using Cadence Spectre. After training for only 15 minutes, RNN learns to predict parameters by inputting gain, bandwidth, power and frequency, which can make critical circuit design decision significantly faster. The reliability and applicability of the algorithm was verified through the parameter prediction of integrated operational amplifier and VCO.

关键词： Training Recurrent neural networks Integrated circuit modeling Neural networks Optimization Logic gates Deep learning

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Flexible system model and architectural exploration for HIPERLAN 2 DLC wireless LAN protocol

Flexible system model and architectural exploration for HIPE...

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IEEE International conference on Communications (ICC)

作者： V. Nema B.V. Poucke M. Glassee S. Vernalde Interuniversity Microelectronics Center (IMEC) Leuven Belgium Interuniversitair Micro-Elektronica Centrum Leuven Vlaams-Brabant BE IMEC Leuven Belgium

Modern wireless communication protocols like HIPERLAN 2, IEEE 802.11a etc. support high data rates of the order of 54 Mbps and have strict timing requirements. Although protocols define the communication rules, they do not address critical design issues like hardware/software (HW/SW) partitioning and the implementation of different algorithms, which have a critical impact on the system performance. We have developed a platform independent flexible system model based on the HIPERLAN 2 data link control (DLC) protocol that allows easy experimenting with HW/SW partitioning and different algorithms. Our design methodology allows performance evaluation at the system level as well as path to HW/SW implementation. The simulation results presented give good information on the computational complexity of different components and on the HW/SW partitioning of the HIPERLAN 2 DLC layer. The HW/SW partitioning results have been verified with a working demonstrator and the object oriented model can be easily extended for future protocols.

关键词： Wireless LAN Wireless application protocol Object oriented modeling Partitioning algorithms Wireless communication Timing Algorithm design and analysis Hardware Communication system software Software performance

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Pragmatic approaches to implement self-checking mechanism in UVM based TestBench

Pragmatic approaches to implement self-checking mechanism in...

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International conference on Advances in Computer Engineering and Applications (ICACEA)

作者： Raghav Madan Nishant Kumar Sujay Deb ECE IIIT-Delhi Delhi India ST Microelectronics Greater Noida India

ISBN: (纸本)9781467369121

Functional Verification of today's highly complex designs cannot rely simply on static verification techniques as these techniques are incapable of verifying modern complex digital designs. However, simulation-Based Verification (SBV) which comes under dynamic verification approach can handle these complex systems. Among the various modern SBV approaches, Universal Verification Methodology (UVM) provides well established and flexible solution for complex system design verification. Flexibility of UVM lies in the fact that the verification environment developed using UVM consists of reusable components and is supported by tools of all major vendors of the industry. UVM provides a complete framework to achieve coverage driven verification that includes automatic test generation, self-checking testbenches and coverage metrics [1]. The self-checking capability provided by UVM is not very well defined and, hence, forces verification engineer to develop complex checking mechanism even for very small designs and also provides less resources for thorough checking of complex designs. In this paper, we will discuss implementation details of different kind of checking mechanisms that can be used along with UVM based verification environment to improve its capability of functional checking, protocol checking and reaching hidden bugs of the design Under Verification (DUV).

关键词： Monitoring Ports (Computers) Computational modeling Protocols Hardware design languages IP networks Computers

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Laser attacks on integrated circuits: From CMOS to FD-SOI

Laser attacks on integrated circuits: From CMOS to FD-SOI

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International conference on design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Jean-Max Dutertre Stephan De Castro Alexandre Sarafianos Noémie Boher Bruno Rouzeyre Mathieu Lisart Joel Damiens Philippe Candelier Marie-Lise Flottes Giorgio Di Natale ENSM.SE Centre Microlectronique de Provence-Georges Charpak France ST Microelectronics Avenue Clestin Coq France STMicroelectronics LIRMM (CNRS UMR N5506) France

The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model permitted us to draw the laser sensitivity map of a SRAM cell. It demonstrates a very close correlation with experimental measures. We also introduce the preliminary results we gathered to build a similar electrical model for FD-SOI circuits. FD-SOI technology is expected to be less sensitive to laser than CMOS.

关键词： Semiconductor lasers Laser modes Transistors Integrated circuit modeling Photoconductivity Junctions Measurement by laser beam

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SPICE modelling of a valley switching flyback power supply controller for improved efficiency in low cost devices

SPICE modelling of a valley switching flyback power supply c...

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IEEE International conference on Circuits and Systems (ICCAS)

作者： Vishnu P. Nambiar Azli Yahya Thayala R. Selvaduray Microelectronics & Computer Engineering Department Universiti Teknologi Malaysia Johor Bahru Malaysia Panaron Sdn. Bhd. Kuala Lumpur Malaysia

The flyback switching mode power supply (SMPS) circuit is undoubtedly the most popular topology currently in low power applications, due to its low cost and simple structure. In the past, there have been many proposed optimizations to flyback designs utilising various techniques such as zero voltage switching (ZVS), active clamping, synchronous rectification, and more. However, most of these designs complicate the original snubbed structure of the flyback topology, and increases its cost. This paper presents the evaluation of a variable-frequency, soft-switching, snubbed, DC/DC flyback converter that utilizes valley switching for improving efficiency. The flyback controller is modelled using SPICE, and uses pulse skipping to maintain the equilibrium of the system based on the feedback from the output. simulation models report up to 92.2% efficiency, which is almost comparable to ZVS and active clamping topologies. The main advantage of this design is the use of only a single switching transistor, with no additional inductors, correctional circuitry, or clamping action, thus guaranteeing a low cost design.

关键词： Switches Pulse width modulation Integrated circuit modeling SPICE Zero voltage switching Clamps MOSFETs

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