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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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An efficient relaxation based DIPIE algorithm for computer aided design of electrostatic actuators

An efficient relaxation based DIPIE algorithm for computer a...

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IEEE International conference on Micro Electro Mechanical Systems

作者： O. Bochobza-Degani D. Elata Y. Nemirovsky Electrical Engineering Department Kidron Microelectronics Research Center Haifa Israel Mechanical Engineering Department Haifa Israel

ISBN: (纸本)0780371852

Pull-In parameters are important properties of electrostatic actuators. Efficient and accurate analysis tool that can capture these parameters for different design geometries, are therefore essential. Current simulation tools approach the Pull-In state by iteratively adjusting the voltage applied across the actuator electrodes. The convergence rate of this scheme gradually deteriorates as the Pull-In state is approached. Moreover, the convergence is inconsistent and requires many mesh and accuracy refinements to assure reliable predictions. As a result, the design procedure of electrostatically actuated MEMS devices can be time-consuming. In this paper a novel Displacement Iteration Pull-In Extraction (DIPIE) scheme is presented. The DIPIE scheme is shown to converge consistently and far more rapidly than the voltage iterations (VI) scheme (>100 times faster!). A relaxation based DIPIE scheme that requires separate mechanical and electrostatic field solvers is suggested. Therefore, it can be easily implemented into existing MOEMS CAD packages. Moreover, using the DIPIE scheme, the Pull-In parameters extraction can be performed in a fully automated mode, and no user input for search bounds is required.

关键词： Voltage Convergence Iterative algorithms Electrostatic actuators Geometry Computational modeling Electrodes Microelectromechanical devices Packaging Parameter extraction

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LEDs Lifetime Prediction modeling: Thermomechanical simulation for SAC305 and SAC105

LEDs Lifetime Prediction Modeling: Thermomechanical Simulati...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Mohd Zubair Akhtar Maximilian Schmid Andreas Zippelius Gordon Elger Technische Hochschule Ingolstadt Esplanade 10 Ingolstadt

The challenge of predicting the reliability of solder joints in high-power LED packages by Finite Element Analysis (FEA) is crucial for the automotive industry. Focusing on the thermo-mechanical stresses between LED package and the PCB, i.e. the aluminum insulated metal substrate (Al-IMS), this paper analyzes the crack formation in the solder joints for seven different ceramic-based LED packages. The model is validated by data from a large experimental study, covering typical two pad and three pad footprint design for LED package and five solder materials. The data set contains experimental data of nearly 1,800 LED packages, including over 40,000 Transient Thermal analyses (TTA) and 9,000 Scanning Acoustic Microscopy (SAM) measurements. The paper investigates different post-processing approaches related to FEA simulations for surface-mounted devices (SMD) LED assemblies, recognizing the limitations of approaches used for Ball Grid Array (BGA) packages due to the large difference in geometry and pad layout. The primary goal of the FEA model is to correctly predict the reliability of different pad designs, i.e. two or three pad footprints for different solders and develop the universal lifetime model. The methodology includes detailed thermomechanical simulations via Ansys. The paper compares the behavior of SAC305 and SAC105. Each LED package undergoes five thermal cycles, ranging from $- 40^{\circ}\mathrm{C}$ to $125^{\circ}\mathrm{C}$, to assess accumulated creep strain. The Coffin Manson model is utilized for the lifetime prediction of the solder joint. To the best of the author’s knowledge, the paper presents for the first time a model which is validated for different pad designs and answers the question: Is a three-pad or a two-pad preferable for solder joint reliability? The results show a good agreement, i.e. $\mathrm{R}^simulation=96$% for critical path averaging, of simulation outcomes for ceramic LED packages with thick film metallization. However, some variabilit

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A MEMS resonator tank for an RF VCO application

A MEMS resonator tank for an RF VCO application

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IEEE International conference on Electronics, Circuits and Systems (ICECS)

作者： Daniel Zammit Owen Casha Ivan Grech Edward Gatt Joseph Micallef Department of Microelectronics and Nanoelectronics University of Malta Msida Malta

This paper presents the design and study of a MEMS tapped-inductor LC resonator tank, proposed to evaluate the improved performance over that generally achieved in standard CMOS passive component integration. The resonator tank, consisting of a fixed-value inductor and a variable capacitor, was implemented in the MetalMUMPs process and was targeted for a VCO intended for telemetry applications. A geometrically optimized 1.25 nH horseshoe inductor was designed and results show that it exhibits a Q-factor of 63 at 7.3 GHz and a self-resonating frequency of 17.6 GHz. In addition, an improved π-inductor model is proposed for design and simulation purposes. The variable capacitor was designed in a parallel-plate topology, using four serpentine springs. The capacitance can be varied from 0.183 pF to 0.245 pF with an actuation voltage in the range of 0 V-to-11.7 V. A Q-factor of 62 at 1.1 GHz and a self-resonating frequency above 10 GHz were achieved. The designed inductor and capacitor were configured in a resonator tank topology yielding an overall Q-factor of 22 at 4.9 GHz.

关键词： Inductors Q-factor Micromechanical devices Capacitors Substrates Integrated circuit modeling Voltage-controlled oscillators

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Applied modeling Framework in Integrated Circuit design and Reliability

Applied Modeling Framework in Integrated Circuit Design and ...

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Electronic Components and Technology conference (ECTC)

作者： Papa Momar Souare Cedrick Bouchard Eric Duchesne James Zaccardi David Pettit Francois Vachon Advanced Packaging &amp Modeling IBM Systems Bromont Canada Semiconductor Packaging Engineer Manager Viasat Inc RF / Microwaye Viasat Inc Business Development Manager IBM Systems Bromont Canada

A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure modes in microelectronics packaging such as module warpage, solder fatigue cracking, TIM tearing or delamination and underfill corner cracking causing chip circuits delamination and increased flip chip solder joint fatigue. The numerical simulations were performed using a specialized cloud software infrastructure named PACK using a one-way macro to micro model approach. Model validation was split into two main aspects. First, the linear behavior of the macro model was based on bottom surface metallurgy (BSM) warpage. BSM module warpage of several packages from ICOS data was used to validate the numerical model, and both room temperature warpage as well as the shape predicted by the FEM model agreed with the ICOS data. Second, the fatigue modeling accuracy was evaluated based on data issued from devices built and subjected to thermal cycles akin to the models. The non-linear simulation of creep was then performed using Norton’s creep model, using SAC material properties obtained from experimental sources. The strain energy density (SEND) was used as a metric to quantify solder creep and interconnect fatigue. The SEND was averaged over a few layers of elements at the top and bottom of the interconnects, forming a normalized volume where creep (and failure probability) was the highest. Early thermal cycles solder fatigue fails were detected electrically on the prototypes, located on the memory module’s corners. These observations were confirmed with dye and pry which corresponded with the computed SEND map and distribution given by the numerical model. Failure analysis (FA) showed that cracks initiated near the bottom side pad neck and propagating along the BGA which was also in agreement with the modeled metric’s distribution across critical BGAs. Finally, l

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D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in Large-Scale M3D 2TOC DRAM Bit Cell Evaluation via Statistical modeling Methodology

D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in L...

引用

International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yue Zhao Yong Yu Jingrui Guo Lingfei Wang Nan Yang Jianpeng Jiang Yanan Lu Menglong Zhou Shijie Huang Lihua Xu Zhenhua Wu Guanhua Yang Di Geng Guilei Wang Bryan Kang Chao Zhao Ling Li Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China Beijing Superstring Academy of Memory Technology Beijing China

ISBN: (数字)9798331516352

ISBN: (纸本)9798331516369

Device nonuniformity of ultra-scaled novel vertical a-IGZO-FETs is induced by multi-sources, such as dimension variation and material disorder, limiting large-scale DRAM design. Particularly, fluctuation of disorders in an amorphous channel exhibits a great impact on density of states (DOS) contributing to statistical effects on gate controllability and transport mechanisms. To clarify this issue, TCAD simulations are conducted by adjusting geometric dimensions and DOS, and corresponding statistical characteristics (e.g., on-voltage and on-current etc.) are extracted from up to 80 samples of down to channel length of 50nm. Such effects are further incorporated into a surface-potential based physics compact model via calibration to experiments. Using this model, the vertical a-IGZO-FET-based 2TOC DRAM is firstly investigated with the statistical analysis of Write/Read performances, supporting device variation aware DTCO flow of future extremely large-scale and high-density M3D memory.

关键词： Semiconductor device modeling Performance evaluation Solid modeling Analytical models Statistical analysis Random access memory Feature extraction Semiconductor process modeling Device-to-device communication Three-dimensional integrated circuits

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A methodology for modeling embedded processors for architecture exploration

A methodology for modeling embedded processors for architect...

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International conference on microelectronics, ICM

作者： Ahmed Elhossini Shawki Areibi Robert Dony School of Engineering University of Guelph Guelph Canada

Architecture exploration for embedded systems is becoming an indispensable tool for System-on-Chip designers. This process requires the evaluation of many architectures that are generated during the exploration process. The evaluation process has a significant impact on the quality of the results and could consume a substantial amount of CPU time. Accordingly, the evaluation process should provide enough accuracy to guide the optimization process to promising points in the design space in reasonable time. In this paper an efficient approach for performance evaluation of embedded systems is proposed. Several cycle-accurate simulations are performed for commercial embedded processors used in our study. The simulation results are used to build Artificial Neural Network (ANN) models with accuracy up to 90% compared to cycle-accurate simulations with a very significant time saving.

关键词： Program processors Artificial neural networks Accuracy Power demand Training Computer architecture Benchmark testing

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Lead-free solder material characterization for thermo-mechanical modeling

Lead-free solder material characterization for thermo-mechan...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Edith S. W. Poh W. H. Zhu X. R. Zhang C. K. Wang Anthony Y. S. Sun H. B. Tan Packaging Analysis & Design Center United Technologies Research Center Inc. Singapore Singapore

Systematic mechanical characterization has been done on lead-free solder alloys, i.e., SAC105, SAC205, SAC305, SAC105Ni0.02, and SAC105Ni0.05 as promising alternatives of SnPb solder. Solder joints in service stay in high homologous temperatures that have profound effects on mechanical properties such as creep and the apparent elastic modulus. Mechanical deformation behaviors of bulk solder alloys at temperatures between 298 K and 398 K, as well as strain rates between 10 -5 to 10 -1 under isothermal conditions, have been studied for the above 5 solder alloys with a designed bulk test vehicle. Isostress loading conditions on the solders were also conducted to study creep behaviour. Based on substantial experimental measurement results, the elastic modulus, yield stress and UTS of the various SAC solder alloys show direct relationships with Ag content at temperatures between 298 K and 398 K. The relationships of strain rate, temperature, Ag content and material properties were developed and material constants are presented. Basic material parameters with viscoplastic constitutive relations for solders encompassing temperature and strain rate dependence have been obtained through curve fitting with experimental data. The creep constitutive model has also been established. By implementing the developed creep or viscoplastic constitutive models of solders into FEA models, the life of an electronic package under thermal cycling and drop performance in board level tests can be evaluated. Material compositions such as Ag content and Ni dopant effect are also studied for their influence on mechanical properties. It was reported that Ni dopant could improve solder joint drop performance by changing the microstructure of the material.

关键词： Environmentally friendly manufacturing techniques Lead Thermomechanical processes Temperature Creep Semiconductor process modeling Soldering Mechanical factors Capacitive sensors Strain measurement

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A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper)

A Method of Estimating FD Capacitance with Large Size Photod...

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IEEE International conference on Integrated Circuits, Technologies and Applications (ICTA)

作者： Chao Gu Zhenhua Guo Shuangming Yu Liyuan Liu Jian Liu Peng Feng Nanjian Wu State Key Laboratory of Superlattices and Microstructures Institute of Semiconductors Chinese Academy of Sciences Beijing China School of Microelectronics University of Chinese Academy of Sciences Beijing China Center of Materials Science and Optoelectronics Engineering University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9781728180328

ISBN: (纸本)9781728180335

This work proposes a simple method of calculating FD capacitance in 2-dimensional (2D) TCAD simulation that combines with pixel layout, simplifying the estimation of CIS FD design. Approximate per unit FD junction capacitance can be extracted by few TCAD simulations. This method has been verified using an image sensor chip with 10um-size pixel fabricated in 180nm CIS process. The testing results show that the error percentage of FD capacitance between test and calculation is approximately 5.90%.

关键词： Image sensors Two dimensional displays Layout Photodiodes Integrated circuit modeling Testing Parasitic capacitance

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Fabrication and characterization of a 83 MHz high temperature /spl beta/-SiC MESFET operational amplifier with an AlN isolation layer on

Fabrication and characterization of a 83 MHz high temperatur...

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Device Research conference

作者： K.K. Diogu G.L. Harris A. Mahajan I. Adesida D.F. Moeller R.A. Bertram Materials Science Research Center of Excellence School of Engineering Howard University College of Medicine Washington D.C. DC USA Center for Compound Semiconductor Microelectronics University of Illinois Urbana IL USA MOS Digita-Analog Integrated Circuits Division Motorola Inc. Austin TX USA

Summary form only given. The fabrication of a high temperature analog integrated operational amplifier implemented in /spl beta/-SiC technology using depletion-only MESFETs is presented. The operational amplifier is implemented with 1 /spl mu/m gate geometries using direct write e-beam lithography to achieve high frequency operation. For the first time, compound MESFETs have been used as current sources and sinks at the various stages of the operational amplifier to provide high output impedance and hence increased circuit gain, while maintaining a reasonable unity gain frequency. Circuit design/simulation methods, circuit layout, device modeling, device parameter extraction methods and operational amplifier circuit fabrication techniques used to achieve excellent operational amplifier characteristics will be discussed in detail.

关键词： Fabrication Temperature Operational amplifiers MESFETs Frequency Geometry Lithography Impedance Circuit synthesis Circuit simulation

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A phase-shift compensation technique for radiation detection readout circuit to improve stability

A phase-shift compensation technique for radiation detection...

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2010 10th IEEE International conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Jing Li Ya-Cong Zhang Zhong-Jian Chen Department of Microelectronics Peking University Beijing 100871 China

Stability is a critical design issue for radiation detection readout circuit when high counting rate together with low power property is simultaneously required. In this letter a novel method which increases the phase margin of the pulse shaper is presented. A readout circuit using this compensation technique has been implemented in 0.35 urn CMOS technology. simulation and test results show that this method gives a significant improvement on stability margins. This readout circuit can process 1MHz injecting rate and provide a conversion gain of about 167.7mV/fC at the power consumption of 0.33mW.

关键词： Circuit stability Stability analysis Preamplifiers Integrated circuit modeling simulation Capacitance Power demand

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