In this paper, a methodology for the design of microelectronic systems which include hardware and software for open-loop and closed-loop control will be presented. An integrated approach to specification and design, a...
详细信息
In this paper, a methodology for the design of microelectronic systems which include hardware and software for open-loop and closed-loop control will be presented. An integrated approach to specification and design, analysis and simulation of the overall system has been developed. This provides for a systematic, computer aided approach to requirements definition, specification and design as well as verification and validation of the results. As embedded systems often require real-time capabilities, the environment presented gives special consideration to these constraints. For verification purpose of the developed design and specification methodology a software prototype has been implemented and used in concrete example applications, which is also presented in this paper.
Summary form only given. Recent work has clearly revealed that transient current in the parasitic bipolar junction transistor (BJT) of the floating-body SOI MOSFET can be significant and degrading even in SOI circuits...
详细信息
Summary form only given. Recent work has clearly revealed that transient current in the parasitic bipolar junction transistor (BJT) of the floating-body SOI MOSFET can be significant and degrading even in SOI circuits operating at voltages well below the BJT-defined drain-source breakdown. The BJT is also critically important with regard to soft errors in low-voltage SOI memory circuits. In these cases, the BJT current is driven by dynamic charging of the body and concomitant forward biasing of the source (or drain) junction, supported by capacitive, or charge coupling between the BJT and the MOSFET. A reliable circuit model for the floating-body SOI MOSFET must therefore account for the coupled BJT. In this paper we present a new, quasi-2D parasitic BJT model physically coupled to the SOISPICE MOSFET models and defined in terms of their parameters. We further use physical insight derived from this BiMOS modeling to identify a new means of controlling the transient BJT, or leakage current in SOI MOSFETs which could be exploited in design.
This paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data...
详细信息
This paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit difficult to be synthesized by a single HLS tool. The combination of two HLS tools for the high-level design of this operator required the definition of a sophisticated design flow allowing mixed-level and multi-language simulations. When compared to design starting from RTL specifications, HLS induces only a negligible area overhead of 5%, and provides gain in description length (divided by 5), design time and flexibility.
A one-dimensional CAD-oriented SOI MOSFET model continuous over all regions of operation is described. This model is valid for long and short channel fully depleted devices. In addition, the NQS nature of the charge r...
详细信息
A one-dimensional CAD-oriented SOI MOSFET model continuous over all regions of operation is described. This model is valid for long and short channel fully depleted devices. In addition, the NQS nature of the charge redistribution is implicitly accounted for, without using any empirical partition of the channel charge. The physical and numerical foundation of our model is first described. In a second part, we propose a quantitative comparison between our modeling approach and two-dimensional device simulation. A circuit application is given in a third part. Finally, current memory cells (a circuit particularly sensible to charge injection) are simulated with this new model.
This paper describes the circuit modeling techniques to predict on-chip simultaneous switching noise for high performance SOI circuits. The analysis includes both the inductive /spl Delta/I noise on the package level ...
详细信息
This paper describes the circuit modeling techniques to predict on-chip simultaneous switching noise for high performance SOI circuits. The analysis includes both the inductive /spl Delta/I noise on the package level and the resistive I R drop on the chip level. By identifying the hot spots on the chip and /spl Delta/V across the chip, designers can optimize the placement of on-chip decoupling capacitors and effectively minimize the switching noise for SOI chips.
Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Au...
详细信息
Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses LANCELOT, a large-scale nonlinear optimization package with an augmented Lagrangian formulation. Simple bounds are handled explicitly and trust region methods are applied to minimize a composite objective function. In the inner loop of the optimization, the fast circuit simulator SPECS is used to evaluate the circuit. SPECS is unique in its ability to efficiently provide time-domain sensitivities, thereby enabling gradient-based optimization. Both the adjoint and direct methods of sensitivity computation have been implemented in SPECS. To assist the user, interfaces in the Cadence and SLED design systems have been constructed.
Summary form only given. The fabrication of a high temperature analog integrated operational amplifier implemented in /spl beta/-SiC technology using depletion-only MESFETs is presented. The operational amplifier is i...
详细信息
Summary form only given. The fabrication of a high temperature analog integrated operational amplifier implemented in /spl beta/-SiC technology using depletion-only MESFETs is presented. The operational amplifier is implemented with 1 /spl mu/m gate geometries using direct write e-beam lithography to achieve high frequency operation. For the first time, compound MESFETs have been used as current sources and sinks at the various stages of the operational amplifier to provide high output impedance and hence increased circuit gain, while maintaining a reasonable unity gain frequency. Circuit design/simulation methods, circuit layout, device modeling, device parameter extraction methods and operational amplifier circuit fabrication techniques used to achieve excellent operational amplifier characteristics will be discussed in detail.
The proceedings contains 129 papers. Topics discussed include CMOS technology, microsystems, shear stress sensors, physics and technology of thin film devices, optical effects in compound semiconductors, optoelectroni...
详细信息
The proceedings contains 129 papers. Topics discussed include CMOS technology, microsystems, shear stress sensors, physics and technology of thin film devices, optical effects in compound semiconductors, optoelectronic devices, analog circuit design, computer aided design, mathematical modeling and simulation, reliability and characterization of CMOS devices, digital circuit design and technologies, solid state devices, power devices and integrated circuits, video circuits, and microprocessors.
With the decreasing device dimensions, faster switching speed, tighter design margin, and larger circuit sizes, deep-submicron MOSFET modeling has become more challenging and difficult to develop than ever. This paper...
详细信息
With the decreasing device dimensions, faster switching speed, tighter design margin, and larger circuit sizes, deep-submicron MOSFET modeling has become more challenging and difficult to develop than ever. This paper describes recent activities and trend in MOSFET modeling. Both the DC and AC aspects of MOSFET models are covered. Due to the more stringent requirements, test procedures for both analog and digital applications have been proposed. Existing SPICE models are evaluated against these tests. In particular, BSIM3 and MOS9, the two mostly discussed candidates for the standard deep-submicron MOSFET model, are compared.
The proceedings contains 73 papers. Topics discussed include intelligent data communications, international standard for quality, modeling and power electronics, logic support analysis, analog and digital interdomain ...
详细信息
The proceedings contains 73 papers. Topics discussed include intelligent data communications, international standard for quality, modeling and power electronics, logic support analysis, analog and digital interdomain concerns in integrated circuits, object oriented paradigm, reengineering, simulation for design. VLSI design with VHDL and synthesis, applied decision analysis, electrifying Puget sound transportation, high speed analog integrated circuits, system engineering, electric vehicles and software piracy.
暂无评论