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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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EMIB Packages simulation for Heterogeneous Integration of GaN and Si High-Power Devices

EMIB Packages Simulation for Heterogeneous Integration of Ga...

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International conference on (ICEPT) Electronic Packaging Technology

作者： Nana Pan Ziyu Liu Yudi Ju Han Jiang Yun Yin Qingqing Sun Lin Chen School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798350353808

ISBN: (纸本)9798350353815

Serving as a high-bandwidth, low-latency, and low-power solution for die-to-die communication, Embedded Multi-die Interconnect Bridge (EMIB) enables selective high-density electrical connections between heterogeneous dices in the same package. In this paper, a three-dimensional finite element model of an EMIB package is developed for the heterogeneous integration of GaN and Si high-power chips. ANSYS simulation software is used and the model is analyzed for its thermal dissipation under forced air cooling condition. For the electrical properties, the experimental design variables are stack position, line width, line spacing, and substrate materials with different dielectric constants to investigate their effect on crosstalk and insertion loss. Also, characterized by the eye diagram quality, impact of trace length on signal transmission is researched, which helps optimize the location of two heterogeneous chips for thermal management. According to the simulation results, under the condition of ensuring enough height of eye diagram (0.6Vpp), the temperature of GaN chip can be controlled within 124.8 $^\circ \mathrm{C}$ , and the temperature of silicon chip within $45.4^{\mathrm{o}}\mathrm{C}$ , both of which have power density of 166 $\text{GW}/\mathrm{m}^{3}$ and 13 $\text{GW}/\mathrm{m}^{3}$ , respectively.

关键词： Temperature Atmospheric modeling Wires Multichip modules Dielectric losses Bridge circuits Electronic packaging thermal management

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design and experiment of a high gain axial-mode helical antenna

Design and experiment of a high gain axial-mode helical ante...

引用

International conference on Communication Technology (ICCT)

作者： Run-nan Cai Shu Lin Li-na Wang Jin-yue Wang Yue-long Lü Guan-long Huang Jing-hui Qiu Jin-xiang Wang School of Electronics and Information Engineering Harbin Institute of Technology Harbin China Electronic Science and Technology post-doctoral research center Harbin Institute of Technology Harbin China Department of Microelectronics Science and Technology Harbin Institute of Technology Harbin China

A high gain axial-mode helical antenna with parasitic element is proposed. A metal wafer is used as parasitic element, loaded in the front of general axial-mode helical antenna to achieve the aim of improving antenna gain. The diameter of the wafer and the distance between the wafer and the end of the helical wire, which can influence the antenna characteristics, are both simulated and optimized by CST Microwave Studio ® , a 3-dimentional full wave electromagnetic simulation software. Prototype of the proposed antenna is manufactured according to the optimal simulated results and measured in the microwave anechoic chamber. Compared with general antennas, both the simulated and measured results indicate that the helical antenna with parasitic element can boost 0.8dB in gain under the circumstance of increasing 8.3% of the antenna axial length. In addition, this antenna can achieve the band 2.1-2.7GHz in its operating bandwidth, and the maximum axial ratio is up to 1.3dB in pass-band, which is not subject to the impact of parasitic element. The proposed antenna can applied in WLAN systems.

关键词： Semiconductor device modeling Correlation Atmospheric modeling Software Reflector antennas

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Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging

Frequency Domain Methodology for Evaluating Signal Integrity...

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Electronics Packaging Technology conference (EPTC)

作者： Li Kangrong Mihai Dragos Rotaru Institute of Microelectronics ASTAR Singapore

ISBN: (数字)9781728189116

ISBN: (纸本)9781728189123

A novel methodology to evaluate the signal integrity (SI) performance of logic to logic and high bandwidth memory (HBM) interconnect model for chiplet packaging is proposed. Compared with the traditional S parameters and eye diagram analyses, the proposed methodology reflects the actual SI performance under the capacitive termination condition, takes much shorter simulation time and provides more insightful SI evaluation, which is suitable for logic to logic and HBM interconnect design and optimization. The S parameters analysis are not sufficient for the cases like logic to logic and HBM interconnect models, which are unterminated (capacitive loading). The eye diagram analysis cannot provide an insightful guideline for optimization of interconnect model. Besides, eye diagram simulations to find the optimum interconnect model are very time consuming, as a frequency domain to time domain via an inverse fast Fourier transformation (FFT) is required. Compared with the eye diagram analysis, the proposed methodology only analyses the SI performance in frequency domain rather than in time domain, so the simulation time is reduced. The proposed methodology can overcome the drawbacks of the S parameters and eye diagram analyses and provide an in-depth and fast evaluation on the SI performance of logic to logic and HBM interconnect models frequently encountered in advanced system in package using chiplets.

关键词： Analytical models Frequency-domain analysis Integrated circuit interconnections Scattering parameters Time-domain analysis Signal integrity Load modeling

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A Study of the States Kinetics in NBTI and HCI Degradation based on TCAD

A Study of the States Kinetics in NBTI and HCI Degradation b...

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Electronics and Electrical Engineering Technology (EEET), International conference on

作者： Xinhuan Yang Mingyan Yu Xingyu Fang Liang Wang Chuanzheng Wang Yuanfu Zhao School of Electronic Information Hangzhou Dianzi University Hangzhou China Beijing Microelectronics Technology Institute Beijing Chinia

ISBN: (数字)9798350395594

ISBN: (纸本)9798350395600

The evaluation of MOSFET reliability requires aging model, which based on time-consuming and costly aging test. In order to reduce the costs of aging test, the parameters of trap (TP) and two-stage (TS) degradation models in TCAD framework were calibrated according to the data of aging test in this paper. Then the impact of parameters on the number of interface trap during degradation in PMOS were studied by using the two models. The results show that the calibrated model can basically replace the aging test and evaluate the lifetime of device. Finally, this paper proposed a decoupling method of hot carrier injection (HCI) and negative bias temperature instability (NBTI) by studying the relationship between the two effects and channel length. The purpose of this paper is to analyze the characteristic of aging effect through TCAD simulation and obtain the data establishing aging model. It provides convenience to the design of high-reliability device.

关键词： Degradation Negative bias temperature instability Semiconductor device modeling Costs Thermal variables control Voltage Aging

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A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC simulation of MPSoCs

A Fully Static Scheduling Approach for Fast Cycle Accurate S...

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2007 International conference on microelectronics (ICM'07)

作者： Richard Buchmann Alain Greiner LIP6/UPMC Université Pierre et Marie Curie Paris France

This paper presents principles and tools to facilitate Multi-Processor System on Chips (MPSoCs) design and modeling, and to speed up cycle accurate SystemC simulation. We describe an effective way to build an hardware architecture virtual prototype, using a library of SystemC simulation models based on communicating synchronous finite state machines. This modeling approach supports a fully static scheduling strategy, based on the analysis of the combinational dependency graph. Our static scheduling algorithm has been implemented in the SystemCASS simulator, and provides speed-up of one order of magnitude versus the standard event-driven SystemC simulation engine. The modeling approach proposed in this paper has been adopted by the SoCLIB french national project, that is an open modeling and simulation platform for multi-processors system on chips.

关键词： Computational modeling Hardware Job shop scheduling Virtual prototyping Discrete event simulation Dynamic scheduling Signal processing System-on-a-chip Libraries Automata

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Enabling Power Side-Channel Attack simulation on Mixed-Signal Neural Network Accelerators

Enabling Power Side-Channel Attack Simulation on Mixed-Signa...

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Omni-layer Intelligent Systems (COINS), International conference on

作者： Simon Wilhelmstätter Joschua Conrad Devanshi Upadhyaya Ilia Polian Maurits Ortmanns Institute of Microelectronics University of Ulm Ulm Germany Institute for Computer Architecture and Computer Engingeering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798350349597

ISBN: (纸本)9798350349603

Due to the tremendous success of Deep Learning with neural networks (NNs) in recent years and the simultaneous leap of embedded, low-power devices (e.g. wearables, smart-phones, IoT, and smart sensors), enabling the inference of those NNs in power-constrained environments gave rise to specialized NN accelerators. One paradigm followed by many of those accelerators was the transition from digital domain computing towards performing operations in the analog domain, turning them from digital to mixed-signal NN accelerators. While power-efficiency and inference accuracy have been researched with increasing interest, security and protection against a side-channel attack (SCA) have not found much attention. However, side-channels pose a major security concern by allowing an attacker to steal valuable knowledge about proprietary NNs deployed on accelerators. In order to evaluate mixed-signal NNs accelerators concerning SCA robustness, its tendency to leak information through the side-channel needs investigation. In this work, we propose a methodology for enabling side-channel analysis of mixed-signal NNs accelerators, which shows reasonable accuracy in an early development stage. The approach enables the reuse of large portions of design sources for simulation and production while providing flexibility and fast development cycles for changes to the analog design.

关键词： Accuracy Computational modeling Artificial neural networks Side-channel attacks Production Turning Robustness

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A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)

A Novel Method for Air-Gap Formation around Via-Middle (VM) ...

引用

Electronic Components and Technology conference (ECTC)

作者： King-Jien Chui Woon Leng Loh Xiangyu Wang Zhaohui Chen Mingbin Yu Institute of Microelectronics A*STAR (Agency for Science Technology and Research) Singapore

Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active CMOS devices through the formation of embedded air-gaps. As the air-gaps are embedded in the Si, stress isolation can be done without compromising on the usable Si area. Formation of the air-gaps have been demonstrated experimentally using a high temperature anneal in a de-oxidizing ambient. Stress reduction in the Si lattice, in the presence of the embedded air-gaps, will be studied through thermo-mechanical stress simulation. Effect of the impact of air-gap design will also be discussed.

关键词： Air gaps Silicon Through-silicon vias Stress Annealing Atmospheric modeling Surface treatment

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A novel low-voltage low-power bulk-driven cascade current mirror

A novel low-voltage low-power bulk-driven cascade current mi...

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International conference on Advanced Computer Theory and Engineering, ICACTE

作者： Li Yani Yang Yintang Zhu Zhangming Institute of Microelectronics Xidian University Xi'an China

ISBN: (纸本)9781424465392;9781424465422

A novel low-voltage low-power PMOS cascade current mirror employing the bulk-driven technique is described in this paper. Based on SMIC 0.18μm CMOS process, the characteristics of the low-voltage bulk-driven cascade current mirror are analyzed and validated, including the input/output resistance, the system dc transmission error, the frequency characteristics and noise performance, etc. The simulation results reveal that: this bulk-driven cascade current mirror is able to reduce the input voltage drop to 0.3V, and it has the better current driving ability than the gate-driven cascade current mirror does under the same conditions, along with the same good current following characteristic as the gate-driven cascade current mirror. The bulk-driven cascade current mirror achieves the low-voltage low-power characteristic at the cost of the linearity of output current vs input voltage and frequency bandwidth, as well as noise performance. The presented low-voltage bulk-driven cascade current mirror has a good performance for low-frequency low-voltage applications in the design of CMOS analog integrated circuits.

关键词： Resistance Logic gates Integrated circuit modeling Manganese

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Silicon implementation of micro pressure sensor

Silicon implementation of micro pressure sensor

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International conference on Electronic Devices, Systems and Applications (ICEDSA)

作者： Yufridin Wahab Aladin Zayegh Rezaul Begg Centre for Industrial Collaboration School of Microelectronic Engineering Universiti Malaysia Pedis Kangar Malaysia Centre for Microelectronics and Telecommunication Centre for Ageing Rehab. Exercise & Sport Science Victoria University Melbourne Australia

ISBN: (纸本)9781424466290;9781424466320

Pressure sensing is one of the mostly performed measurement encompassing varieties of applications. The latest technology such as silicon based Micro-electromechanical Systems (MEMS) technology is favoured due to its competitive cost and proven performance. In our research, MEMS pressure sensor for biomedical application is investigated. There are a number of stages involved in our research for implementation of a MEMS pressure sensor which includes application review, conceptual design, modeling, simulation, tape-out, fabrication and characterization. A highly proven technology offered by Infineon Technologies SensorNor AS is used in this research and the requirements are discussed. Recently, the device is successfully implemented on silicon and our research is now entering the characterization stage. In this paper, the research work prior to fabrication, the fabrication result and the post foundry packaging tasks for full device characterization are discussed. Future works are also discussed in the final section.

关键词： Silicon Biosensors Micromechanical devices Fabrication Sensor phenomena and characterization Performance evaluation Biomedical measurements Pressure measurement Microelectromechanical systems Costs

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Analysis of the three-dimensional delamination behavior of stretchable electronics applications

Analysis of the three-dimensional delamination behavior of s...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： O. van der Sluis P.H.M. Timmermans E.J.L. van der Zanden J.P.M. Hoefnagels Philips Applied Technologies Eindhoven Netherlands Department of Precision and Microsystem Engineering Delft University of Technnology Delft Netherlands Department of Mechanical Engineering Eindhovan University of Technology Eindhoven Netherlands

Stretchable electronics offer potential application areas in biological implants interacting with human tissue. Furthermore, they facilitate increased design freedom of electronic products. Typical applications can be found in healthcare, wellness and functional clothes. A key requirement on these products is the ability to withstand large deformations during usage without losing their integrity (i.e., large stretchability). One of the possible basic designs for stretchable electronics is to interconnect small rigid semiconductor islands with thin metal conductor lines on top of a highly deformable substrate, such as a rubber material. In this case, large stretchability must also be provided by these thin metal conductor lines. The adhesion of the conductor lines to the rubber substrate is of major importance from a reliability point of view. Experimental observations show that delamination between the metal conductor lines and the stretchable substrate may eventually lead to short circuits while also the delaminated area could result in cohesive failure of the metal lines. To understand and quantify the behavior of the copper-rubber interface, peel tests are performed and analyzed by means of experiments and numerical simulations. Interestingly, experimental observations show that the rubber is severely lifted at the delamination front caused by its high compliance. To quantify the interface properties, numerical simulations of the peel test have been performed by developing a finite element model comprising of cohesive zone elements by which the transient delamination process during the peel test is described in detail. By means of an extensive model parameter sensitivity study combined with the measured peel-force curves and the rubber-lift geometry at the delamination front, the final set of model parameters has been determined. Finally, the thus obtained model parameters are used to simulate the delamination behavior of actual three-dimensional stretchable elec

关键词： Delamination Conducting materials Substrates Rubber Performance evaluation Numerical simulation Testing Solid modeling Implants Humans

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