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A Novel CMOS Current Reference with Low Temperature and Supply Dependence

A Novel CMOS Current Reference with Low Temperature and Supp...

2006 International conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

作者： Yuan Liu Guo-qing Liu Bo He Long Fan Ning Ning Qi Yu Mo-hua Yang School of Microelectronics and Solid-State Electronics University of Electronic Science and Technology of China Chengdu Sichuan China

A new CMOS current reference solution is presented, by creating a new negative temperature coefficient (TC) current resulted from negative-TC voltage which is generated in the bandgap circuit whose zero-TC (ZTC) point is specially selected, and proposing low line regulation mechanism which is realized by compensating variations of source-to-gate voltage and threshold voltage versus supply voltages. Based on the SMIC CMOS 0.35μm model, simulation results in Cadence Hspice indicate that the current reference has a TC of 6.9ppm/℃ over the temperature range from -40 to 85℃ and a line regulation of 10.6ppm/V for a supply voltage of 3.0 to 3.6V, which are much lower than the specifications in recent designs. The new solution has been implemented into a 10 bit 100MSample/s ADC design and is promising to be applied in the research and development of analog/mixed signal systems.

关键词： Temperature dependence Temperature distribution Photonic band gap Threshold voltage Semiconductor device modeling Resistors Helium microelectronics Solid state circuits CMOS technology

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Performance of an air-cooled heat sink with microscale dimples under transitional flow conditions

Performance of an air-cooled heat sink with microscale dimpl...

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Intersociety conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM)

作者： Krishna Kota Ludovic Burton Yogendra Joshi Microelectronics and Emerging Technologies Thermal Laboratory The George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA

The objective of this effort is to pursue artificial microscale surface roughness features in the form of dimples, on the fins of an air cooled heat sink, as a passive option to energy-efficiently augment heat transfer in forced convection flows. High fidelity numerical simulations were employed for realizing an optimized dimple configuration and to comprehend the behavior of micro-sized dimples under high velocity (~17 m/s) transitional flow conditions. Fully developed flow simulations were performed, and design of experiments with response surface methodology was employed for the numerical optimization. The results showed up to 30% heat transfer improvement in the fully developed region compared to a smooth finned channel. Experiments were also carried out to assess the performance of the aforementioned optimized configuration in a custom built setup in the laboratory, which showed up to 10.5% heat transfer improvement over a corresponding smooth-walled channel. The results showed that application-specific optimization of dimples is crucial. With further exploration of shape and design parameters, dimples might have the potential to improve thermal performance passively and form an attractive candidate to realize high-performance air-cooled heat sinks in the future.

关键词： Heat transfer Heat sinks Numerical models Computational modeling Temperature measurement Response surface methodology Numerical simulation

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simulation of capacitive type bimorph humidity sensors

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Journal of Physics: conference Series 2005年第1期10卷 305-308页

作者： Fragakis, J. Chatzandroulis, S. Papadimitriou, D. Tsamis, C. National Technical University of Athens Department of Physics GR-15780 Athens Greece Institute of Microelectronics NCSR Demokritos 15310 Aghia Paraskevi PO Box 60228 Greece

FEM modeling of recently developed silicon/polymer bimorph micro-cantilever structures, applied as capacitive type humidity sensors, is presented. In these structures, the expansion of the overlying polymer in the presence of water vapors forces the silicon cantilever to bend resulting in a change of device capacitance. Experimental behavior is approximated by taking into account the stress induced in the cantilever due to the polymer swelling. simulation results are in good agreement with experimental values. The FEM model developed facilitates the design and optimization of the cantilever beam sensors. © 2005 IOP Publishing Ltd.

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Thermal design of heat spreader and analysis of thermal interface materials (TIM) for multi-chip package

Thermal design of heat spreader and analysis of thermal inte...

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Electronic Components and Technology conference (ECTC)

作者： D. Pinjala N. Khan Xie Ling Poi-Siong Teo E.H. Wong M.K. Iyer C. Lee I.J. Rasiah Institute of Microelectronics Greece Infineon Technologies Asia Pacific Private Limited Corporation Singapore Honeywell (S) Private Limited USA

Industry demand for high power multi-chip packages is increasing to realize multifunctional compact systems. In line with industry requirements a multi-chip package suitable for high performance devices is developed. The package has 1296 I/Os. It is capable of handling 2 GHz signal speed and dissipating 75 W power with an external thermal solution. A concurrent design approach is adopted for the package design. Electrical, thermal, structural issues and assembly, and materials limitations are considered in developing this package. Package level thermal design challenges involve optimization of package structure and selection of stable thermal interface material. As a part of this project, a simulation model of the package along with the external thermal solution is developed and validated by measurements. The optimized heat spreader has been designed by performing a parametric study with the validated model. The type of thermal interface material (TIM) suitable to the package has also been identified by measurements. Desired thermal performance of the package has been achieved through design optimization of the package and selection of suitable TIM. Thermal modeling and measurement methodologies, validation and parametric study results are presented in the paper. Analysis of TIMs and measured thermal performance results of packages assembled with different type of TIMs are also discussed in the paper.

关键词： Electronic packaging thermal management Thermal resistance design optimization Chemical technology Parametric study Semiconductor device measurement Copper Heat sinks Resistance heating Vehicles

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The study of thermo-mechanical reliability for multi-layer stacked chip module with through-silicon-via (TSV)

The study of thermo-mechanical reliability for multi-layer s...

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Electronics Packaging Technology conference (EPTC)

作者： F.X. Che Xiaowu Zhang Navas Khan K.H. Teo S. Gao D Pinjala Institute of Microelectronics Agency for Science Technology and Research Singapore Singapore

Through-silicon-via (TSV) technology permits devices to be placed and wired in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to many advantages of TSV application. However, there are also some challenges for stacked die package with TSVs. One of the challenges is thermo-mechanical reliability of multi-layer stacked chip modules when subjected to temperature cycling loading. In this paper, multi-layer stacked chip modules with 6 via-last memory chips and one via-middle logic chip were investigated in terms of thermo-mechanical reliability using finite element modeling and simulation method in the design stage for packaging material selection, solder joint layout design, package size effect on reliability, and solder joint fatigue life assessment and so on. The simulation results show that underfill is one of the most important parameters relating to solder joint thermal fatigue life. The effect of underfill glass transition temperature (T g ) and coefficient of thermal expansion (CTE) on solder joint life is significant. High T g and low CTE underfill results in high solder joint life. Substrate CTE is another key parameter in terms of solder joint thermo-mechanical reliability. When underfill with low T g is used in package, package with low CTE substrate results in high solder joint life. However, when high T g underfill is used in package, the effect of substrate CTE on solder joint is not significant. In addition, the effects of following parameters on solder joint reliability have also been investigated: solder joint layout design of peripheral vs. full array, solder joint alloy (low Ag vs. high Ag content solder), mold compound (molding height, mold compound material properties), substrate thickness, TSV and die thickness effects.

关键词： Soldering Reliability Substrates Strain Flip chip Through-silicon vias Fatigue

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simulation study of carbon nanotubes field emission display with triode structure

Simulation study of carbon nanotubes field emission display ...

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IEEE International conference on Vacuum microelectronics (IVMC)

作者： Chun-Tao Lee Yung-Chiang Lan Yuan Hu Cheng-Chung Lee Bing-Yue Tsui Tsang-Lang Lin Electronics Research and Service Organization Industrial Technology and Research Institute Hsinchu Taiwan National Center of High-performance Computing Hsinchu Taiwan Department of Engineering and System Science National Tsing Hua University Hinchu Taiwan Department of Electronics Engineering National Chiao Tung University Hinchu Taiwan

ISBN: (纸本)4818195154

Owing to the high aspect ratios and small radii of curvature, carbon nanotubes (CNTs) exhibit excellent field emission characteristics, which is very advantageous for the field emission display (FED) applications. In FED design, the triode structures are more attractive for their lower driving voltage and higher light efficiency. Recently, a new CNT-based triode structure, i.e., planar triode structures, was proposed and exhibited good characteristics. In this design, the lateral gate electrode generates the transverse electric fields to pull out the electrons from the neighboring emitters. But how the display resolution affected by the bias conditions of the gate electrode and by the electron beams diverged in the y-direction is not clear yet. In this paper, these problems are investigated via computer simulation.

关键词： Carbon nanotubes Flat panel displays Voltage Anodes Electron beams Electrodes Computational modeling Electron emission Computer displays Current density

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Thermal design and Characterization of High Power SiC Inverter with Low Profile and Enhanced Thermal Performance

Thermal Design and Characterization of High Power SiC Invert...

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IEEE Electronic Components and Technology conference

作者： Gongyue Tang Tai Chong Chai Xiaowu Zhang A*STAR (Agency for Science Technology and Research) Institute of Microelectronics Singapore

A single phase high power package is designed and developed in this study. The developed power package achieves significant thermal performance improvement as compared with the conventional wire-bonded power package. The improvement is attributed to two features of the package design. Firstly, the SiC chips are embedded into the active metal brazed (AMB) substrates with specially designed cavities, as such the heat transfer path from the embedded SiC chips to the liquid cooled heat sink attached to the bottom side of AMB substrate is shortened. Moreover, customized copper clips are introduced as the interconnections between the SiC chips and top metal layer of the substrate in the same level, and the top surface of the power package remains flat. As such another heat sink can be added to the top side of the package to improve the power package thermal performance further by implementing this double side cooling (DSC) Scheme. Results of the modeling and simulation show that the proposed package junction to case thermal resistance is ~50% less than the junction to case thermal resistance of the conventional wire bonded power package with same size and same power rate. Further utilizing two heat sinks on the both sides of the proposed power package which is not suitable to the conventional wire bonded power package, the junction to case thermal resistance of the proposed power package reduces another 20%. In addition, the effects of the core and metal layers of the AMB substrate on the thermal resistance of the proposed power package are investigated systematically. Finally, the thermally optimized power package is fabricated and assembled. Thermal characterization has been conducted and thermal performance of the developed power package has been evaluated. The simulation results and characterization results match well with each other.

关键词： high power modules thermal management SiC chip dual-side-cooling

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Board Level Solder Joint Reliability design and Analysis of FOWLP

Board Level Solder Joint Reliability Design and Analysis of ...

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Electronics Packaging Technology conference (EPTC)

作者： Xiaowu Zhang Boon Long Lau Haoran Chen Yong Han Ming Chinq Jong Sharon Pei Siang Lim Simon Siak Boon Lim Xiaobai Wang Yosephine Andriani Songlin Liu Institute of Microelectronics (IME) A*STAR (Agency for Science Technology and Research) Singapore Institute of Materials Research and Engineering (IMRE) A*STAR (Agency for Science Technology and Research) Singapore

ISBN: (数字)9781728189116

ISBN: (纸本)9781728189123

This paper presents a comprehensive board level solder joint reliability study under thermal cycling (TC) loading by both numerical simulation and experimental test. TC profile is from -40°C to 125°C. In numerical simulation, both epoxy molding compound (EMC) and dielectric are modeled as viscoelastic materials. SAC is modeled as a creep material while the remaining materials are assumed to be elastic. The critical solder joint location predicted by modeling agrees well with the experimental result. Results show: (1) lower CTE PCB improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB CTE is reduced from 17 ppm/°C to 10ppm/°C; (2) thinned PCB thickness improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB thickness is reduced from 1.5 mm to 1 mm. Finally, life prediction model for solder joints of FOWLP has been successfully established as well.

关键词： Soldering Reliability Creep Semiconductor device reliability Strain Packaging Predictive models

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Avalanche Ruggedness Evaluation on Planar and Trench SiC MOSFETs: An Experimental and TCAD simulation Study

Avalanche Ruggedness Evaluation on Planar and Trench SiC MOS...

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International conference on (ICEPT) Electronic Packaging Technology

作者： Tao Luo Runding Luo Zaiman Xiang Jianjun Zhuang Guoqi Zhang Jiajie Fan Academy for Engineering & Technology Fudan University Shanghai China Changzhou Galaxy Century Microelectronics Co. Ltd. Changzhou China EEMCS Faculty Delft University of Technology Delft the Netherlands Research Institute of Fudan University in Ningbo Ningbo China

ISBN: (数字)9798350353808

ISBN: (纸本)9798350353815

In the domain of power electronics, especially for applications requiring high power, high temperature, and high frequency, Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors (SiC MOSFETs) stand out due to their excellent properties such as high thermal conductivity, elevated breakdown electric field, and minimal power loss. These devices are pivotal in the reliability and safety of electric vehicles, where avalanche-induced failures represent a significant risk within automotive uses. This study extensively explores the avalanche ruggedness of both planar and trench SiC MOSFET configurations through a combination of Unclamped Inductive Switching (UIS) testing in single and multiple pulse scenarios, and Technology Computer-Aided design (TCAD) simulations. Initial UIS experiments revealed the primary failure mechanisms and their origins in SiC MOSFETs. Following empirical analysis, TCAD simulations were employed to develop comprehensive models of these devices., enhancing the understanding of failure dynamics during UIS conditions. The integration of empirical and simulation data supports the creation of advanced strategies to reduce the risk of avalanche failures, thereby enhancing the durability and reliability of Wide Bandgap Semiconductor devices.

关键词： MOSFET Analytical models Silicon carbide Computational modeling Failure analysis Metals Switches

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Multiple transient effects in SOI transistors: Systematic measurements and simulation

Multiple transient effects in SOI transistors: Systematic me...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： D. Weiser D. Munteanu S. Cristoloveanu O. Faynot J.L. Pelloie J. Fossum Department of Electrical Engineering University of Florida Gainesville FL USA LPCS (UMR CNRS 5531) ENSERG Grenoble France LETI-CEA Grenoble Grenoble France

The use of partially depleted SOI CMOS technology in mainstream ULSI can be limited by transient floating body effects, that make circuit design problematic. Time-dependent V/sub T/ is observed in circuits, leading to unusual behaviours, such as current overshoot and undershoot. In order to properly evaluate the time-dependent floating-body effects on circuit performance, it is necessary to use a model (including both carrier generation and recombination) which predicts the transient responses of single devices to various front and back gate pulses. We present an enhanced version of SOISPICE-4.4 which provides the capabilities needed to correctly simulate floating-body transient effects in partially depleted circuits. The simulations are validated through systematic measurements over a wide range of experimental conditions: carrier generation and recombination-based transients, single and dual gate, back and front gate, various gate geometries. Most experiments were conducted at low V/sub D/ (to avoid impact-ionization and self-heating, i.e., to facilitate accurate calibration of the simulator) on partially depleted NMOS transistors fabricated on UNIBOND and Low-Dose SIMOX wafers. Four families of transients have been recorded, analyzed and simulated.

关键词： CMOS technology Circuit simulation Ultra large scale integration Circuit synthesis Circuit optimization Predictive models Pulse generation Pulse circuits Solid modeling Geometry

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