This paper describes an approach to the major issues of design for Manufacturability (DFM) based on Principal Component Analysis and design of Experiments techniques, which has been formulated and implemented for a 1...
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This paper describes an approach to the major issues of design for Manufacturability (DFM) based on Principal Component Analysis and design of Experiments techniques, which has been formulated and implemented for a 1μm CMOS technology, culminating in the generation of realistic nominal and worst-case model parameter sets.
The use of numerical simulation has become an invaluable tool in the competitive environment of technology and device development. Effective process and device simulation can reduce the time and cost associated with n...
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The use of numerical simulation has become an invaluable tool in the competitive environment of technology and device development. Effective process and device simulation can reduce the time and cost associated with new product development and can provide a means for rapid assessment of new design concepts. The scaling of voltages and geometries in flash EEPROM has highlighted the need for models which more accurately reproduce device terminal currents. A new model for hot-carrier gate current has been developed and integrated into 2D hydrodynamic (HYDRO) HFIELDS, a numerical device simulator developed in the University of Bologna. This paper presents a selection of design issues analysed using the enhanced simulator.
A digital implementation of self-organizing maps is presented. The chip designed includes 32 neurons with 1024 16-bit weights and 8-bit inputs. Each neutron performs bit-serial processing to minimize the occupied sili...
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A digital implementation of self-organizing maps is presented. The chip designed includes 32 neurons with 1024 16-bit weights and 8-bit inputs. Each neutron performs bit-serial processing to minimize the occupied silicon area. Several chips can be interconnected to expand the number of neurons in the network. The number of inputs per neuron depends on the internal weight memory size. The dimensionality of the network the neighbourhood topology and the rate at which the neighbouring cells learn, are programmable. The design was realised using the cells of the ES2 ecpd10 Library and simulated with Verilog. The estimated operation speed is 0.7 MCUPS/mm/sup 2/ during the learning phase, and 1.95 MCPS/mm/sup 2/ during the recall phase.
A systolic array architecture based on an efficient data-flow management for implementing the full-search block-matching algorithm for HDTV motion estimation is described. It is capable of treating (16/spl times/16)-b...
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ISBN:
(纸本)0818649909
A systolic array architecture based on an efficient data-flow management for implementing the full-search block-matching algorithm for HDTV motion estimation is described. It is capable of treating (16/spl times/16)-blocks, with a displacement of /spl minus/8/+7 pixels. Serial data inputs save the pin counts and all the input data in current frame are read only once to keep the requirements to external units to a minimum. A simplified PE design reduces the computation to 1/3 of that by directly implementing the original algorithm without any influence on the performance. simulation results show that pixel rates at about 150 MHz can be reached with 0.8 /spl mu/m CMOS technology. Owing to the highly regular and modular properties, the proposed architecture is suitable for VLSI implementation. Transistor count is estimated about 320,000, which shows that the architecture can be realized in a single chip.< >
This paper describes the simulation results of an induction motor speed control based on fuzzy logic theory. Voltage impress control technique has been applied to medium power induction motor. An automatic approach to...
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This paper describes the simulation results of an induction motor speed control based on fuzzy logic theory. Voltage impress control technique has been applied to medium power induction motor. An automatic approach to extract control rules allows us to reduce the design time. Computer simulations have been carried out in order to test the performances of the whole control system. Then a hardware implementation of the fuzzy controller is proposed by means of a dedicated fuzzy processor: WARP (weight associative rule processor).< >
Summary form only given. We have developed a mixed-level simulation environment by integrating a new system-level optical link simulation tool with a circuit-level simulation tool to provide a simulation environment t...
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Summary form only given. We have developed a mixed-level simulation environment by integrating a new system-level optical link simulation tool with a circuit-level simulation tool to provide a simulation environment that can be used to efficiently optimize component parameters in an optical interconnect. The optical link simulation is driven by the iFROST (Illinois fiber-optic and optoelectronic systems toolkit) program. iFROST is an ANSI C program for the simulation of digital lightwave links at a higher level than a circuit or component simulator.
Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation becomes more complex, difficult, and costly. Behavioral fault simulation at...
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Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation becomes more complex, difficult, and costly. Behavioral fault simulation at top functional level, described in a hardware description language, offers very attractive alternatives to these problems. This paper presents a new way to simulate the behavioral fault models for the Very high speed integrated circuits Hardware Description Language (VHDL). The performance analysis shows that relatively small number of test patterns generated by the behavioral fault simulation and Automatic Test Pattern Generation (ATPG) system detects around 98 percent of all testable gate-level faults.< >
Parameter extraction stands as a critical issue for the modeling, simulation and design of CMOS transistors and circuits. Over the years, many methods have been proposed, refined and optimized until they became unable...
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Parameter extraction stands as a critical issue for the modeling, simulation and design of CMOS transistors and circuits. Over the years, many methods have been proposed, refined and optimized until they became unable to account for new device characteristics brought about by technological progress. Such a situation applies to ultra-thin oxides, where the transconductance may exhibit negative values. The aim of this paper is: (1) to propose an adequate method for the extraction of the threshold voltage V/sub T/, field effect mobility /spl mu//sub 0/, effective channel length (L-/spl Delta/L), gate-induced mobility attenuation factors /spl theta//sub 1,2/; and (2) to demonstrate its superiority over standard techniques used in thicker oxides (>10 nm). Our test devices were n-channel (partially and fully depleted) SOI MOSFET's with silicon thicknesses ranging from 30 to 150 nm, with LDD configuration and various gate oxides from 4.5 to 17.5 nm thick. The device width was 25 /spl mu/m and the gate length varied from 0.4 to 25 /spl mu/m.
The conference third volume contains 224 papers. The topics covered include adaptive control;aerospace systems;nonlinear control in mechanical applications;fuzzy control;process control;linearization techniques;discre...
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ISBN:
(纸本)0780308611
The conference third volume contains 224 papers. The topics covered include adaptive control;aerospace systems;nonlinear control in mechanical applications;fuzzy control;process control;linearization techniques;discrete event systems;identification;computer aided design;optimization methods;mechanical systems;applications of stability theory;robust LQ control;space station Freedom;robotics;neural networks;batch processes and discrete events;nonlinear control;modeling and simulation;discrete time systems;numerical methods;optimal control;motion and vibration control;decentralized control;robust pole placement;adaptive nonlinear control;flexible manipulators;modeling and control of microelectronics;stability theory;fault tolerant control;and linear systems.
This conference proceedings contains 230 papers on control system design and robotics. Topics discussed include identification for control design, computer aided control system design, control system stability theory,...
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ISBN:
(纸本)0780308611
This conference proceedings contains 230 papers on control system design and robotics. Topics discussed include identification for control design, computer aided control system design, control system stability theory, nonlinear control theory, modeling and control of microelectronics manufacturing, flexible manipulators, neural network synthesis, nonlinear dynamical problems in process control, robust performance of control systems, adaptive nonlinear control of mechanical systems, motion and vibration control using command shaping methods, decentralized control systems, robust pole placement, estimation and control of discrete time systems, numerical methods of control system synthesis, optimal control systems, batch processes and discrete events, applications and design methods for nonlinear control, and computer simulation of control systems.
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