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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Applications of a Novel Hot Carrier Injection Model in Flash EEPROM design

Applications of a Novel Hot Carrier Injection Model in Flash...

引用

European conference on Solid-State Device Research (ESSDERC)

作者： A. Concannon A. Mathewson F. Piccinini G.L. Mei R. Bez C. Lombardi National Microelectronics Research Centre University College Cork Ireland SGS-Thomson Microelectronics-Central Research and Development Agrate Italy SGS-Thomson Agrate-Brianza Italy

The use of numerical simulation has become an invaluable tool in the competitive environment of technology and device development. Effective process and device simulation can reduce the time and cost associated with new product development and can provide a means for rapid assessment of new design concepts. The scaling of voltages and geometries in flash EEPROM has highlighted the need for models which more accurately reproduce device terminal currents. A new model for hot-carrier gate current has been developed and integrated into 2D hydrodynamic (HYDRO) HFIELDS, a numerical device simulator developed in the University of Bologna. This paper presents a selection of design issues analysed using the enhanced simulator.

关键词： Hot carrier injection EPROM Numerical simulation Costs Product development Voltage Geometry Solid modeling Hot carriers Hydrodynamics

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A digital implementation of self-organizing maps

A digital implementation of self-organizing maps

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Proceedings of the International conference on microelectronics for Neural Networks and Fuzzy Systems

作者： B. Pino F.J. Pelayo A. Prieto Departamento Electronica y Tecnologia de Computadores Universidad de Granada Granada Spain

A digital implementation of self-organizing maps is presented. The chip designed includes 32 neurons with 1024 16-bit weights and 8-bit inputs. Each neutron performs bit-serial processing to minimize the occupied silicon area. Several chips can be interconnected to expand the number of neurons in the network. The number of inputs per neuron depends on the internal weight memory size. The dimensionality of the network the neighbourhood topology and the rate at which the neighbouring cells learn, are programmable. The design was realised using the cells of the ES2 ecpd10 Library and simulated with Verilog. The estimated operation speed is 0.7 MCUPS/mm/sup 2/ during the learning phase, and 1.95 MCPS/mm/sup 2/ during the recall phase.

关键词： Self organizing feature maps Neurons Artificial neural networks Network topology Extraterrestrial measurements Silicon Libraries Hardware design languages Computational modeling Computer simulation

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VLSI architecture for HDTV motion estimation based on block-matching algorithm

VLSI architecture for HDTV motion estimation based on block-...

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International conference on VLSI design

作者： Feng-Ming Yang S. Wolter R. Laur Institute for Microelectronics University of Brethemen Bremen Germany Research Centre of Dbp Telekom Darmstadt Germany

ISBN: (纸本)0818649909

A systolic array architecture based on an efficient data-flow management for implementing the full-search block-matching algorithm for HDTV motion estimation is described. It is capable of treating (16/spl times/16)-blocks, with a displacement of /spl minus/8/+7 pixels. Serial data inputs save the pin counts and all the input data in current frame are read only once to keep the requirements to external units to a minimum. A simplified PE design reduces the computation to 1/3 of that by directly implementing the original algorithm without any influence on the performance. simulation results show that pixel rates at about 150 MHz can be reached with 0.8 /spl mu/m CMOS technology. Owing to the highly regular and modular properties, the proposed architecture is suitable for VLSI implementation. Transistor count is estimated about 320,000, which shows that the architecture can be realized in a single chip.< >

关键词： Very large scale integration HDTV Motion estimation Computer architecture CMOS technology Systolic arrays Bandwidth microelectronics Electronic mail Computational modeling

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Fuzzy controller design to drive an induction motor

Fuzzy controller design to drive an induction motor

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IEEE International conference on Fuzzy Systems (FUZZ-IEEE)

作者： G. D'Angelo M. Lo Presti G. Rizzotto Universita degli Studi di Catania Catania Sicilia IT Fuzzy Logic Res. Group Catania Univ. Italy S.G.S. Thomson Microelectronics Corporate Advanced System Architectures Agrate-Brianza Italy

This paper describes the simulation results of an induction motor speed control based on fuzzy logic theory. Voltage impress control technique has been applied to medium power induction motor. An automatic approach to extract control rules allows us to reduce the design time. Computer simulations have been carried out in order to test the performances of the whole control system. Then a hardware implementation of the fuzzy controller is proposed by means of a dedicated fuzzy processor: WARP (weight associative rule processor).< >

关键词： Fuzzy control Induction motors Automatic control Computational modeling Velocity control Fuzzy logic Voltage control Computer simulation System testing Performance evaluation

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Optimizing component specifications in optical interconnects using mixed-level simulation

Optimizing component specifications in optical interconnects...

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IEEE Photonics conference (IPC)

作者： B.K. Whitlock J.J. Morikuni Sung-Mo Kang University of Illinois at Urbana-Champaign Urbana IL US Department of Electrical and Computer Engineering and Center for Compound Semiconductor Microelectronics University of Illinois Urbana-Champaign Urbana IL USA

Summary form only given. We have developed a mixed-level simulation environment by integrating a new system-level optical link simulation tool with a circuit-level simulation tool to provide a simulation environment that can be used to efficiently optimize component parameters in an optical interconnect. The optical link simulation is driven by the iFROST (Illinois fiber-optic and optoelectronic systems toolkit) program. iFROST is an ANSI C program for the simulation of digital lightwave links at a higher level than a circuit or component simulator.

关键词： Optical interconnections Circuit simulation Optical fiber communication Laser modes Semiconductor lasers Laser noise Laser theory Quantum well lasers Computational modeling Optical design

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Behavioral fault simulation and ATPG, system for VHDL

Behavioral fault simulation and ATPG, system for VHDL

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Annual IEEE International conference and Exhibit ASIC

作者： T.H. Noh C.-I.H. Chen S.M. Chung ELDC/Custom Microelectronics Defense Electronics Supply Center Dayton OH USA Department of Electrical EngE28099g Wright State University Dayton OH USA Department of Computer Science EngE28099g Wright State University Dayton OH USA

Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation becomes more complex, difficult, and costly. Behavioral fault simulation at top functional level, described in a hardware description language, offers very attractive alternatives to these problems. This paper presents a new way to simulate the behavioral fault models for the Very high speed integrated circuits Hardware Description Language (VHDL). The performance analysis shows that relatively small number of test patterns generated by the behavioral fault simulation and Automatic Test Pattern Generation (ATPG) system detects around 98 percent of all testable gate-level faults.< >

关键词： Automatic test pattern generation Circuit faults Circuit simulation Very large scale integration Hardware design languages Integrated circuit technology Integrated circuit modeling Very high speed integrated circuits Performance analysis Test pattern generators

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A new parameter extraction method for ultra-thin oxide SOI MOSFET's

A new parameter extraction method for ultra-thin oxide SOI M...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： O. Faynot S. Cristoloveanu P. McLarty C. Raynaud J. Gautier LETI (CEA-Technologies Avancées)-DMEL-CEN/G Grenoble France Laboratoire de Physique des Composants à Semiconducteurs (UA-CNRS) ENSERG Grenoble France Department Electrical and ComputerEngineering State University Raleigh NC USA

Parameter extraction stands as a critical issue for the modeling, simulation and design of CMOS transistors and circuits. Over the years, many methods have been proposed, refined and optimized until they became unable to account for new device characteristics brought about by technological progress. Such a situation applies to ultra-thin oxides, where the transconductance may exhibit negative values. The aim of this paper is: (1) to propose an adequate method for the extraction of the threshold voltage V/sub T/, field effect mobility /spl mu//sub 0/, effective channel length (L-/spl Delta/L), gate-induced mobility attenuation factors /spl theta//sub 1,2/; and (2) to demonstrate its superiority over standard techniques used in thicker oxides (>10 nm). Our test devices were n-channel (partially and fully depleted) SOI MOSFET's with silicon thicknesses ranging from 30 to 150 nm, with LDD configuration and various gate oxides from 4.5 to 17.5 nm thick. The device width was 25 /spl mu/m and the gate length varied from 0.4 to 25 /spl mu/m.

关键词： Parameter extraction Semiconductor device modeling Circuit simulation MOSFETs Optimization methods CMOS technology Transconductance Threshold voltage Attenuation Testing

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American Control conference

American Control Conference

引用

Proceedings of the 1993 American Control conference

ISBN: (纸本)0780308611

The conference third volume contains 224 papers. The topics covered include adaptive control;aerospace systems;nonlinear control in mechanical applications;fuzzy control;process control;linearization techniques;discrete event systems;identification;computer aided design;optimization methods;mechanical systems;applications of stability theory;robust LQ control;space station Freedom;robotics;neural networks;batch processes and discrete events;nonlinear control;modeling and simulation;discrete time systems;numerical methods;optimal control;motion and vibration control;decentralized control;robust pole placement;adaptive nonlinear control;flexible manipulators;modeling and control of microelectronics;stability theory;fault tolerant control;and linear systems.

关键词： Control systems

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American Control conference

American Control Conference

引用

Proceedings of the 1993 American Control conference Part 3 (of 3)

ISBN: (纸本)0780308611

This conference proceedings contains 230 papers on control system design and robotics. Topics discussed include identification for control design, computer aided control system design, control system stability theory, nonlinear control theory, modeling and control of microelectronics manufacturing, flexible manipulators, neural network synthesis, nonlinear dynamical problems in process control, robust performance of control systems, adaptive nonlinear control of mechanical systems, motion and vibration control using command shaping methods, decentralized control systems, robust pole placement, estimation and control of discrete time systems, numerical methods of control system synthesis, optimal control systems, batch processes and discrete events, applications and design methods for nonlinear control, and computer simulation of control systems.

关键词： Control system synthesis

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Demosthenes-A technology-independent power DMOS layout generator

Demosthenes-A technology-independent power DMOS layout gener...

引用

European design Automation conference

作者： G. Fourneris N. Bekkara J. Benkoski L. Zullino D. Spatafora G. Martino SGS-Thomson Microelectronics Grenoble France SGS-Thomson Microelectronics Cornaredo Italy

A methodology to automate DMOS layout generation starting from electrical specifications is presented. The main features of the Demosthenes technology independent layout generator that make it possible to synthesize lateral and vertical DMOS in different low and high voltage technologies are described. The built-in electrical model used by the generator to extract the device layout resistance is exposed and the accuracy of the model, ranging from 1% to 15%, is reported, according to comparisons with silicon measurements. In the future, the Demosthenes generator will be extended to support the next generation of BCD technology. In addition, electrical modeling capabilities will be improved by generating detailed electrical simulation models that make it possible to accurately simulate DMOS switching.< >

关键词： Power generation microelectronics Low voltage MOSFETs FETs Switches Libraries Solid modeling CMOS technology Silicon

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