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IEEE International conference on Plasma Science (ICOPS)

作者： Junqing Lu M.J. Kushner Dept. of Mech. & Ind. Eng. Illinois Univ. Urbana IL USA Department of Electrical and Computer Engineering University of Illinois Urbana IL USA

Summary form only given. Ionized metal physical vapor deposition (IMPVD) is used to deposit diffusion barriers and metal seed layers into high aspect ratio trenches for interconnect wiring in the fabrication of microelectronics devices. To decrease the RC time delay of signals, Cu interconnects are replacing Al whose resistance is almost twice that of Cu. To improve the design of IMPVD systems, it is useful to have a comprehensive simulator. To address this need, an integrated plasma equipment-feature model has been developed, and applied to the investigation of Cu IMPVD. The computational tools use in this study are the two-dimensional Hybrid Plasma Equipment Model (HPEM), the Plasma Chemistry Monte Carlo simulation (PCMCS) and the Monte Carlo feature profile model (MCFPIM). The HPEM produces species densities and source functions in the bulk plasma. The PCMCS computes the trajectories of ions and neutral species which are incident onto features based on the species densities and sources from the HPEM. The MCFPM uses these fluxes to simulate the deposition profile in a trench. The MCFPM, originally written for etching, was extended to deposition by adding surface diffusion algorithms. These algorithms use Monte Carlo techniques to move adsorbed pseudoparticles on the surface employing probabilities based on the local inter-particle potentials.

关键词： Plasma applications Plasma chemistry Plasma density Plasma simulation Plasma sources Plasma devices Computational modeling Monte Carlo methods Chemical vapor deposition Wiring

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simulation study of carbon nanotubes field emission display with triode structure

Simulation study of carbon nanotubes field emission display ...

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IEEE International conference on Vacuum microelectronics (IVMC)

作者： Chun-Tao Lee Yung-Chiang Lan Yuan Hu Cheng-Chung Lee Bing-Yue Tsui Tsang-Lang Lin Electronics Research and Service Organization Industrial Technology and Research Institute Hsinchu Taiwan National Center of High-performance Computing Hsinchu Taiwan Department of Engineering and System Science National Tsing Hua University Hinchu Taiwan Department of Electronics Engineering National Chiao Tung University Hinchu Taiwan

ISBN: (纸本)4818195154

Owing to the high aspect ratios and small radii of curvature, carbon nanotubes (CNTs) exhibit excellent field emission characteristics, which is very advantageous for the field emission display (FED) applications. In FED design, the triode structures are more attractive for their lower driving voltage and higher light efficiency. Recently, a new CNT-based triode structure, i.e., planar triode structures, was proposed and exhibited good characteristics. In this design, the lateral gate electrode generates the transverse electric fields to pull out the electrons from the neighboring emitters. But how the display resolution affected by the bias conditions of the gate electrode and by the electron beams diverged in the y-direction is not clear yet. In this paper, these problems are investigated via computer simulation.

关键词： Carbon nanotubes Flat panel displays Voltage Anodes Electron beams Electrodes Computational modeling Electron emission Computer displays Current density

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simulation of capacitive type bimorph humidity sensors

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Journal of Physics: conference Series 2005年第1期10卷 305-308页

作者： Fragakis, J. Chatzandroulis, S. Papadimitriou, D. Tsamis, C. National Technical University of Athens Department of Physics GR-15780 Athens Greece Institute of Microelectronics NCSR Demokritos 15310 Aghia Paraskevi PO Box 60228 Greece

FEM modeling of recently developed silicon/polymer bimorph micro-cantilever structures, applied as capacitive type humidity sensors, is presented. In these structures, the expansion of the overlying polymer in the presence of water vapors forces the silicon cantilever to bend resulting in a change of device capacitance. Experimental behavior is approximated by taking into account the stress induced in the cantilever due to the polymer swelling. simulation results are in good agreement with experimental values. The FEM model developed facilitates the design and optimization of the cantilever beam sensors. © 2005 IOP Publishing Ltd.

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Statistical rare event analysis using smart sampling and parameter guidance

Statistical rare event analysis using smart sampling and par...

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IEEE International SOC conference

作者： Yue Zhao Hosoon Shin Haibao Chen Sheldon X.-D. Tan Guoyong Shi Xin Li Department of Electrical and Computer Engineering University of California Riverside CA School of Microelectronics Shanghai Jiao Tong University Shanghai China Shanghai Jiao Tong University Shanghai CN Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA

In this paper, we propose a new efficient statistical method for failure probability estimation of analog circuits with rate failure events, which is a time-consuming process using the existing Monte Carlo method. On top of this, the new method can also provide the estimation of parameter regions to achieve targeted performance to facilitate the design process, which is missing in the traditional fast statistical methods such as the statistical blockage based method. The new method employs two new techniques to speed up the analysis. First, to reduce the large number of samples for rare event analysis, the new approach employs a smart sample selection scheme, which can consider the effectiveness of samples and well-coverage for the parameter space. As a result, it can reduce an additional simulation costs by pruning less effective samples while keeping the accuracy of failure estimation. Second, the new approach identifies the failure regions in terms of parameters to provide a good design guideline for designers and optimization tools. This is enabled by applying the variance based feature selection to find the dominant parameters. A quasi-random sampling with dominant parameters is then applied to determine in-spec boundaries of those parameters. In addition, we also provide the complete formula for the probability determinations of failure regions in the iterative failure region searching framework. We demonstrate the advantage of our proposed method using two test benches: 6T-SRAM reading failure diagnosis with 27 process parameters, charge pump operation failure diagnosis in a PLL circuit with 81 process parameters. Experimental results show that the new method can be 4X more accurate than the recently proposed REscope method. Furthermore, the new method reduces the simulation cost by 2X than the recursive statistical blockage (RSB) method with same accuracy level. Our approach also provides the precise guidance of diverse parameters with 1.21% estimation error

关键词： Probability Integrated circuit modeling simulation Estimation Measurement Monte Carlo methods

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Avalanche Ruggedness Evaluation on Planar and Trench SiC MOSFETs: An Experimental and TCAD simulation Study

Avalanche Ruggedness Evaluation on Planar and Trench SiC MOS...

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International conference on (ICEPT) Electronic Packaging Technology

作者： Tao Luo Runding Luo Zaiman Xiang Jianjun Zhuang Guoqi Zhang Jiajie Fan Academy for Engineering & Technology Fudan University Shanghai China Changzhou Galaxy Century Microelectronics Co. Ltd. Changzhou China EEMCS Faculty Delft University of Technology Delft the Netherlands Research Institute of Fudan University in Ningbo Ningbo China

ISBN: (数字)9798350353808

ISBN: (纸本)9798350353815

In the domain of power electronics, especially for applications requiring high power, high temperature, and high frequency, Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors (SiC MOSFETs) stand out due to their excellent properties such as high thermal conductivity, elevated breakdown electric field, and minimal power loss. These devices are pivotal in the reliability and safety of electric vehicles, where avalanche-induced failures represent a significant risk within automotive uses. This study extensively explores the avalanche ruggedness of both planar and trench SiC MOSFET configurations through a combination of Unclamped Inductive Switching (UIS) testing in single and multiple pulse scenarios, and Technology Computer-Aided design (TCAD) simulations. Initial UIS experiments revealed the primary failure mechanisms and their origins in SiC MOSFETs. Following empirical analysis, TCAD simulations were employed to develop comprehensive models of these devices., enhancing the understanding of failure dynamics during UIS conditions. The integration of empirical and simulation data supports the creation of advanced strategies to reduce the risk of avalanche failures, thereby enhancing the durability and reliability of Wide Bandgap Semiconductor devices.

关键词： MOSFET Analytical models Silicon carbide Computational modeling Failure analysis Metals Switches

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Multiple-choice Hardware/Software Partitioning:Computing Model and Algorithms

Multiple-choice Hardware/Software Partitioning:Computing Mod...

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2010 2nd International conference on Computer Engineering and Technology(2010年第二届计算机工程与技术国际会议 ICCET 2010)

作者： Wu Jigang Qiqiang Sun Thambipillai Srikanthan School of Computer Science and Software Tianjin Polytechnic UniversityChina300160 School of Comput School of Software and Microelectronics Peking UniversityBeijingChina 102600 School of Computing Engineering Nanyang Technological UniversityRepublic of Singapore639798

ISBN: (纸本)9781424463473

Hardware/software (HW/SW) partitioning is one of the crucial steps of co-design systems. It determines which components of the system are implemented in hardware and which ones are in software. As hardware of larger area may provide higher implementing speed for a give component due to the parallelizable execution in hardware,one component may have different ways of hardware implementations. In this paper the computing model is proposed to cater for the multiplechoice HW/SW partitioning. On the new computing model an *** heuristic algorithm is developed,in which both speedup in hardware and communication penalty are taken into account. In addition,an exact algorithm is also presented based on dynamic programming to evaluate the approximate solutions produced by the heuristic algorithm for relatively small problems. simulation results show that the heuristic algorithm runs fast and is able to produce high-quality approximate solutions. The difference between the approximate solutions and the optimal ones is bounded by 0.5％,and it hardly increases with the increase in the problem size.

关键词： Hardware Partitioning algorithms Software algorithms Heuristic algorithms Software performance Dynamic programming Computational modeling Computer science Genetic engineering microelectronics

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Spot defect modeling: Past and evolution

Spot defect modeling: Past and evolution

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International conference on design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Michel Renovell LIRMM CNRS/Université de Montpellier

ISBN: (纸本)9781509063789

With today manufacturing technology, it is not possible to eliminate all defects and ensure every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. Different Test Strategies are commonly used since none is considered as optimal in terms of low defect level. Most companies use some but not all of the following three Test Strategies: the Static Voltage strategy, the Dynamic Voltage or Delay strategy, the Static or Dynamic Current (I_DDX) strategy. While using different approaches, these different test strategies have a common objective: reveal the presence in the chip of defects or deviations that may create a dysfunction. Knowing the complexity of today defects, it is admitted that the classical fault models used for test generation cannot guarantee a satisfactory detection of defects. This implies that new test generation technique specifically oriented to defects have to be defined. So, we must analyze and understand the electrical behavior of the defect and describe its behavior through an adequate `defect model'. Then, defect simulation techniques and defect-oriented ATPG techniques must be proposed to allow specific test generation for these defects. This presentation focuses on spot defects that manifest themselves as shorts or opens in the interconnect or in the MOS transistors: `Interconnect open', `Interconnect short', `Floating gate', and `Gate-Oxide-Short' are analyzed in detail using different model levels. For every defect, it is shown that the electrical behavior is in fact not predictable due to the presence of random parameters. In order to tackle the problem of unpredictability, unified concepts are proposed that allow new test generation techniques guaranteeing coverage of unpredictable defects.

关键词： Analytical models Computer science microelectronics Manufacturing Companies Delays Complexity theory

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L-MPC: A LUT based MuIti-LeveI Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network

L-MPC: A LUT based MuIti-LeveI Prediction-Correction Archite...

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design Automation conference

作者： Hong Liu Leibo Liu Wenping Zhu Qiang Li Huiyu Mo Shaojun Wei Institute of Microelectronics Tsinghua University Beijing China Chinese Academy of Science Institute of Semiconductors Beijing China Intel Corporation Beijing China

ISBN: (纸本)9781728124261

A binary-weight hourglass network (B-HG) accelerator for landmark detection, built on the proposed look-up-table (LUT) based multi-level prediction-correction approach, is enabled for highspeed and energy-efficient processing on IoT edge devices. First, LUT with a unified mode is adopted to support convolutional neural network with fully variable weight bit precision to minimize operations of B-HG, which achieves 1.33×-1.50× speedup on multi-bit weight CNN relative to the similar solution. Second, multi-level prediction-correction model is proposed to achieve computationalefficient convolution with adaptive precision. The operations saved can be increase by about 30% than the two-stage model. Besides, nearly 77.4% of the operations in B-HG can be saved by using the combination of these two methods, yielding a 2.3× inference speedup. Third, block computing based pipeline is designed to improve the residual block deficiency in B-HG. It can not only reduce about 66.2% off-chip memory access than the baseline, but also save 60% and 31% on-chip memory space and access compared to the similar fused-layer accelerator. The proposed B-HG accelerator achieves 450 fps at 500MHz based on the simulation in TSMC 28 nm process. Meanwhile, the power efficiency is up to 8.5 TOPS/W, which is two orders of magnitude higher than the dedicated face landmark detection accelerator.

关键词： Table lookup Kernel Convolution Computational modeling Energy efficiency Image edge detection Hardware

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The study of thermo-mechanical reliability for multi-layer stacked chip module with through-silicon-via (TSV)

The study of thermo-mechanical reliability for multi-layer s...

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Electronics Packaging Technology conference (EPTC)

作者： F.X. Che Xiaowu Zhang Navas Khan K.H. Teo S. Gao D Pinjala Institute of Microelectronics Agency for Science Technology and Research Singapore Singapore

Through-silicon-via (TSV) technology permits devices to be placed and wired in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to many advantages of TSV application. However, there are also some challenges for stacked die package with TSVs. One of the challenges is thermo-mechanical reliability of multi-layer stacked chip modules when subjected to temperature cycling loading. In this paper, multi-layer stacked chip modules with 6 via-last memory chips and one via-middle logic chip were investigated in terms of thermo-mechanical reliability using finite element modeling and simulation method in the design stage for packaging material selection, solder joint layout design, package size effect on reliability, and solder joint fatigue life assessment and so on. The simulation results show that underfill is one of the most important parameters relating to solder joint thermal fatigue life. The effect of underfill glass transition temperature (T g ) and coefficient of thermal expansion (CTE) on solder joint life is significant. High T g and low CTE underfill results in high solder joint life. Substrate CTE is another key parameter in terms of solder joint thermo-mechanical reliability. When underfill with low T g is used in package, package with low CTE substrate results in high solder joint life. However, when high T g underfill is used in package, the effect of substrate CTE on solder joint is not significant. In addition, the effects of following parameters on solder joint reliability have also been investigated: solder joint layout design of peripheral vs. full array, solder joint alloy (low Ag vs. high Ag content solder), mold compound (molding height, mold compound material properties), substrate thickness, TSV and die thickness effects.

关键词： Soldering Reliability Substrates Strain Flip chip Through-silicon vias Fatigue

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A 800MS/s, 150µV input-referred offset single-stage latched comparator

A 800MS/s, 150µV input-referred offset single-stage latched...

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International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： Sarang Kazeminia Sina Mahdavi Department of Electrical Engineering Urmia University of Technology Urmia Iran Department of Microelectronics Engineering Urmia Graduate Institute Urmia Iran

ISBN: (纸本)9781509030996

In the proposed single-stage comparator, the comparison cycle is divided into six phases to cancel the static offset and then perform comparison. Operations, except in reset, are scheduled by applying small voltage variations, up to 200mVolts, on bulk terminals of concurrently used negative and positive feedback PMOS devices. Negative feedback restricts the gain of the main comparison and the offset cancellation loop during pre-amplification. Pre-amplification phase is intentionally added before the latch operation to remove the concerns of the erroneous latch of unpredictable residues which might be remained across the reset switch from the last comparison. The negative and positive feedback devices also impart in offset cancellation loop to provide high loop gain and remove the need for auxiliary amplifier. Worst-Case simulation results confirms that the proposed comparator can detect 1.5mVolts input difference, at all process corners, in presence of 15mVolts input offset voltage, at 800MS/s comparison rate. The Monte-Carlo analysis for 100 iterations on input offset voltages shows that input referred offset would be improved to 150μV while was 6mVolts at 1σ before correction. Power consumption is 0.78mW at 800MS/s comparison speed. simulations are performed using the BSIM3 model of a 0.18μm CMOS technology.

关键词： Negative feedback Switches Latches Threshold voltage Power demand Semiconductor device modeling Periodic structures

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