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Development of Low-cost Wafer Level Package through Integrated design and simulation Analysis

Development of Low-cost Wafer Level Package through Integrat...

2011 12th International conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

作者： Tong Yan Tee In Soo Kang Haoyang Chen Glen Siew Serine Soh Jong Heon Kim Shan Gao Germaine Hoe Teck Kheng Lee Bok Leng Ser Hun Shen Ng Nepes Pte Ltd.12 Ang Mo Kio Street 65 Singapore 569060. Institute of Microelectronics.11 Science Park Road Singapore Science Park II Singapore 117685. Institute of Technical Education.201 Circuit Road Singapore 379498. SMARTS Technology LLP.Blk 425 Canberra Road #11-477 Singapore 750425.

Wafer level package (WLP) provides the smallest form factor to satisfy multifunctional device requirements along with improved signal integrity for today's latest handheld electronics. WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Three sizes of LCWLP are designed and simulated, prior to assembly and reliability tests. The structural design features electrical, mechanical and thermal simulations of LCWLP with three chip sizes and ball layout. simulation results show LCWLPs investigated are able to satisfy the functional and reliability requirements. Electrical simulation demonstrates that LCWLP with the same I/O counts but smaller package size, has better functional performance than FCBGA. Mechanical simulation indicates that wafer level warpage of all LCWLPs studied are within acceptable range for wafer level processes. For board level reliability, LCWLPs are expected to pass the thermal cycling test. Furthermore, LCWLPs are small in sizes with very low junction-to-case thermal resistance, able to keep the maximum junction temperature low and cool the chips during operations. Its thermal performance is strongly influenced by the chip size but independent of the Cu RDL density.

关键词： Resistance Copper Electronic packaging thermal management Junctions Semiconductor device modeling Semiconductor device reliability

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Rectangular Partially Adaptive Antenna Array in Real-Valued Arithmetic

Rectangular Partially Adaptive Antenna Array in Real-Valued ...

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Siberian conference on Control and Communications (SIBCON)

作者： Victor Djigan Russian Metrological Institute of Technical Physics and Radio Engineering Institute for Design Problems in Microelectronics of RAS Moscow Russia

ISBN: (纸本)9781665476294

Arithmetic complexity of the Adaptive Antenna Array (AAA) consists of two parts: the complexity of the beamforming (the AAA input signal weighting and combination) and the AAA weights computation (the adaptive algorithm). The beamforming complexity cannot be reduced because it depends on the number of the antennas/channels which are selected to ensure the required properties of the array. At the same time, if the number of the adaptively controlled weights is less than the total number of the array weights, the arithmetic complexity of the adaptive algorithm can be reduced. Such an AAA is called a partially adaptive one. In the case of the rectangular AAA the partial adaptation can be achieved by the combination of the signals received by the antennas of the rows and the columns of the array prior to the adaptive weighting. This reduces the adaptive algorithm complexity because the reduced number of the adaptively computed/controlled weights is required in this case. However if the receiving signals number (the informational one and the interfering ones) is less than the array rows and columns number the partially adaptive array provides the steady-state performance which is almost the same as that of the array with all adaptively controlled weights. If the AAA is a symmetrical one (the pairs of its weights, which correspond the antennas placed in the locations symmetrical relatively the array phase center, are complex conjugated to each other) then a further reduction of the arithmetic complexity might be achieved by means of the usage of the real-valued computations. The main steps of the development of the real-valued partially adaptive antenna array with the combination of the row and column signals are considered in this paper. The AAA architecture, its computational procedure and the results of the AAA simulation are also considered. This simulation demonstrates about 3 dB better cancellation of the interferences and about two times shorter transient response

关键词： Adaptation models Transient response Array signal processing Computational modeling Adaptive arrays Complexity theory Time factors

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Study of Two Control Strategies Based in Fuzzy Logic and Artificial Neural Network Compared with an Optimal Control Strategy Applied to a Buck Converter

Study of Two Control Strategies Based in Fuzzy Logic and Art...

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conference of the North American Fuzzy Information Processing Society - NAFIPS

作者： N. L. Diaz J. J. Soriano Laboratory for Automation Microelectronics and Computational Intelligence Universidad Distrital Francisco José de Caldas Bogota Colombia

The dc-dc converters are highly efficient tools used to supply power to different systems, they have a nonlinear behavior and variations at their main parameters could affect their stability. This document studies and compares different control strategies, linear and non linear controllers applied to a Buck converter. There are mainly three control strategies treated in this paper. First an optimal control based design, by employing The quadratic performance index (QPI) is used, second a knowledge based fuzzy control is studied and third an artificial neural network (ANN) as a dynamic emulator of the fuzzy control is proposed. Some comparisons about the systems composed by the plant and a controller, in variation of a few plant parameters were made; in addition the computational time in simulation is compared between the two intelligent controllers.

关键词： Optimal control Fuzzy logic Artificial neural networks Buck converters Fuzzy control DC-DC power converters Power supplies Stability Performance analysis Computational modeling

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Topology- and Resource-Based Distribution Scheme for Collaborative Security-Focused design Space Exploration in Large-Scale Static WSNs

Topology- and Resource-Based Distribution Scheme for Collabo...

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Australasian Telecommunication Networks and Applications conference, ATNAC

作者： Benjamin Förster Thomas Hinze Peter Langendorfer Cyber-Physical System Engineering IHP - Innovations for High Performance Microelectronics Frankfurt (Oder) Germany Brandenburg University of Technology Cottbus-Senftenberg Cottbus Germany Dpt. of Bioinformatics Faculty of Biological Sciences Matthias-Schleiden Institute University of Jena Jena Germany

ISBN: (数字)9798350379112

ISBN: (纸本)9798350379129

Security is a crucial aspect in wireless sensor networks (WSNs), ensuring protection of the network and its data against attackers. The resource-constrained nature of sensor nodes, however, poses a challenge for the implementation of security means. Instead of perfect security a trade-off between security, longevity and functional requirements is necessary. The problem of designing optimal security configurations for large-scale static WSNs, becomes even more complex when we intend to take advantage of the distributed nature. On the model of a neighbourhood watch, the advantage of distributed collaborative security is displayed, in which security coverage increases, while the individually induced workload for security tasks is reduced. Ensemble security frameworks provide similar solutions for WSNs by combining multiple security means. While they are capable of optimally utilising available resources to maximise security, they are highly specialised, hence not well adaptable to new applications and requirements. We propose a topology- and resource-based distribution scheme for the design of distributed collaborative security configurations in large-scale static WSNs. Further, we elaborate the application of our scheme and its suitability to be integrated into a design space exploration (DSE) concept. Moreover, we propose a DSE concept that combines exhaustive and heuristic exploration techniques and is able to integrate analytical and simulation models for evaluation. The computational efficiency of our distribution scheme is evaluated on lambda-precision unit disk graphs as models for WSNs with up to 300 nodes.

关键词： Wireless communication Wireless sensor networks Analytical models Computational modeling Collaboration Space exploration Computational efficiency Security Protection Optimization

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An Efficient Approach for Load Balancing in Vehicular Ad-hoc Networks

An Efficient Approach for Load Balancing in Vehicular Ad-hoc...

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IEEE International conference on Advanced Networks and Telecommuncations Systems

作者： Shubham Agarwal Avirup Das Nabanita Das Department of Electrical and Electronics Engineering Manipal Institute of Technology Manipal Manipal University India Institute of Radio Physics and Electronics University of Calcutta Kolkata India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)9781509021949

With the rapid increase in vehicular traffic in urban areas, optimal use of available resources is necessary to minimize the cost while maintaining the safety, and the quality of service. For this purpose, Vehicular Ad hoc Networks (VANETs) are emerging, connecting vehicles with static road side units (RSUs) serving as a backbone. For energy efficiency, vehicles may upload data to the nearest RSU by multi-hop routing via shortest paths. But it drains the energy of the nodes nearer to the RSU faster leading to frequent recharging of batteries. For cost-efficient design and longer battery life, both optimal placement of RSUs and uniform power dissipation of nodes are necessary in VANETs. In this paper, a novel approach of load balanced routing is proposed to improve the network stability and battery lifetime in individual nodes. Assuming variable energy levels of transmission in each vehicle, our analysis establishes some upper bounds on the separation of two consecutive RSUs for nearly load balanced routing. The problem has been defined for linear network with uniform distribution of vehicles over 1-D road. simulation studies show that the proposed scheme enhances the network performance significantly in terms of energy usage, network load and average packet delay.

关键词： Routing Roads Vehicular ad hoc networks Batteries Mathematical model Load modeling Load management

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System-Level Evaluation of AOS Gain Cell eDRAMs for Low-Power Normally-Off Computing

System-Level Evaluation of AOS Gain Cell eDRAMs for Low-Powe...

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International conference on Solid-State and Integrated Circuit Technology

作者： Long Chen Yecheng Yang Wei Li Shao Hao Wang School of Advanced Manufacturing Fuzhou University Fujian Jinjiang China FZU-Jinjiang Joint Institute of Microelectronics Fuzhou University Fujian Jinjiang China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

Recent gain cell (GC) embedded dynamic random access memory (eDRAM) using short channel length amorphous oxide semiconductor (AOS) field-effect transistors (FETs) has demonstrated extremely low leakage current and promising three-dimensional integrating capacity. This makes AOS-GC eDRAM a promising technology for normally-off computing applications. However, the lack of comprehensive models and evaluation approaches prevents the exploration and optimization of its design space. We presented a system-level simulation approach, GCSim, to perform power analysis for low-power scenarios. The results indicate that AOS-GC eDRAM can provide higher density, lower static power, and dynamic energy compared to static random access memory (SRAM) and silicon-based GC (Si-GC) eDRAM. For normally-off computing applications, such as the intermittent wake-up deep neural network (DNN), the quasi-nonvolatile AOS-GC eDRAM can achieve up to 96.7% energy savings compared to SRAM when the wake-up interval exceeds one second.

关键词： Integrated circuit technology Computational modeling Field effect transistors Energy conservation Random access memory Artificial neural networks Leakage currents Optimization

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A 10-Watts 0.5-6 GHz SPDT Switch in 0.13-µm CMOS SOI for 5G-Compatible IoT Applications

A 10-Watts 0.5-6 GHz SPDT Switch in 0.13-µm CMOS SOI for 5G...

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Cross Strait Quad-Regional Radio Science and Wireless Technology conference (CSQRWC)

作者： Shilin Shi Fanyi Meng Jianquan Hu Shouxian Mou Kaixue Ma School of Physics University of Electronic Science and Technology of China Chengdu Sichuan China School of Microelectronics Tianjin University Tianjin China

ISBN: (数字)9781728181813

ISBN: (纸本)9781728181820

This paper presents a high-power single-pole double-throw (SPDT) switch with a novel design methodology to achieve>10 Watts 1-dB compression point (P 1dB ) and low level of insertion loss for sub-6-GHz related applications. Implemented in a 0.13-μm silicon-on-insulator (SOI) CMOS process, the proposed switch adopts an all-positive alternative independent biasing technique to alleviate negative biasing voltage requirements in conventional high-power designs, avoiding that extra power consumption and noise introduced by the negative voltage generator while improved the power handling capability about 3 dB than conventional switches. The design has achieved 0.5~6 GHz operation band, 0.7~1 dB insertion loss, and 20~34 dB isolation. P 1dB is better than 42 dBm that covers majority of the high-power industrial scientific medical (ISM) and fifth-generation (5G) mobile applications. Stacked-FETs technique is co-designed to further enhance power handling capability. In post-layout simulation with passive components simulated with full-wave solver. The core area is as compact as 0.36×0.66 mm 2 .

关键词： Wireless communication Semiconductor device modeling 5G mobile communication Silicon-on-insulator Insertion loss CMOS process Switching circuits

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A high speed high precision linear drive system for manufacturing automation

A high speed high precision linear drive system for manufact...

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Annual IEEE conference on Applied Power Electronics conference and Exposition (APEC)

作者： M.S.W. Tam N.C. Cheung Department of Electrical Engineering Hong Kong Polytechnic University Hong Kong China

ISBN: (纸本)0780366182

High speed and high precision linear motions are found in many industrial applications, such as the wire-bonding and die-bonding of microelectronic components. In order to achieve the tight requirements of future-generation semiconductor packaging machines, a high-performance linear drive system is developed. The linear drive system consists of linear permanent magnet synchronous motors (LPMSM) and a DSP-based fully digital PWM drive. To achieve high trajectory accuracy, a dual-rate multi-loop cascade control structure with velocity and acceleration feed-forward is employed. Also, a velocity observer is used to provide reliable and ripple free feedback information. To increase the current dynamics, overrated momentary high-voltage and high-current are injected to the actuator's coils, through the PWM drive. Finally, to reduce mechanical resonance during the high-speed start-stop operations, a third-order profile generator is developed and employed in the motion path generation process. This paper describes the development of such a linear drive system. The paper includes: (i) the construction and modeling of the permanent magnet synchronous linear drive; (ii) the simulation of the linear drive and the control system; (iii) the design and hardware implementation of the linear drive system; and (iv) the implementation result. The final result shows that the system is capable of 15 G acceleration and 1 micron position accuracy.

关键词： Pulse width modulation Acceleration Semiconductor device manufacture Manufacturing industries microelectronics Packaging machines Permanent magnet motors Velocity control Feedforward systems Feedback

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Optimization of thermal load distribution in accelerated temperature cycling tests for solder joint lifetime qualification tests

Optimization of thermal load distribution in accelerated tem...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Jonas Gleichauf Youssef Maniar Roumen Ratchev Sebastian Spring Steffen Wiese Robert Bosch GmbH Corporate Sector Research and Advance Engineering Renningen Germany Tplus Engineering GmbH Leinfelden-Echterdingen Germany Saarland University Institute for Microintegration and Reliability Saarbrücken Germany

ISBN: (数字)9781728160498

ISBN: (纸本)9781728160504

The cost- and time-efficient qualification process of solder joints in automotive electronic assemblies requires accelerated temperature cycling (ATC) testing. Such tests, aiming to investigate durability of solder joints in increased temperature range, are usually performed in temperature chambers on component level. In typical chambers, heat transfer imposed onto tested assemblies is driven by convection causing circulation of airflow, resulting in inhomogeneous airflow velocity and temperature distributions. These effects are expected to affect the local thermal load imposed onto the solder joint and consequently solder joints in different locations of the temperature chamber could experience different load magnitudes. Finally, the higher the temperature gradients within the test setup, the higher scatter in solder lifetime data is expected. This study proposes an approach of a test setup thermally optimized using computational fluid dynamics (CFD) simulations aiming to reduce the influence of temperature deviations on the reliability of solder joints. A transient simulation approach is applied in order to optimize the local heat transfer on the test setup during thermal cycling. Furthermore, the effect of various heating and cooling gradients on the solder joint reliability is assessed in thermomechanical finite element (FE) simulation. It is shown, that the derived test bench design provides improved airflow conditions, which significantly homogenizes and increases the local heat transfer (HTC) on the component setup board due to forced convection. Finally, the decreased transient spatial temperature gradients are confirmed by temperature measurements.

关键词： Soldering Temperature distribution Heat transfer Thermal loading Iron Load modeling Testing

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Microfluidic design for bio-sample delivery to silicon nanowire biosensor - A simulation study

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Journal of Physics: conference Series 2006年第1期34卷 626-630页

作者： Tan, S.J. Lao, I.K. Ji, H.M. Agarwal, A. Balasubramanian, N. Kwong, D.L. Institute of Microelectronics Singapore Science Park II Singapore 117685 11 Science Park Road Singapore

We examine various microfluidic channel designs for sample delivery to silicon nano-wire biosensors pertaining to the modeling and simulation. Nano-wires with its high sensitivity permits label free detection of bio-molecules. Without careful considerations to its fluidic delivery network, effects of detection can be limited. Different micro-channel designs of relatively larger width aid in fluid release and sensors are placed strategically to attain high efficiency in bio-sample delivery. One design establishes the viability of hydrodynamic focusing through splitting a single flow into two and permits focusing of bio-samples at the flow recombination region. It avoids the delicated fluidic delivery systems generally used in hydrodynamic focusing. A focusing effect of 71.3% based on the movement of a massless particle in the fluid is achieved using a straight channel design with a partition wall inside. Moreover, sample is focused in low velocity region which maintains minimal impact to nanowire sensor. This provides a simple and efficient delivery system for the nano-wire sensor upon integration. © 2006 IOP Publishing Ltd.

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