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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1418 条记录，以下是251-260 订阅

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Mechanical modeling study for fan-out wafer level package parameters to enhance BGA TCoB life

Mechanical modeling study for fan-out wafer level package pa...

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Electronics Packaging Technology conference (EPTC)

作者： Rathin Mandal Chai Tai Chong Institute of Microelectronics 2 Fusionopolis Way #08-02 Innovis Singapore

ISBN: (纸本)9781665416207

Fan-Out Wafer Level Package (FOWLP) is experiencing a significant growth due to its thinner thickness, higher I/Os in smaller chip area, better thermal and electrical performance. Due to the shorter, finer and simpler interconnection as compare to flip chip, FOWLP shows superior performance. On the other hand this package is vulnerable due to its higher warpage and package stress concentration. This paper will explore different options to enhance board level reliability performance during temperature cycling for FOWLP. The mechanical simulation has been performed for board level temperature cycling reliability test on a uniform ball pitch, with/without UBM (under bump metallization), BGA with underfill, SACQ (bismuth bearing SnAgCu alloy) solder material and different package design factors (pad diameter, solder resist opening, silicon chip thickness, BGA height, etc). Our aim from this mechanical simulation is to find ways to enhance TCoB (temperature cycling on board) solder joint life performance for FOWLP to be used for antenna-in-package (AiP) automotive radar application. Among the different package parameters, UBM, SACQ solder, solder resist opening and larger BGA height are the few packaging parameters which significantly enhancing the BGA solder joint life. The most noticeable factor bismuth bearing SACQ shows more than 2x performance improvement whereas underfilling the BGA layer in the FOWLP package reduces solder join life significantly.

关键词： Semiconductor device modeling Temperature Thermomechanical processes Resists Bismuth Reliability engineering Silicon

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A comparative study of stress-based and fracture mechanics-based finite element simulation approaches for RDL based wafer level package

A comparative study of stress-based and fracture mechanics-b...

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Electronics Packaging Technology conference (EPTC)

作者： Sasi Kumar Tippabhotla Lin Ji Tai Chong Chai Institute of Microelectronics A*STAR (Agency for Science Technology and Research) 2 Fusionopolis Way Innovis Tower A Singapore

ISBN: (纸本)9781665416207

Conventional stress analysis (CSA) and fracture mechanics using cohesive zone modelling (CZM) approaches are currently available in the finite element analysis framework for virtual design evaluation of microelectronic packages. CSA exists for a long time and the CZM is currently being adopted widely, especially by the universities and R&D institutes. Both the approaches have their own advantages and challenges. In this scenario, a comparison of relative merits and limitations need to be evaluated to make efficient use of both the approaches in the package development process. Such a comparison aids the simulation engineers to gage the requirements of each approach and plan an affordable simulation strategy while maximizing the output. In this study we present a comparative evaluation of CSA approach and fracture mechanics approach using CZM for design evaluation of a simple fan-out wafer level package. We show the requirements (mechanical properties and mechanical and fracture strength details of materials) and merits (prediction capabilities) of both the approaches and thus gauge their viability and suitability for different design stages. We also show the specific advantages and challenges of CZM approach. We conclude that the CZM method enhances the virtual product development process through its capability of predicting the likeliness of delamination and damage. However, this approach has the prerequisite of fracture properties of the material interfaces. The initial (conceptual/preliminary) development phases of a new package require evaluation of a large number of candidate materials, processes and designs and the fracture strength (interface/bulk) data for all the material/process combinations are seldom available. The CSA approach is more suitable for such situation to narrow down the product parameters by comparative analysis. The candidate designs thus narrowed down can be simulated using CZM approach to evaluate the likeliness of delamination and modific

关键词： Semiconductor device modeling Analytical models Temperature Systematics Product development Finite element analysis Delamination

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Automated Parameter Extraction and SPICE Model Modification For Gate Enclosed MOSFETs simulation 16

Automated Parameter Extraction and SPICE Model Modification ...

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16th International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD) / 15th conference on PhD Research in microelectronics and Electronics (PRIME)

作者： Contreras, Boris Ducoudray, Gladys Palomera, Rogelio Bernal, Carlos Univ Puerto Rico Dept Elect & Comp Engn Mayaguez PR 00681 USA

ISBN: (纸本)9781728112015

This work focuses in using experimental measurements to extract the aspect ratio (W/L) for Gate-Enclosed or Annular MOSFETs. All measurements and calculations are performed with an automated virtual instrumentation (VI) environment developed in LabVIEW. The VI was capable of extracting threshold voltage and low field mobility, needed for W/L calculation. An extraction procedure for the body effect factor is also presented. For validation purposes, extracted parameters were compared with those provided by the foundry (MOSIS) using traditional rectangular transistors. The extracted W/L was validated by comparing to Giraldo's experimental method. The SPICE BSIM 3 model parameters provided by the foundry is then modified using the extracted parameters including the aspect ratio. With this modification better simulation results were obtained. They were compared to the experimental measurements for an annular MOSFET drain voltage vs drain current characteristic curves at different gate voltages, showing an improvement of 58% when compared to the original non modified SPICE model parameters.

关键词： SPICE

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Dual Mode Ion Mobility Spectrometer High Voltage Formation Circuit 31

Dual Mode Ion Mobility Spectrometer High Voltage Formation C...

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IEEE 31st International conference on microelectronics (MIEL)

作者： Gromov, E. Matusko, M. Shaltaeva, Y. Pershenkov, V. Belyakov, V. Golovin, A. Malkin, E. Ivanov, I. Vasilyev, V. Natl Res Nucl Univ MEPhI Moscow Engn Phys Inst Inst Nanotechnol Elect Spintron & Photon Kashirskoe Shosse 31 Moscow 115409 Russia

ISBN: (纸本)9781728134192

It was designed dual mode ion mobility spectrometer high voltage formation circuit. The circuit design includes simulation of the dynamic formation of a sinusoidal signal. The simulation of the dynamic formation of a sinusoidal signal is investigated. It is characterized by a high voltage multiplier and several variants of a voltage smoothing filter.

关键词： Ions High-voltage techniques Spectroscopy Switches Transistors Optical filters Integrated circuit modeling

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On Intelligent Agent-Based simulation of Network Worms Propagation 15

On Intelligent Agent-Based Simulation of Network Worms Propa...

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15th IEEE International conference on the Experience of designing and Application of CAD Systems (CADSM)

作者： Chumachenko, Dmytro Yakovlev, Sergiy Natl Aerosp Univ Kharkiv Aviat Inst Dept Math Modeling & Artificial Intelligence Kharkiv Ukraine

ISBN: (纸本)9781728100531

To assess the propagation behavior of network worms, it is advisable to use modeling techniques. Existing models are based on deterministic approaches, which does not allow to take into account the dynamic nature of the development of the malware epidemic process. A multi-agent network worm propagation model has been developed, for example, the Code Red worm, which eliminates the disadvantages of deterministic analytic models. The simulation results allow you to accurately repeat the dynamics of the real behavior of the Code Red worm, and can be used to study the behavior of other network worms.

关键词： simulation of epidemic process malicious software network worm agent-based simulation multi-agent simulation Code Red

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simulation of Ternary CMOS Schemes for Many-Valued Logic Systems 31

Simulation of Ternary CMOS Schemes for Many-Valued Logic Sys...

引用

IEEE 31st International conference on microelectronics (MIEL)

作者： Krasnyuk, A. A. Prozorova, A. G. Russian Acad Sci Sci Res Inst Syst Anal Nakhimovsky Pr 36-1 Moscow 117218 Russia Natl Res Nucl Univ MEPhI Moscow Engn Phys Inst Kaslurskoe Sh 31 Moscow 115409 Russia

ISBN: (纸本)9781728134192

Of interest is the possibility of implementing many-valued logic systems using traditional CMOS tecluiologies. We considered an example of the implementation of three-valued logic elements based on symmetric 3vL, logic using the values {-,0,+}, {-1.0, +1}, {1,0,1}, {i, 0, 1} etc. From the totality of obtained results, it can be assumed that ternary CMOS logic can be fully implemented according to norms of 28-180 mu with minimal changes for design rules.

关键词： Transistors Solid modeling Switching circuits Semiconductor device modeling Inverters Standards Resistance

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Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits 16

Efficient generation of data sets for one-shot statistical c...

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作者： Cilici, Florent Leger, Gildas Barragan, Manuel J. Mir, Salvador Lauga-Larroze, Estelle Bourdel, Sylvain Univ Grenoble Alpes CNRS Grenoble INP TIMA F-38000 Grenoble France Univ Grenoble Alpes RFIC Lab Grenoble INP F-38000 Grenoble France Univ Seville IMSE CNM CSIC Seville 41092 Spain

ISBN: (纸本)9781728112015

Millimeter-wave circuits in current nanometric technologies are especially sensitive to process variations, which can seriously degrade the device behavior and reduce fabrication yield. To tackle this issue, conservative designs and large design margins are widely used solutions. Another approach consists in introducing variable elements, also called tuning knobs, to allow post-fabrication tuning. One-shot statistical calibration techniques take advantage of advanced machine learning regression tools to propose a set of tuning knobs values that enhance the circuit performance based on simple measurements. Training the regression models require a huge amount of data covering the device performances, the effect of the tuning knobs and the simple measurements that guide the regression. In this work, we propose an efficient method for generating such a data set that reduces noticeably the size of the required training set for an accurate calibration.

关键词： Tuning Calibration Training data Machine learning Monte Carlo methods Integrated circuit modeling Data models

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A modeling Approach for 7nm Technology Node Area-Consuming Circuit Optimization and Beyond 16

A Modeling Approach for 7nm Technology Node Area-Consuming C...

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作者： Huo, Qiang Wu, Zhenhua Zhang, Feng Li, Ling Chinese Acad Sci Key Lab Microelect Devices & Integrated Technol Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781728112015

This work presents a novel statistical-based general compact model for 7nm technology node devices like FinFETs. Unlike conventional compact model based on less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of high accuracy, strong scaling capability, good robustness and excellent transfer capability. It is demonstrated that the performance of 6T SRAM and RC control ESD power clamp through the trade-off between two key design knobs of FinFET can be improved extremely with implementation of the newly proposed general compact model. This framework is also suitable for path-finding researches on 5nm node gate-all-around devices, like nanowire FETs, nanosheet FETs and beyond.

关键词： General compact model FinFETs Circuit Optimization 7nm technology node and beyond

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Optical micro-machined ultrasound sensors with a silicon photonic resonator in a buckled acoustical membrane 20

Optical micro-machined ultrasound sensors with a silicon pho...

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20th International conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in microelectronics and Microsystems (EuroSimE)

作者： Westerveld, W. J. Leinders, S. M. van Neer, P. L. M. J. Urbach, H. P. de Jong, N. Verweij, M. D. Rottenberg, X. Rochus, V. IMEC Kapeldreef 75 B-3001 Leuven Belgium Delft Univ Technol Dept ImPhys Lorentzweg 1 NL-2628 CJ Delft Netherlands TNO Oude Waalsdorperweg 63 NL-2597 AK The Hague Netherlands

ISBN: (纸本)9781538680407

Future applications of ultrasonography in (bio-)medical imaging require ultrasound sensor matrices with small sensitive elements. Promising are opto-mechanical ultrasound sensors (OMUS) based on a silicon photonic ring resonator embedded in a silicon-dioxide acoustical membrane. This work presents new OMUS modelling: acousto-mechanical non-linear FEM and photonic circuit equations. We show that initial wafer stress needs to be considered in the design: the acoustical resonance frequency changes considerably and OMUS sensitivity differs for up- or downwards buckled membranes. Simulated acoustical resonance frequency agrees well with measurements, assuming realistic SOI wafer stress. Measured sensitivity showed large device-to-device variation and simulations agree within this order of magnitude. We conclude that careful modeling of stress is necessary for the design of robust and sensitive sensors.

关键词： conferences microelectronics Micromechanical devices

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Long-Term Reliability Management For Multitasking GPGPUs 16

Long-Term Reliability Management For Multitasking GPGPUs

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作者： Sun, Zeyu Kim, Taeyoung Chow, Marcus Peng, Shaoyi Zhou, Han Kim, Hyoseung Wong, Daniel Tan, Sheldon X-D Univ Calif Riverside Dept Elect & Comp Engn Riverside CA 92521 USA Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781728112015

This paper proposes long-term reliability management for spatial multitasking GPU architectures. Specifically, we focus on electro-migration (EM)-induced long-term failure of the GPU's power delivery network. A distributed power delivery network model at functional unit granularity is developed and used for our EM analysis of GPU architectures. We use a recently proposed physics-based EM reliability model and consider the EM-induced time-to-failure at the GPU system level as a reliability resource. For GPU scheduling, we mainly focus on spatial multitasking, which allows GPU computing resources to be partitioned among multiple applications. We find that the existing reliability-agnostic thread block scheduler for spatial multitasking is effective in achieving high GPU utilization, but poor reliability. We develop and implement a long-term reliability-aware thread block scheduler in GPGPU-Sim, and compare it against existing reliability-agnostic scheduler. We evaluate several use cases of spatial multitasking and find that our proposed scheduler achieves up to 30% improvement in long-term reliability.

关键词： Reliability Graphics processing units Power system reliability Multitasking Wires Instruction sets Computational modeling

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