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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是301-310 订阅

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LSTM-RNN Based Analog IC Automated Sizing Model for Operational Amplifier and VCO

LSTM-RNN Based Analog IC Automated Sizing Model for Operatio...

引用

International conference on Integrated Circuits and Microsystems (ICICM)

作者： Zihan Yang Wensi Wang Zhijie Chen Qianhui Fan Xuanchong Chen College of Microelectronics University of Technology Faulty of Information Technology Beijing Beijing China

ISBN: (数字)9781728189789

ISBN: (纸本)9781728189796

Artificial intelligence and machine learning have been widely used to replace human work. Analog integrated circuit design needs to adjust a large number of circuit parameters to satisfy the balance between various performance metrics, which now mostly rely on the experience of designers and sometimes of the intuitions. Machine learning has demonstrated the potential to aid the design of analog integrated circuits in the literature, whilst most of them adopted particle swarm intelligence and Bayesian optimization. However, the model training time and simulation run time are substantial when any circuit structure modification occurs. In this paper, Recurrent Neural Network (RNN) was used to automatically optimize the parameters sizing by giving requested performance. Training data sets for the RNN of component parameters and circuit performance were simulated using Cadence Spectre. After training for only 15 minutes, RNN learns to predict parameters by inputting gain, bandwidth, power and frequency, which can make critical circuit design decision significantly faster. The reliability and applicability of the algorithm was verified through the parameter prediction of integrated operational amplifier and VCO.

关键词： Training Recurrent neural networks Integrated circuit modeling Neural networks Optimization Logic gates Deep learning

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Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging

Frequency Domain Methodology for Evaluating Signal Integrity...

引用

Electronics Packaging Technology conference (EPTC)

作者： Li Kangrong Mihai Dragos Rotaru Institute of Microelectronics ASTAR Singapore

ISBN: (数字)9781728189116

ISBN: (纸本)9781728189123

A novel methodology to evaluate the signal integrity (SI) performance of logic to logic and high bandwidth memory (HBM) interconnect model for chiplet packaging is proposed. Compared with the traditional S parameters and eye diagram analyses, the proposed methodology reflects the actual SI performance under the capacitive termination condition, takes much shorter simulation time and provides more insightful SI evaluation, which is suitable for logic to logic and HBM interconnect design and optimization. The S parameters analysis are not sufficient for the cases like logic to logic and HBM interconnect models, which are unterminated (capacitive loading). The eye diagram analysis cannot provide an insightful guideline for optimization of interconnect model. Besides, eye diagram simulations to find the optimum interconnect model are very time consuming, as a frequency domain to time domain via an inverse fast Fourier transformation (FFT) is required. Compared with the eye diagram analysis, the proposed methodology only analyses the SI performance in frequency domain rather than in time domain, so the simulation time is reduced. The proposed methodology can overcome the drawbacks of the S parameters and eye diagram analyses and provide an in-depth and fast evaluation on the SI performance of logic to logic and HBM interconnect models frequently encountered in advanced system in package using chiplets.

关键词： Analytical models Frequency-domain analysis Integrated circuit interconnections Scattering parameters Time-domain analysis Signal integrity Load modeling

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Board Level Solder Joint Reliability design and Analysis of FOWLP

Board Level Solder Joint Reliability Design and Analysis of ...

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Electronics Packaging Technology conference (EPTC)

作者： Xiaowu Zhang Boon Long Lau Haoran Chen Yong Han Ming Chinq Jong Sharon Pei Siang Lim Simon Siak Boon Lim Xiaobai Wang Yosephine Andriani Songlin Liu Institute of Microelectronics (IME) A*STAR (Agency for Science Technology and Research) Singapore Institute of Materials Research and Engineering (IMRE) A*STAR (Agency for Science Technology and Research) Singapore

ISBN: (数字)9781728189116

ISBN: (纸本)9781728189123

This paper presents a comprehensive board level solder joint reliability study under thermal cycling (TC) loading by both numerical simulation and experimental test. TC profile is from -40°C to 125°C. In numerical simulation, both epoxy molding compound (EMC) and dielectric are modeled as viscoelastic materials. SAC is modeled as a creep material while the remaining materials are assumed to be elastic. The critical solder joint location predicted by modeling agrees well with the experimental result. Results show: (1) lower CTE PCB improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB CTE is reduced from 17 ppm/°C to 10ppm/°C; (2) thinned PCB thickness improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB thickness is reduced from 1.5 mm to 1 mm. Finally, life prediction model for solder joints of FOWLP has been successfully established as well.

关键词： Soldering Reliability Creep Semiconductor device reliability Strain Packaging Predictive models

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Transfer Molding simulation to Predict Filling Flaws and Optimize Package design

Transfer Molding Simulation to Predict Filling Flaws and Opt...

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European microelectronics and Packaging conference, EMPC

作者： M. Rovitto A. Cannavacciuolo STMicroelectronics via C. Olivetti 2 Agrate Brianza (MB) Italy

The process of microchip encapsulation by epoxy resin injection is simulated by employing moldflow modeling. In this work, the use of modeling allows to reproduce the unbalanced flow behavior of the resin within the mold cavity during the filling stage which leads to the formation of voids in the molded package. simulation results are compared to experimental findings, in which the molding process is interrupted at designed points in time. Comparison shows good agreement between numerical outputs and experimental data and demonstrates the effectiveness of the model. After modeling is validated, the numerical methodology is applied to optimized package design in order to minimize the risk of issues caused by the filling stage. As a result, geometric variations show a significant effect on filling front progression avoiding the generation of structural defects during molding process.

关键词： Filling Electromagnetic compatibility Solid modeling Resins Encapsulation Welding Electronics packaging

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Electrical characterization and design of hyper-dense interconnect on HD-FOWLP for die to die connectivity for AI and ML accelerator applications

Electrical characterization and design of hyper-dense interc...

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Electronics Packaging Technology conference (EPTC)

作者： Mihai Dragos Rotaru Li Kangrong Institute of Microelectronics ASTAR Singapore

ISBN: (数字)9781728189116

ISBN: (纸本)9781728189123

High Density Fan Out Wafer Level Package (HD-FOWLP) can be an alternative for technologies such as Embedded Multi-Die Interconnect Bridge (EMIB) and silicon interposer to achieve heterogeneous integration for applications that requires ultra-high bandwidth for die to die communications. This work focusses on the electrical characteristics of this type of interconnect and explains why the metrics based on S-parameters regularly used for designing and qualifying interconnects on substrates and PCBs are not enough and may be misleading in this case. With the lines cross-sectional dimensions of, 1umx1um and respectively and Nyquist frequency around 1GHz, some of these lines operate at the onset of skin effect, with per-unit-length resistance and inductance undergoing severe dispersion. This is very different from signals routed as thicker and wider traces on an organic package, where the skin effect develops at much lower frequencies. It is also different from the on-die signal routing, where RC is an adequate model of the signal interconnect. simulation examples of different interconnect structures and layouts are presented to support the findings reported here.

关键词： Couplings Impedance Attenuation Microstrip Bandwidth Scattering parameters Integrated circuit modeling

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modeling and simulation of Novel GaN-based Light Emitting Transistor for Display Applications 14

Modeling and Simulation of Novel GaN-based Light Emitting Tr...

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15th International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD) / 14th conference on PhD Research in microelectronics and Electronics (PRIME)

作者： Lee, Sang Myung Yun, Ilgu Yonsei Univ Elect & Elect Engn Seoul South Korea

ISBN: (纸本)9781538653869

For the research of next-generation displays, technology of shrink device size is the most attractive and important technology. It is possible to manufacture high-performance display products by using high integrated devices such as mobile application. However, there is a certain limitation to the downsizing technology. Therefore, new device synthesis techniques are becoming important. In this paper, we propose a device design that combines inorganic material based light-emitting diode (LED) and thin-film transistor (TFT). By integrating the LED and TFT devices into one region, it is possible to highly integrate the devices, which can greatly reduce the size of the entire device. To investigate a possibility of device implementation, technology computer-aided design (TCAD) simulation is used. After that, an optical and electrical characteristic of the device are analyzed. Finally, the light-emitting transistor (LET) is proposed.

关键词： inorganic LET TCAD simulation and modeling device prototype implementation

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ToPoliNano & MagCAD: a Complete Framework for design and simulation of Digital Circuits based on Emerging Technologies 15

ToPoliNano & MagCAD: a Complete Framework for Design and Sim...

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作者： Garlando, Umberto Riente, Fabrizio Vergallo, Deborah Graziano, Mariagrazia Zamboni, Maurizio Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy

ISBN: (纸本)9781538651537

Evaluating the performance of beyond CMOS devices poses many challenges to the research community. Several works analyze emerging technologies at device level;nonetheless an architectural design space exploration is fundamental to understand their potential. We present a design framework for emerging technologies, consisting of two tools ToPoliNano and MagCAD. It provides a top-down design flow and a methodology enabling the architectural exploration of emerging devices.

关键词： Tools Integrated circuit modeling Layout Windows CMOS technology Libraries Semiconductor device modeling"

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Fast converter simulation method including parasitic nonlinear capacitances 15

Fast converter simulation method including parasitic nonline...

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作者： Schmidt, Eva Duerbaum, Thomas Friedrich Alexander Univ Erlangen Nuremberg Chair Electromagnet Fields Erlangen Germany

ISBN: (纸本)9781538651537

Converter topologies of Switch Mode Power Supplies, for example in consumer products, have to fulfill many specifications and demands especially in matters of efficiency and low overall costs. In order to optimize these converters, simulation methods have to be found that predict their real behavior accurately within short simulation time. However, simulation accuracy often suffers from neglection of nonlinear component characteristics, especially nonlinear capacitances associated with semiconductor devices. Integrating them in Sample Data modeling generates a simulation method that achieves both goals, short simulation durations and results close to reality.

关键词： Sampled Data modeling nonlinear piece wise constant capacitance

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A Fluctuation Model of a Hf02 RRAM Cell for Memory Circuit designs

A Fluctuation Model of a Hf02 RRAM Cell for Memory Circuit D...

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International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD)

作者： Feng Zhang Linan Li Qiang Huo Cong Fang Wenqiang Ba Key Laboratory of Microelectronics Devices and Integrated Technology Chinese Academy of Sciences Beijing China School of Electronic and Information Engineering Beijing Jiaotong University Beijing P.R. China

ISBN: (纸本)9781728112022

A resistive random access memory device based on HfO 2 with outstanding nonvolatility is fabricated. A dynamic Verilog-A model obeying the electrochemical metallization conductive filament mechanism is demonstrated. The fluctuation of conductive filament growth is added to this model, and the model is verified by DC voltage scanning. The simulation and experimental data are compared using data processing software. Experimental results verify the good electrical characteristics of the RRAM device. modeling of the fluctuations of RRAM devices provides guiding significance to the design of peripheral circuits.

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Electrical modeling and Analysis of Through-Silicon-Via Crosstalk Based on Scalable Physical Lumped Circuit Model for 3D Packaging

Electrical Modeling and Analysis of Through-Silicon-Via Cros...

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European microelectronics and Packaging conference, EMPC

作者： Xiangyang Shi Rong Zeng Liming Lv China Academy of Engineering Physics Institute of Electronic Engineering Mianyang China

In this paper, we investigate the transportation mode of TSV structure for subsequent modeling G-S TSVs. Next, a scalable physical lumped circuit model of ground-signal TSVs is established The scalable G-S TSVs model is developed with closed-form analytic RLGC equations derived from physical structure, and can be changed with structure parameters in design process accordingly. The validity of this model is verified with full-wave FEM-based simulator up to 20 GHz. Based on this accurate physical lumped circuit model, we investigate crosstalk of TSV array in both frequency domain and time domain. The method of modeling and analysis of TSV array crosstalk proposed in this paper can effectively reduce simulation time and computing resource over finite-element-based 3-D full-wave simulation.

关键词： Through-silicon vias Integrated circuit modeling Crosstalk Mathematical model Analytical models Silicon Computational modeling

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