This paper presents an automatic matched devices layout generation tool. An adapted form of genetic optimization is used to minimize the overall systematic mismatch due to oxide gradients and Shallow Trench Isolation ...
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ISBN:
(纸本)9781538651537
This paper presents an automatic matched devices layout generation tool. An adapted form of genetic optimization is used to minimize the overall systematic mismatch due to oxide gradients and Shallow Trench Isolation (STI) effect. A new STI evaluation methodology is introduced based on simulation and foundry models. The tool is capable of generating a current mirror or capacitor array layout pattern with optimal systematic mismatch and STI mismatch.
This paper demonstrates the characterization and modeling of an antenna to predict its effect when used in a digital communication system. The technique was applied to a commercial dual-band antenna. An equivalent cir...
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ISBN:
(纸本)9781538651537
This paper demonstrates the characterization and modeling of an antenna to predict its effect when used in a digital communication system. The technique was applied to a commercial dual-band antenna. An equivalent circuit model was derived to characterize the antenna behavior in the frequency domain. A time domain system model was also derived to enable the estimation of the antenna effects in a digital system. The results show that the antenna caused symbol scattering and contributed to the error vector magnitude.
A numerical approach to model fatigue damage propagation in metal-on-silicon structures under transient thermal loading is presented. The considered fatigue failure mechanisms are fatigue crack growth inside the thick...
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ISBN:
(纸本)9781538623596
A numerical approach to model fatigue damage propagation in metal-on-silicon structures under transient thermal loading is presented. The considered fatigue failure mechanisms are fatigue crack growth inside the thick metallization and potential cyclic delamination growth at the interface between the metallization and the silicon. Advanced methods within the framework of the Finite Element Method are developed to study these failure mechanisms and to assess the material and interface degradation on a generic metal-onsilicon geometry. Such methodology can be applied to explore fatigue-determined robustness limits of power semiconductor devices exposed to severe temperature swings, e.g. during cyclic electric overload switching.
In this paper, an automated extraction method to optimize the thermal conductivity of silicon is proposed. The approach is based on the electrical and thermal co-simulation of SiGe HBTs. The bisection method is used t...
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ISBN:
(纸本)9781538623596
In this paper, an automated extraction method to optimize the thermal conductivity of silicon is proposed. The approach is based on the electrical and thermal co-simulation of SiGe HBTs. The bisection method is used to optimize silicon conductivity values. The optimized material stack is embedded in the process design kit and allows designers to perform computing of the full-chip temperature profile and get accurate simulation results. The overall investigation is confirmed by measurements performed on bulk-silicon HBTs. Comparison between the simulations and the measurements shows that the maximum mismatch of %5 is achieved for the RTH values.
Medical implant devices have been widely used in recent years. The Super-Regenerative Receiver has been on preferred architecture due to its power advantage over other architectures. We present a detailed analysis of ...
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ISBN:
(纸本)9781538653869
Medical implant devices have been widely used in recent years. The Super-Regenerative Receiver has been on preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equivalent models to be used in system level design of a Super-Regenerative Receiver in this paper. designs were carried out in UMC 180nm process with a center frequency of 416MHz for MedRadio band. The study is concluded with the simulation results of the circuits and the equivalent models.
MATLAB/Simulink modeling of offset and flicker noise in Delta-Sigma modulators has been developed, providing a fast tool for the estimation of ADC performances. Since high accuracy and resolution are fundamental in se...
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ISBN:
(纸本)9781538651537
MATLAB/Simulink modeling of offset and flicker noise in Delta-Sigma modulators has been developed, providing a fast tool for the estimation of ADC performances. Since high accuracy and resolution are fundamental in sensor applications, a brief analysis of the main noise sources in second order Delta-Sigma modulators is presented, together with the typical solutions found in the literature. Generalization of system-level chopper technique for the rejection of the converter overall offset and low-frequency noise has been proposed and their effectiveness is evaluated by means of high-level simulations.
Testability analysis of linear time-invariant networks under the single-fault scenario is considered in this paper. To this end an interesting technique is proposed which does not require the analytic expression of th...
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ISBN:
(纸本)9781538651537
Testability analysis of linear time-invariant networks under the single-fault scenario is considered in this paper. To this end an interesting technique is proposed which does not require the analytic expression of the input-to-output network function. It is based on a fault model in the complex plane. The validity of the developed method is proved through applicative examples. A comparison with other similar techniques is also included.
This work reports on an universal lumped element model for integrated millimeter-wave (mmWave) transformers which is valid up to 100 GHz. The presented 2-pi architecture covers the calculation of planar and stacked tr...
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ISBN:
(纸本)9781538651537
This work reports on an universal lumped element model for integrated millimeter-wave (mmWave) transformers which is valid up to 100 GHz. The presented 2-pi architecture covers the calculation of planar and stacked transformer topologies as well as higher winding ratios and different geometries. All model components depend both on the transformer dimensions and technological parameters. A verification by electromagnetic field simulations in a 65 nm CMOS process results in a close agreement to the calculated S-parameter set.
The power elements are the weak parts of integrated circuits (ICs), in fact, through these elements the power is usually dissipated as heat with unavoidable thermal and mechanical stress. On the contrary the logic par...
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The power elements are the weak parts of integrated circuits (ICs), in fact, through these elements the power is usually dissipated as heat with unavoidable thermal and mechanical stress. On the contrary the logic parts of ICs stay at lower temperatures. This gives rise to two effects: the non-uniform generation of the heat across the die and the temperature gradients. Understanding these phenomena is very important to choose the right location of sensitive components, like thermal sensors, in order to improve reliability. As a consequence, the knowledge of the temporal evolution of the temperature distribution plays a very important role to improve both design and lifetime. Here we show how a single IR sensor based experimental setup is suitable to catch very fast thermal events performing high spatial resolution. We demonstrate the effectiveness of the method maps for three IC samples where an accurate thermal modeling for reliability has been obtained and validated, greatly improving the overall quality.
This paper presents simulation results of a CMOS switching mode power amplifier (SA) in a 65 nm technology with adjustable output voltage swing. The output stage is built in a stacked design to prevent dielectric brea...
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ISBN:
(纸本)9781538653869
This paper presents simulation results of a CMOS switching mode power amplifier (SA) in a 65 nm technology with adjustable output voltage swing. The output stage is built in a stacked design to prevent dielectric breakdown of the transistors. Inverters at the top and bottom of the stack provide the supply voltage for the stack. The configuration offers a variable output voltage swing between one, two or three times the nominal transistor supply voltage. This paper demonstrates the advantages over a power amplifier with fixed output levels for signals with high peak to average output power ratio (PAPR).
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