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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是471-480 订阅

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A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)

A Novel Method for Air-Gap Formation around Via-Middle (VM) ...

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Electronic Components and Technology conference (ECTC)

作者： King-Jien Chui Woon Leng Loh Xiangyu Wang Zhaohui Chen Mingbin Yu Institute of Microelectronics A*STAR (Agency for Science Technology and Research) Singapore

Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active CMOS devices through the formation of embedded air-gaps. As the air-gaps are embedded in the Si, stress isolation can be done without compromising on the usable Si area. Formation of the air-gaps have been demonstrated experimentally using a high temperature anneal in a de-oxidizing ambient. Stress reduction in the Si lattice, in the presence of the embedded air-gaps, will be studied through thermo-mechanical stress simulation. Effect of the impact of air-gap design will also be discussed.

关键词： Air gaps Silicon Through-silicon vias Stress Annealing Atmospheric modeling Surface treatment

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Aerospace-Electronics Reliability-Assurance (AERA): Three-Step Prognostics-and-Health-Monitoring (PHM) modeling Approach 17

Aerospace-Electronics Reliability-Assurance (AERA): Three-St...

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17th International conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in microelectronics and Microsystems (EuroSimE)

作者： Suhir, E. Portland State Univ Portland OR 97207 USA Vienna Univ Technol Vienna Austria Ariel Univ Ariel Israel ERS Co 727 Alvina Ct Los Altos CA 94024 USA

ISBN: (纸本)9781509021062

When encountering a particular reliability problem at the design, fabrication, testing, or an operation stage of an electronics product's life, and considering the use of predictive modeling to assess the seriousness and possible consequences of its detected malfunction and likely failure, one has to choose whether a statistical, or a physics-of failure -based, or a suitable combination of these two major predictive modeling tools should be employed to address the problem and to decide on how to proceed. An effective aerospace-electronics reliability-assurance (AERA) approach is suggested as a possible way to go in such a situation. In this approach the classical statistical Bayes formula (BF) is used at the first step as a technical diagnostics (TD) tool, with an objective to identify, on the probabilistic basis, the faulty (malfunctioning) device(s) from the obtained prognostics-and-health-monitoring (PHM) signals ("symptoms of faults"). The physics-of failure -based Boltzmann-Arrhenius-Zhurkov's (BAZ) equation, a powerful, flexible and physically meaningful modeling tool suggested about five years ago can be employed at the second step with an objective is to assess the remaining useful life (RUL) of the malfunctioning device(s). If the predicted RUL is still long enough, no action might be needed, but if not, a corrective (restoration) action becomes necessary. It is shown in this connection how short/long the repair time should/could be, so that the availability of the equipment (the probability that it is sound and available to the user when needed) does not fall below the allowable level. In any event, after the first two steps of the AERA modeling effort are carried out, and the assessed probability of the product's continuing operation is found to be satisfactory, the device is put back into operation (testing). If failure nonetheless occurs, the third AERA step should be undertaken to update reliability. A well-known four-parametric statistical beta-distri

关键词： Systems engineering

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A novel three-jet microreactor for localized metal-organic chemical vapour deposition of gallium arsenide: design and simulation 3

A novel three-jet microreactor for localized metal-organic c...

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3rd International School and conference on Optoelectronics, Photonics, Engineering and Nanostructures (Saint Petersburg OPEN)

作者： Konakov, S. A. Krzhizhanovskaya, V. V. Peter Great St Petersburg Polytech Univ Dept Phys Chem & Microsyst Technol St Petersburg 195251 Russia Univ Amsterdam NL-1098 XH Amsterdam Netherlands ITMO Univ St Petersburg Russia

We present a novel three-jet microreactor design for localized deposition of gallium arsenide (GaAs) by low-pressure Metal-Organic Chemical Vapour Deposition (MOCVD) for semiconductor devices, microelectronics and solar cells. Our approach is advantageous compared to the standard lithography and etching technology, since it preserves the nanostructure of the deposited material, it is less time-consuming and less expensive. We designed two versions of reactor geometry with a 10-micron central microchannel for precursor supply and with two side jets of a dilutant to control the deposition area. To aid future experiments, we performed computational modeling of a simplified-geometry (two-dimensional axisymmetric) microreactor, based on Navier-Stokes equations for a laminar flow of chemically reacting gas mixture of Ga(CH3)(3)-AsH3-H-2. simulation results show that we can achieve a high-rate deposition (over 0.3 mu m/min) on a small area (less than 30 mu m diameter). This technology can be used in material production for microelectronics, optoelectronics, photovoltaics, solar cells, etc.

关键词： Gallium arsenide

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Spot defect modeling: Past and evolution

Spot defect modeling: Past and evolution

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International conference on design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Michel Renovell LIRMM CNRS/Université de Montpellier

ISBN: (纸本)9781509063789

With today manufacturing technology, it is not possible to eliminate all defects and ensure every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. Different Test Strategies are commonly used since none is considered as optimal in terms of low defect level. Most companies use some but not all of the following three Test Strategies: the Static Voltage strategy, the Dynamic Voltage or Delay strategy, the Static or Dynamic Current (I_DDX) strategy. While using different approaches, these different test strategies have a common objective: reveal the presence in the chip of defects or deviations that may create a dysfunction. Knowing the complexity of today defects, it is admitted that the classical fault models used for test generation cannot guarantee a satisfactory detection of defects. This implies that new test generation technique specifically oriented to defects have to be defined. So, we must analyze and understand the electrical behavior of the defect and describe its behavior through an adequate `defect model'. Then, defect simulation techniques and defect-oriented ATPG techniques must be proposed to allow specific test generation for these defects. This presentation focuses on spot defects that manifest themselves as shorts or opens in the interconnect or in the MOS transistors: `Interconnect open', `Interconnect short', `Floating gate', and `Gate-Oxide-Short' are analyzed in detail using different model levels. For every defect, it is shown that the electrical behavior is in fact not predictable due to the presence of random parameters. In order to tackle the problem of unpredictability, unified concepts are proposed that allow new test generation techniques guaranteeing coverage of unpredictable defects.

关键词： Analytical models Computer science microelectronics Manufacturing Companies Delays Complexity theory

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Unified and efficient power integrity impedance target flow for flexible PCB design

Unified and efficient power integrity impedance target flow ...

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International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT)

作者： Denis Chen Jimmy Hsiao Yun Ling Chi-Te Chen Xingjian Kinger Cai Data Center Group 20F No.369 Sec 7 Zhong Xiao East Road. NanGang District. Taipei Taiwan Client Computing Group Intel Microelectronics Asia Ltd Taipei NanGang District Taiwan

ISBN: (纸本)9781538647202

The modern communication system, data center and electronics devices deign, are facing increasing challenges in power delivery network design, besides the well-known signal integrity design challenges. In order to make sure the designed product works well to meet design specification, normally platform design guideline will be provided from System on Chip (SoC) suppliers to OEMs or ODMs before OEMs/ODMs product design phase. After the SoC have been well designed for power integrity by SoC suppliers in terms of power delivery network, conventionally a customer reference board (CRB) with a fixed PDBOM and an assumed stack-up which meets the targeted performance at the known worst case scenario will be provided to the OEMs or ODMs as reference design. Nowadays, one SoC will be widely used in many different products. For example, Intel Ultra product line is used for Microsoft Surface-pro product on any layer, u-via of 10-layer HDI motherboard with performance oriented. It is also used for China Technology Eco-system (CTE) low-end laptop on 6-layer, through hole via motherboard with cost optimized design. The customer reference board with a fixed PDBOM and an assumed stack-up in Platform design Guideline (PDG) could not cover all OEMs/ODMs product design specification requirement, like the performance oriented product or the cost optimized product. And it results in many out of guideline (OOG) designs in the industry with the same SoC. In order to meet design specification of OOG products, the OEMs/ODMs have to invest significant PI resource to re-do the PI design to make sure their products' success. Unified and Efficient Power Integrity Impedance Target Flow (UEPI Flow) provides the flexibility to OEMs/ODMs in designing their products with freedom of doing trade-off among performance, cost and schedule. With provided SoC package MCP (Model Connection Protocol) PI model and coengineered within a commercial EDA tool, OEMs/ODMs can verify their product PI design by this f

关键词： Integrated circuit modeling Tools Impedance Product design Rails Circuit simulation Computational modeling

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Strober: Fast and Accurate Sample-Based Energy simulation for Arbitrary RTL 16

Strober: Fast and Accurate Sample-Based Energy Simulation fo...

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43rd ACM/IEEE Annual International Symposium on Computer Architecture (ISCA)

作者： Kim, Donggyu Izraelevitz, Adam Celio, Christopher Kim, Hokeun Zimmer, Brian Lee, Yunsup Bachrach, Jonathan Asanovic, Krste Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781467389471

This paper presents a sample-based energy simulation methodology that enables fast and accurate estimations of performance and average power for arbitrary RTL designs. Our approach uses an FPGA to simultaneously simulate the performance of an RTL design and to collect samples containing exact RTL state snapshots. Each snapshot is then replayed in gate-level simulation, resulting in a workload-specific average power estimate with confidence intervals. For arbitrary RTL and workloads, our methodology guarantees a minimum of four-orders-of-magnitude speedup over commercial CAD gate-level simulation tools and gives average energy estimates guaranteed to be within 5% of the true average energy with 99% confidence. We believe our open-source sample-based energy simulation tool Strober can not only rapidly provide ground truth for more abstract power models, but can enable productive design-space exploration early in the RTL design process.

关键词： design Energy Experimentation FPGA Hardware modeling Performance Power estimation Statistical sampling

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modeling UML object event handling with Petri nets 23

Modeling UML object event handling with Petri nets

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23rd International conference Mixed design of Integrated Circuits and Systems, MIXDES 2016

作者： Szmuc, Wojciech Szmuc, Tomasz Department of Applied Computer Science AGH University of Science and Technology Kraków30-059 Poland

ISBN: (纸本)9788363578084

The paper describes method of formal modeling object event handling as it is implemented in UML. The resulted Petri net allows to check UML model properties not only by simulation but also formally. For possibly closest congruence between UML and Petri net model an event queue is defined. Each state machine assigned to an object has its own event queue which is available as long as the machine is. That allows to model not only a simple message passing but also cases, when state machine cannot handle an event. A higher priority of submachine's event queue was also taken into consideration. The presented solutions are part of bigger conversion algorithm from UML model to Petri nets [7]. However, the paper was intended to describe the issue in such a detailed way it could be used outside the whole algorithm. © 2016 Department of microelectronics and Computer Science, Lodz University of Technology.

关键词： Petri nets

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4th Asia Pacific conference on Optics Manufacture, APCOM 2014

4th Asia Pacific Conference on Optics Manufacture, APCOM 201...

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4th Asia Pacific conference on Optics Manufacture, APCOM 2014

ISBN: (纸本)9783038356387

The proceedings contain 37 papers. The special focus in this conference is on Optics Manufacture. The topics include: Orthogonal Experiment Study of Micro/nano Motion Platform;3D simulation of the Ultra-precision V-groove Machine Tool;key technologies of diamond tool cutting of ferrous metals with ultrasonic vibration;a Novel Tool Wear Measurement Method in Ultra-precision Raster Milling;the Analysis and design of a Large Stroke with High-precision Polarized Laser Interferometer System;development and modeling of a Macro/Micro Composite Positioning System for microelectronics Manufacturing;design and Analysis of a Planar Piezo-actuated Nanopositioner with Millimeter Scale Stroke;the Assessment of Subsurface Damage in Ground Optics by Chemical Etching;design of the Micro-V-Groove Ultra-Precision CNC Electric Transmission Communication System;a Framework of Data Fusion Algorithm for Precision Measurement of Multiscale Surfaces;adaptive diamond turning for micro-structured surfaces;a Study of Fiducial Aided Precision Positioning of Ultra-precision Freeform Surfaces;modeling and Adaptive Control Based on Actor-Critic Algorithm for a Piezo-positioning System;fabrication of Micro V-Grooves in Ultra-Precision Grinding;using Collins Formula with scaling factor to analysis the propagation properties in laser focus system design;modeling and compensation of the thermal error on feed drive system of CNC grinding machine;a Study of Tool Path Generation for Machining of Precision Roller with Wavy Patterned Microstructures by Slow Tool Servo;spherical Approximation of Free-form Surface Closed to a Sphere in Semi-finishing;solution Concentration Affected Wavy Fibers Fabrication Via Auxiliary Electrodes In Near-field Electrospinning;finite element simulation about abrasive belt grinding Silicon carbide.

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SystemC NoC simulation as the alternative to the HDL and high-level modeling

SystemC NoC simulation as the alternative to the HDL and hig...

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Open Innovations Association and Seminar on Information Security and Protection of Information Technology (FRUCT-ISPIT), conference of

作者： Aleksandr Romanov Aleksandr Ivannikov National Research University Higher School of Economics Moscow Russian Federation The Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Zelenograd Russian Federation

ISBN: (纸本)9781509025008

Actual trends of networks-on-chip research and known approaches to their modeling are considered. The characteristics of analytic and high-/low-level simulation are given. The programming language SystemC as an alternative solution to create models of networks-on-chip is proposed, and SystemC models speed increase methodic is observed.

关键词： Solid modeling Analytical models Unified modeling language Object oriented modeling Hardware design languages Routing Topology

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modeling and simulation of a hybrid 3D silicon detector system using SILVACO and Simulink/MATLAB framework

Modeling and simulation of a hybrid 3D silicon detector syst...

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International conference on microelectronics, ICM

作者： Abdelhady Ellakany Ahmed Shaker Mohamed Abouelatta I. M. Hafez Christian Gontrand Faculty of Engineering Ain Shams University Cairo Egypt CNRS Institut des Nanotechnologies de Lyon INL-UMR5270 France

In this paper, a system of a hybrid pixel detector has been developed. The purpose is to create a flexible and reliable model that simulates the entire system, starting from a 3D detector to a data acquisition system and processing analysis. The model flexibility is achieved by minimizing interdependencies among its entities, so they can be added or removed as needed. The implementation of the system is accomplished using SILVACO and Simulink/MATLAB. The 3D detector is simulated using SILVACO to investigate its electrical performance. It is designed such that to have a good charge collection efficiency, position resolution and reduced charge sharing effects. Simulink is used to implement the readout circuit. The front-end readout circuit includes the Charge Sensitive Amplifier (CSA) and Active Shaper. The most suitable approach and parameters for a real system are selected according to the simulation results. Additionally, practical design constraints are also included in the model.

关键词： Detectors Three-dimensional displays Semiconductor process modeling Mathematical model Software packages Silicon Solid modeling

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