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International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： Mykhaylo Melnyk Andriy Kernytskyy Mykhailo Lobur Michal Szermer Piotr Zajac Cezary Maj Wojciech Zabierowski Department of Computer Aided Systems Lviv Polytechnic National University Lviv Ukraine Department of Microelectronics and Computer Science Lodz University of Technology Lodz Poland

This paper presents an approach to facilitate the design of a microbolometer. It is based on three main steps: the construction of a simplified model in Matlab, automatic transfer of the generated model into ANSYS and the verification of the model using ANSYS FEM (Finite Element Method) simulation. The novel idea is the second step, realized using a special application, which reads the parameters from the simplified model and automatically creates a batch file for ANSYS with all appropriate material and geometry data as well as loads and simulation parameters.

关键词： Finite element analysis Mathematical model Computational modeling MATLAB Cameras Geometry

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Fracture risk assessment of laser marked die by means of simulation and test

Fracture risk assessment of laser marked die by means of sim...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Ilko Schmadlak Betty Yeung Derek Morgan Paul Galles Freescale Halbleiter Deutschland GmbH Munich Germany Freescale Semiconductor Inc. Phoenix Arizona USA Freescale Semiconductor Inc. Austin Texas USA

The method of laser marking die for the purpose tracking and identification is well established in the semiconductor industry. This process needs to be well controlled in order to avoid sacrificing the fracture strength of the die. A common way to assess and compare different laser marking processes is to conduct a series of fracture tests and calculate the characteristic strength that can be expected for a certain laser marking process window. This paper presents and discusses a new methodology that allows obtaining stress concentration results by measuring, simulating and testing laser marked die in great detail. It can be used to compare and rate different laser marking processes. The approach therefore has good potentials of saving money and time by reducing the amount of fracture test studies in the future.

关键词： Solid modeling design automation Stress Computational modeling Laser modes Stress measurement Size measurement

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Compact model for vertical silicon nanowire based device simulation and circuit design

Compact model for vertical silicon nanowire based device sim...

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International SoC design conference, ISOCC

作者： M. Sharma S. Maheshwaram Om. Prakash A. Bulusu A. K. Saxena S. K. Manhas Microelectronics & VLSI E&CE Dept. Indian Institute of Technology Roorkee Uttarakhand India

Verilog-A based unified compact model of silicon vertical nanowire FET is developed for circuit simulation, which includes: short channel, velocity saturation, mobility degradation, quantum mechanical effects and device parasitic. We include scalable TCAD calibrated parasitic resistance and capacitance models, which also consider device asymmetry due to vertical nanowire structure. The model shows excellent match with calibrated TCAD at device as well as circuit level for both long and short channel devices. Further, the model results underline the importance of parasitics on nanowire based circuit performance.

关键词： Integrated circuit modeling Semiconductor device modeling Mathematical model Silicon Nanoscale devices Circuit optimization CMOS integrated circuits

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PGMOR: An Efficient Model Order Reduction Method for Power Grids

PGMOR: An Efficient Model Order Reduction Method for Power G...

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IEEE International conference on Computer-Aided design and Computer Graphics

作者： Qicheng Huang Xiao Li Chenlei Fang Fan Yang Yangfeng Su Xuan Zeng Microelectronics Dept Fudan University Shanghai P. R. China SChool of Mathematical Sciences Fudan University Shanghai P. R. China

simulation of power girds has become increasingly computationally expensive. In this paper, we propose a Model Order Reduction (MOR) method for power grid circuits by extending the existing Aggregation-based MOR (AMOR) method. In the proposed method, besides resistors and capacitors, current sources are also aggregated to improve MOR efficiency. Moreover, pre-partition and parallelization techniques are employed to decrease the reduction time. Numerical results demonstrate that the reduced-order models can achieve up to 18× simulation speed-up over the original circuits without much loss of accuracy.

关键词： Power grids Integrated circuit modeling Partitioning algorithms Resistors Capacitors Ports (Computers) Computational modeling

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System-level modeling and analysis of third order MEMS accelerometer

System-level modeling and analysis of third order MEMS accel...

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International conference on ASIC

作者： Xiangliang Jin Feng Zhang School of Physics and Optoelectronics Xiangtan University Xiangtan China Hunan Engineering Laboratory for Microelectronics Optoelectronics and System on a chip Xiangtan

MEMS technology has been applied to the fields of deep oil exploration, seismic detection. Many of researches for improving the performance of MEMS acceleration sensor had been put forward. In this paper, an effective way for design of feed-forward sigma-delta for MEMS acceleration sensor is proposed. Furthermore, the simulation model is designed successfully under idea environment in MATLAB, which can not indicate it can reach the same performance in real environment after taped out. Therefore, the useful model parameters which had been verified by taped out can be the most valuable parameters for MEMS readout design. In this paper, the work shows an optimized parameters design with signal to noise ration (SNR) of 130dB and its experimental result can reach 125dB.

关键词： Micromechanical devices Accelerometers Sigma-delta modulation Acceleration Modulation Integrated circuit modeling simulation

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A novel three-jet microreactor for localized metal-organic chemical vapour deposition of gallium arsenide: design and simulation

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Journal of Physics: conference Series 2016年第1期741卷

作者： S A Konakov V V Krzhizhanovskaya Department of Physics Chemistry and Microsystems Technology Peter the Great St. Petersburg Polytechnic University 195251 St. Petersburg Russia University of Amsterdam 1098 XH Amsterdam The Netherlands ITMO University St. Petersburg Russia

We present a novel three-jet microreactor design for localized deposition of gallium arsenide (GaAs) by low-pressure Metal-Organic Chemical Vapour Deposition (MOCVD) for semiconductor devices, microelectronics and solar cells. Our approach is advantageous compared to the standard lithography and etching technology, since it preserves the nanostructure of the deposited material, it is less time-consuming and less expensive. We designed two versions of reactor geometry with a 10-micron central microchannel for precursor supply and with two side jets of a dilutant to control the deposition area. To aid future experiments, we performed computational modeling of a simplified-geometry (twodimensional axisymmetric) microreactor, based on Navier-Stokes equations for a laminar flow of chemically reacting gas mixture of Ga(CH3)3-AsH3-H2. simulation results show that we can achieve a high-rate deposition (over 0.3 μm/min) on a small area (less than 30 μm diameter). This technology can be used in material production for microelectronics, optoelectronics, photovoltaics, solar cells, etc.

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CCT post-layout simulation process in mobile phone product design

CCT post-layout simulation process in mobile phone product d...

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International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT)

作者： Denis Chen Thonas Su Jimmy Hsu YL Li Vick Chuang C1ient Computing Group Data Center Group Intel Microelectronics Asia Ltd Taipei Taiwan Data Center Group Intel Microelectronics Asia Ltd Taiwan Branch B1 No.205 Tun-Hwa North Rd. Taipei Taiwan

In Server industry, simulation process is usually separated into pre-layout and post-layout phases. The pre-layout simulation focuses on finding the solution space or choosing a better topology. For post-layout simulation, Intel Channel Check Tool (CCT) methodology has become popular and widely used for past two or three years. CCT is the board-level interconnect electrical performance characterization method. It simplifies and automates the electrical layout checking flow without losing confidence level, and provides indicators (SIG, ISI, XTK, P_Eye, P_Ratio) for a board designer to find the potential layout issues. Comparing with server product, CCT post-layout simulation method is even more suitable for modern mobile phone design due to its routings simplicity and small board size. It is also used in feasibility study of PCB cost reduction.

关键词： Layout Servers Mobile handsets Silicon Analytical models Computational modeling Product design

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A geometry-independent lifetime modelling method for aluminum heavy wire bond joints

A geometry-independent lifetime modelling method for aluminu...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Arian Grams Jan Höfer Andreas Middendorf Stefan Schmitz Olaf Wittler Klaus-Dieter Lang Fraunhofer IZM Berlin Germany Microperipheric Technologies Technische Universitat Berlin Berlin Germany

Wire bond degradation is a limiting factor for the lifetime of state of the art power modules. So, there is a need for widely applicable and proven modelling techniques to achieve a reliable design. In this paper, a new crack growth law has been developed and calibrated with experimental data. By defining a failure criterion and optimizing model parameters, good lifetime predictions have been achieved. In addition, further possibilities to use this modelling approach have been proposed, e.g. damage in interconnect layers as sinter silver or solder layers could be considered.

关键词： Wires Semiconductor device modeling MOSFET Plastics Insulated gate bipolar transistors

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Parallel Native-simulation for Multi-processing Embedded Systems

Parallel Native-Simulation for Multi-processing Embedded Sys...

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Euromicro Symposium on Digital System design

作者： Alejandro Nicolas Pablo Sanchez Microelectronics Engineering Group University of Cantabria Santander Spain

The number of cores in embedded systems is continuously growing, supporting increasingly complex concurrent applications. In order to verify that the systems comply specification requirements during the design process, fast simulations and performance analysis tools are required. These simulation frameworks typically use virtualization or host-compiled simulation techniques. On one hand, current host compiler simulators normally offer fast simulations, but they do not exploit host parallelism capacity. On the other hand, some virtual emulation frameworks take advantage of host parallelization, but they do not achieve simulations as fast as native (host-compiled) simulators because of the dynamic binary translation. This paper proposes a parallel host-compiled simulation methodology that aims to make an efficient use of multi-core host platforms. The performance of the proposed technique has been evaluated with the PARSEC benchmark suite [10]. The evaluation also includes comparisons with native execution and other parallel simulation tools. Results demonstrate that the proposed technique reduces simulation time and provide fast estimations of embedded SW code.

关键词： Computational modeling Kernel Instruction sets Performance analysis Synchronization Estimation Analytical models

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Predictive Physical simulation of III/V Quantum-Well MISFETs for Logic Applications

Predictive Physical Simulation of III/V Quantum-Well MISFETs...

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European Solid State Device Research conference

作者： Z. Stanojevi? M. Karner M. Aichhorn F. Mitterbauer V. Eyert C. Kernstock H. Kosina Global TCAD Solutions GmbH. Landhausgasse 4/la 1010 Vienna Austria Institute for Microelectronics TU Wien GuBhausstraBe 27-29/E360 1040 Vienna Austria Materials Design s.a.r.l. 18 rue de Saisset 92120 Montrouge France

ISBN: (纸本)9781467371360

We present a simulation modeling chain for nanoscaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility;at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.

关键词： present simulation TCAD

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