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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Multiphysics modelling of the fabrication and operation of a micro-pellistor device

Multiphysics modelling of the fabrication and operation of a...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Ferenc Biró Zoltán Hajnal Andrea Edit Pap István Bársony University of Pannonia Veszprém Hungary MEMS Laboratory Institute of Technical Physics and Materials Science Research Centre for Natural Sciences Hungarian Academy of Sciences Konkoly Thege Miklós út 29-33 H-1121 Budapest Hungary MEMS Laboratory Hungarian Academy of Sciences Budapest Hungary

Downsizing efforts in gas-sensing applications lead to ever smaller active elements. Integration with data processing circuitry requires the use of CMOS compatible fabrication technology, autonomous operation poses limits on energy consumption of the elements, whereas reliable catalytic detection often needs high temperatures that may otherwise be constrained by safety considerations. Under these conditions, development of active sensor elements proves to be a growing challenge for design and *** this work we present a step-by-step study on a ≈500 *** diameter thermally isolated membrane element of a gas detecting microsensor device. Sensitivity is based on high temperature (≈3-400 0C) catalytic activity of a porous pellistor deposited on a multilayer SiO 2 /SiN x - filament heated - membrane that has to be durable enough for several thousand hours of operation, and as thin as possible to reduce heat conduction to the substrate. SiO 2 membranes tend to show high residual stress that can be significantly reduced by "sandwiching" with SiN x . We have used COMSOL Multiphysics ® 4.3a [I] to assist the initial product design, and evaluation of operational constrains of the multi-layer thin film. The first part involved systematic thermo-mechanical iterations, while the latter consisted of a combination of gradual static thermo-electro-mechanical simulation steps. As shown by simulating the steps of the deposition process in this work, the right combination of different techniques produces a stable 4-layer membrane with only a sub-micron deformation, and tolerable residual stresses after membrane forming (substrate removal) and during operation. Also, the pellistor filament heating power should be minimized and still reach the operating temperature of the catalyst hotspot. This design, supported by our model calculation was used to realize the device with targeted characteristics. The structure endures the distortion and thermal expansion and contraction du

关键词： Heating Abstracts Product design Biological system modeling Thickness measurement

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Physical model for GaN HEMT design optimization in high frequency switching applications

Physical model for GaN HEMT design optimization in high freq...

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European conference on Solid-State Device Research (ESSDERC)

作者： D. Cucak M. Vasic O. Garcia Y. Bouvier J. Oliver P. Alou J. A. Cobos A. Wang S. Martin-Horcajo F. Romero F. Calle Center for Industrial Electronics (CEI) Universidad Politecnica de Madrid (UPM) Madrid Spain Institute for Optoelectronics Systems and Microelectronics (ISOM) Universidad Politecnica de Madrid (UPM) Madrid Spain

In this paper, physical modeling of a GaN HEMT is proposed, with the objective of device design optimization for application in a high frequency DC/DC converter. From the point of view of a switching application, physical model for input, output and reverse capacitance as well as for channel resistance is very important, since the aforementioned parameters determine power losses in the circuit. The obtained physical model of the switching device can be used for simulation models such as PSpice or hybrid behavioral power loss models for high frequency DC/DC converters. In this work, extrinsic model for I d (V ds , V gs ) output characteristics of a depletion mode GaN HEMT with a field plate structure was obtained, as well as physical model for input, output and reverse capacitance in the subthreshold regime. The model was implemented in Simplorer simulation model and verified by the measured efficiency curves of the buck converter prototype, using the GaN HEMT that was analyzed. With the increase of the switching frequency, precision of the model increases, especially in the low power area, which is the area of interest in our application.

关键词： HEMTs Gallium nitride Capacitance MODFETs Logic gates Aluminum gallium nitride Integrated circuit modeling

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Molecular dynamic simulations of maximum pull-out forces of embedded CNTs for sensor applications and validating nano scale experiments

Molecular dynamic simulations of maximum pull-out forces of ...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Steffen Hartmann Ole Hölck Thomas Blaudeck Sascha Hermann Stefan E. Schulz Thomas Gessner Bernhard Wunderle Technische Universität Chemnitz Chemnitz Germany

We present investigations of pull-out tests on CNTs embedded in palladium by means of molecular dynamics (MD) and compare our results of maximum pull-out forces with values of nano scale in situ pull-out tests inside a scanning electron microscope (SEM). Our MD model allows the investigation of crucial influencing parameters on the interface behaviour, like CNT diameter, intrinsic CNT defects and functional groups. For the experiments we prepared simple specimens using silicon substrates and wafer level compliant technologies. We realised the nano scale experiment with a nanomanipulation system supporting an AFM cantilever with known stiffness as a force sensing element inside a SEM. Greyscale correlation has been used to evaluate the cantilever deflection. From simulations derived maximum pull-out forces are approximately 17 nN and depend on the existence of intrinsic defects or functional groups and weakly on temperature. Experimentally obtained maximum pull-out forces with values between 16-29 nN are in good agreement with the computational predictions. Our results are of significant interest for the design and a failure-mechanistic treatment of future mechanical sensors with integrated single-walled CNTs showing high piezoresistive gauge factor or other nano scale systems incorporating CNT-metal interfaces.

关键词： Abstracts Loading Load modeling

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modeling of SiC power modules with double sided cooling

Modeling of SiC power modules with double sided cooling

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Klas Brinkfeldt Klaus Neumaier Alexander Mann Olaf Zschieschang Alexander Otto Eberhard Kaulfersch Michael Edwards Dag Andersson Swerea IVF Mölndal Sweden Fairchild Semiconductor GmbH Aschheim Germany Fraunhofer ENAS Chemnitz Germany Berliner Nanotest und Design GmbH Berlin Germany

Silicon Carbide (SiC) based transistor devices have demonstrated higher efficiency switching operation compared to silicon-based, state-of-the-art solutions due to the superior electrical and thermal properties of the SiC material. The improved current density and thermal conductivity allows SiC-based power modules to be smaller than their silicon counterparts for comparable current densities. The active chip area can be reduced further by effectively cooling the devices. In this work, a new power module including SiC bipolar junction transistors (BJT) and diodes and integrated double sided cooling will be introduced. The target application of these modules is a new drive-train system for commercial electric vehicles. The double sided cooling concept (named 2Cool) is a feasibility study with the goal to further compact the inverter system. More efficient removal of heat from the junction leads to a higher power rating per die, which in turn leads to fewer die and reduced system volume. Since temperature is a main driver in expected failure modes an increase in cooling capability will also enhance margins of the SiC device reliability. In addition, the removal of wirebonds on the top side of the die will result in lower electrical inductance. Several geometries of the heat exchanger cooling structures have been modeled in terms of thermal performance. The best geometry was a staggered pin-fin structure, which resulted in a junction temperature increase of 74 K at 400 W thermal loading. Also, thermomechanical modeling was used to make an estimation of stress in the power module materials.

关键词： Heating Abstracts Three-dimensional displays Switches Cooling Pumps Power dissipation

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A new structure of current mode min-max circuit using CMOS technology for fuzzy applications

A new structure of current mode min-max circuit using CMOS t...

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Iranian conference on Electrical Engineering (ICEE)

作者： Ramin Khayatzadeh Ghasem Yazdani Abdollah Khoie Khayrollah Hadidi Microelectronics Research Laboratory Urmia University Urmia Iran

In this paper a new structure of current mode minmax circuit is presented. The proposed structure can detect minimum and maximum of the input current signals simultaneously. It has advantages of analog design such as 1.5 percent error in maximum amplitude and low power consumption. Hence, the proposed circuit has high precision. The proffered circuit involves 14+4 transistors using 0.18um CMOS standard technology. A 1.8 (V) power supply is applied and the Monte Carlo, corner, pulse and other simulations for checking performances of the proposed circuit have been done using HSPICE level49 (BSIM3v3) software. Also, the layout pattern of the proposed circuit is drawn by CADENCE software.

关键词： Fuzzy logic CMOS integrated circuits Transistors simulation Integrated circuit modeling CMOS technology Mirrors

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Channel noise scan by using simulations of voltage regulator noise to signals

Channel noise scan by using simulations of voltage regulator...

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International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT)

作者： Jimmy Hsu Patt Chang Thonas Su Gong Ouyang Kai Xiao Falconee Lee Y L Li DCG Intel Microelectronics Asia Ltd. Taipei Taiwan DCG Intel Corporation DuPont WA USA

In this paper, channel noise scan approach (CNS) is proposed to efficiently analyze the potential VR-signal coupling issue in the pre-silicon design and the post-silicon debug of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction between the two. The goal of this simulation methodology is to help platform developer to quantify the VR-signal coupling risk and find the outliers of the victim signal nets according to the board layout and the VR design. This methodology can also provide the ability for the designer to do performance/cost tradeoff, layout optimization. To systematically analyze the VR-signal coupling problems, both the frequency and time domain approaches have been developed to characterize the VR-signal coupling in different levels. The frequency domain approach can quickly point out potential issues and the time domain approach is proved to be consistent with the frequency domain but with more detail and intuitive information. A design flow is given to efficiently identify the outliers of victim signals by VR noise coupling impact. designers can improve the layout based on channel noise scan results from the simulations.

关键词： Couplings Noise Layout Integrated circuit modeling Switches Frequency-domain analysis Voltage control

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A modified CMOS nano-power resistorless current reference circuit

A modified CMOS nano-power resistorless current reference ci...

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Shailesh Singh Chouhan Kari Halonen SMARAD-II Department of Micro and Nano Sciences Aalto University School Of Electrical Engineering Finland

In this work, all MOS current reference circuit is proposed using a standard 0.18 μm technology and the simulations were performed using the Cadence Spectre simulator. The proposed current reference circuit is based on, the resistorless current reference circuit suggested by Oguey and Aebishcher. The Oguey's circuit is capable of generating the reference current in a nanoampere range, but with the high temperature coefficient (TC). The reason for high TC, that we found, is the lack of control over the gate-source voltage of an active resistor used in the design. This gate-source voltage is one of the controlling parameters responsible to obtain adequate thermal compensation for the reference current. In the proposed work, we modified the architecture to limit the variation of the gate-source voltage with the temperature and hence controls the thermal behaviour of the reference current. The working supply voltage of the proposed circuit ranges from 1.25 V to 2 V. The temperature coefficients of the reference current generated from the proposed and conventional architectures are 39.8 ppm/°C and 545.12 ppm/°C respectively at a supply voltage of 1.25V for the temperature ranging from -60°C to 85°C. The maximum power consumption of proposed and conventional architecture is 624.8nW and 468.59nW at a supply voltage of 2 V with the layout area of 0.0013μm 2 and 0.001μm 2 respectively.

关键词： Threshold voltage Logic gates Temperature distribution Resistors CMOS integrated circuits Integrated circuit modeling simulation

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Laser attacks on integrated circuits: From CMOS to FD-SOI

Laser attacks on integrated circuits: From CMOS to FD-SOI

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International conference on design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Jean-Max Dutertre Stephan De Castro Alexandre Sarafianos Noémie Boher Bruno Rouzeyre Mathieu Lisart Joel Damiens Philippe Candelier Marie-Lise Flottes Giorgio Di Natale ENSM.SE Centre Microlectronique de Provence-Georges Charpak France ST Microelectronics Avenue Clestin Coq France STMicroelectronics LIRMM (CNRS UMR N5506) France

The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model permitted us to draw the laser sensitivity map of a SRAM cell. It demonstrates a very close correlation with experimental measures. We also introduce the preliminary results we gathered to build a similar electrical model for FD-SOI circuits. FD-SOI technology is expected to be less sensitive to laser than CMOS.

关键词： Semiconductor lasers Laser modes Transistors Integrated circuit modeling Photoconductivity Junctions Measurement by laser beam

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Drop impact simulations for lifetime assessment of PCB/BGA assemblies regarding pad cratering

Drop impact simulations for lifetime assessment of PCB/BGA a...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Grace L. Tsebo Simo Hossein Shirangi Matthias Nowottnick Rainer Dudek Eberhard Kaulfersch Sven Rzepka Bernd Michel Robert Bosch GmbH Engineering Assembly and Interconnect Technology (AE/EAI2) Stuttgart Germany University of Rostock: IEF/IGS Institute of Electronic Appliances and Circuits Rostock Germany Fraunhofer ENAS Micro Materials Center Chemnitz Germany

In automotive electronics, complex automotive functionalities are managed by car's computers such as electronic control units (ECU). Albeit extremely rare, accidental drop impacts may occur during transportation or mounting ECUs on automobiles, damaging the built-in printed circuit board (PCB)/ball grid array (BGA) package assembly. However, due to larger package dimensions together with heavy components such as capacitors mounted on the board surface, higher acceleration and stress levels can be achieved on ECU electronic components than on hand-held electronic devices during a drop impact. In such cases, the board level drop test methodology defined in the Joint Electron Device Engineering Council (JEDEC) standard needs to be modified in order to match the requirements in automotive applications. The experimental setup used in this study includes a test board clamped between two aluminum frames with the help of screws, in order to reproduce the real clamping conditions of the PCB in an ECU. Furthermore, the new board design allows mounting additional masses at the center of the PCB to take into account the effect of the mass of electronic components present in real ECUs. In this work, the mechanical behavior of PCB/BGA assemblies used in automotive applications when subjected to drop events is assessed. Numerical simulations of the board behavior are performed in order to analyze the transient structural response of the PCB and evaluate the local stresses on the board/joint interface responsible for pad cratering. By varying the loading conditions, different stress levels can be achieved on the PCB laminate directly under the solder joints and a stress-life curve for predicting the assembly lifetime is hence established.

关键词： Predictive models Abstracts Accelerometers Load modeling Glass Soldering Solids

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Bluetooth Transceiver modeling Using SystemC-AMS

Bluetooth Transceiver Modeling Using SystemC-AMS

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9th conference on Ph D Research in microelectronics and Electronics (PRIME)

作者： Li, Fangyan Butaud, Remi Dekneuvel, Eric Jacquemod, Gilles Univ Nice Biomed Implants Project Team EPIB Sophia Antipolis France Riviera Waves Sophia Antipolis France

ISBN: (纸本)9781467345811;9781467345804

This paper presents the high-level modeling and simulation of a GFSK RF transceiver for a Bluetooth Low Energy (BLE) system. This model, written in SystemC-AMS (SC-AMS) permits a simple integration within the existing system digital environment written in SystemC-TLM, which enables a global system simulation to obtain the system performance (e. g. Bit-Error-Rate (BER) or Packet- Error-Rate (PER)) related to the power and energy consumption.

关键词： BT SystemC-AMS RF system design

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