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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Finite element based design of a new dogbone specimen for low cycle fatigue testing of highly filled epoxy-based adhesives for automotive applications

Finite element based design of a new dogbone specimen for lo...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： B. Öztürk P. Gromala C. Silber K.M.B. Jansen L.J. Ernst Delft University of Technology CD Delft The Netherlands Robert Bosch GmbH Automotive Electronics Reutlingen Germany Industrial Design Engineering Delft University of Technology CE Delft The Netherlands Emeritus Professor of Delft University of Technology Schoonhoven The Netherlands

Highly filled epoxy-based adhesives are used as thermal and electrical interfaces in automotive electronics. The successful design for reliability of electronic packages depends on understanding and modeling the fatigue behavior of these materials. Both mechanical and thermal loadings are varying in a cyclic manner in test or field conditions. To establish an adequate constitutive model describing the thermo-mechanical behavior under cyclic mechanical and thermal loading, material testing is required on a dedicated test specimen. Current specimen geometries which are used to describe fatigue behavior of highly filled epoxy-based materials fail to describe the mechanical behavior. They contain stress concentrations near the clamping area, which leads to the failure within these areas and not in the reduced section of the beam. In this paper, a new test sample with dogbone geometry is designed by utilizing finite element analysis (FEA). A design space (DoE) is used to analyze the effect of important parameters (e.g. thickness, length and radius) that influence the stress distribution. The optimum design point is selected by FEA of stresses in the reduced section of the beam and near the clamping. In order to validate the simulations, experiments are done with samples, which are produced with the help of PTFE coated steel molds. This approach is shown to improve the existing dogbone designs and validity of the low cycle fatigue testing.

关键词： Abstracts Load modeling Analytical models Testing Geometry Computer aided software engineering Knowledge based systems

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A Block Cipher Circuit design against Power Analysis

A Block Cipher Circuit Design against Power Analysis

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International conference on Computational Intelligence and Security

作者： Yuxiao Ling Zheng Guo Zhimin Zhang Zhigang Mao Zeleng Zhuang School of Micro-Electronics Shanghai Jiao Tong University Shanghai Fudan Microelectronics Group Co. Ltd Shanghai China

In this paper, we will present a block cipher circuit design against Power Analysis. This design consists of usual masking and hiding method. For XOR, permutation and other linear layer, masking method of protection is used, but for S-box and other non-linear layer, hiding method is used in the reason that masking requires a lot of hardware consumption. We accomplished hardware implementation and Power Analysis in our research, whose test results proved that the design had strong capacity against Power Analysis. 200, 000 curves were extracted in our attack simulation, and the key successfully resisted complete recovery.

关键词： Integrated circuit modeling Ciphers Hardware Registers Algorithm design and analysis

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Determination of interface fracture parameters: Energy Release Rate and Mode Mixity using FEA

Determination of interface fracture parameters: Energy Relea...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： I. Maus H. Pape H. S. Nabi B. Michel B. Wunderle Infineon Technologies AG Regensburg Germany Infineon Technologies AG Neubiberg Germany ENAS Chemnitz TU Chemnitz Germany TU Chemnitz

Interfacial delamination IS one of the most important reliability issues in the microelectronic industry. On this account more and more focus is set on related research. The application of advanced Finite Element Analysis (FEA) provides a way to understand, predict and in conclusion to prevent reliability issues. Critical interface fracture data, which include the Critical (Strain) Energy Release Rate G c (Ψ) as a function of temperature, humidity or aging, are crucially needed in microelectronic industry for failure modeling, lifetime prediction and design evaluation associated with reliability [1], but they are rarely given in literature. Therefore fast measurement methods are needed [2, 3, 4]. The evaluation of the critical data with respect to interfacial fracture mechanics needs not only measurements, but also simulations to be carried out in parallel. The numerical methods used in this work are the Crack Surface Displacement Extrapolation Method (CSDEM) [3, 5] and the Virtual Crack Closure Technique (VCCT) [3, 4, 6]. The interface we focus on is between Cu-Lead frame and epoxy-based glue-Die Attach. This work is focused on the measurement method of the critical fracture mechanic properties with the micro Mixed Mode Tester (μMMT) [2] on samples cut from real products and their numerical evaluation including parameter effect studies.

关键词： Abstracts microelectronics Aging Predictive models Welding Force

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Stress impact of moisture diffusion measured with the stress chip

Stress impact of moisture diffusion measured with the stress...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： F. Schindler-Saefkow F. Rost A. Otto R. Pantou R. Mroßko B. Wunderle B. Michel S. Rzepka J. Keller AMIC Angewandte Micro-Messtechnik GmbH Berlin Germany Micro Materials Center Fraunhofer ENAS Chemnitz Germany Fraunhofer ENAS Micro Materials Center Chemnitz Germany Technische Universität Chemnitz Germany

The experimental observation of the actual thermo mechanical weak points in microelectronics packages remains a big challenge. Recently, a stress sensing system has been developed by the publicly funded project that allows measuring the magnitudes and the distribution of the stresses induced in the silicon dies by thermomechanical loads. Moisture can saturate a package very fast at high temperatures and high humidity within hours but also at low temperatures and low humidity within weeks or months. Every normal stored or used package will be swelled due to this moisture. A high temperature over a short time or within the first cycle of a temperature cycling test will dry the package and the internal stress of the package decrease. This moisture swelling will be investigated in this paper. All measurements are supplemented by finite element simulations based on calibrated models for in depth analysis and for extrapolating the stress results to sites of the package that are not measured directly. The methodology of closely combining stress measurements and FE simulation presented in this paper has been able to validate the stress sensing system for tasks of comprehensive design and process characterization as well as for health monitoring. It allows achieving both, a substantial reduction in time tomarket and a high level of reliability under service conditions, as needed for future electronics and smart systems packages.

关键词： Abstracts Moisture measurement Sensors Computational modeling Heating Materials Lead

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Novel reliability assessment concept based on an accelerated de-rated strength approach

Novel reliability assessment concept based on an accelerated...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： E.P. Veninga R. Kregting A. van der Waal A.W.J. Gielen TNO Technical Sciences-Materials for Integrated Products Eindhoven Netherlands

The introduction of new materials or technologies can have an enormous impact on the Time to Market (TTM) of new products. Preferably, the performance of new materials or technologies is known before these are designed into a product. This paper presents a reliability assessment approach which has been developed with the aim to reduce the so called Time to Technology (TTT). The method which is based on an accelerated de-rated strength approach has been expanded to a concept which could also include health monitoring and prognostics during lifetime. In this part of the work a combination of modelling and statistical techniques was used to explore the feasibility and potential of the concept. Ball Grid Array (BGA) designs were used as a vehicle with solder fatigue as the selected failure mechanism. Finite Element Modelling (FEM) together with design of Experiments (DoE) revealed that the (package) substrate thickness, stand-off, (package) substrate size and the final solder ball diameter are the statistical significant factors with respect to fatigue life of SnAgCu BGA balls. Simplified linear models obtained from regression analyses were used to design de-rated strength variants and estimate test times. simulations using a strain based lifetime model of Engelmaier together with a Monte Carlo method were used to generate lifetime distributions based on induced variations. A statistical analysis showed a significant difference in lifetime performance between the simulated de-rated strength designs.

关键词： Reliability Load modeling Abstracts Monitoring

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Study on reliability of ultrathin device embedded in organic substrate under drop impact loading using stresses monitor and simulation

Study on reliability of ultrathin device embedded in organic...

引用

Electronics Packaging Technology conference (EPTC)

作者： Zhaohui Chen Xiaowu Zhang A*STAR (Agency for Science Technology and Research) Institute of Microelectronics

Reliability of the embedded ultrathin device in the organic substrate packaging is one of major concerns during its applications. In this paper, drop impact tests were conducted to the embedded ultrathin stress sensor chip in the organic substrate. Stresses were monitored with the embedded stress sensor chip based on silicon piezoresistive effects. Dynamic explicit finite element model with the input-G method was built up to investigate the stress and strain behaviors of the embedded chip and solder bump. The drop impact simulation model was validated by the experimental stresses monitoring results. It indicated that the discrepancy of the normal stress σ 11 at the center of embedded stress sensor chip from experimental and numerical simulation results is within 10%. Based on the validated model, the effects of material properties and structural parameters on the stress and strain responses were studied by the numerical simulation. The maximum normal stress σ 11 at the embedded sensor chip and the peeling stress σ 33 of the solder bump were selected as the indexes for the comparisons and optimizations. The experimental and numerical simulation efforts can provide design guidelines for the embedded ultrathin chip in the organic substrate packaging.

关键词： Stress Substrates Reliability Numerical models Load modeling Material properties Finite element analysis

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Multi-core SoC architecture exploration with radar digital system based on dataflow graph method

Multi-core SoC architecture exploration with radar digital s...

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IEEE International conference on Electronics, Circuits and Systems (ICECS)

作者： Zhiyuan Lu Yuanyi Shen Hu He Institute of Microelectronics Tsinghua University Beijing China

This article outlines a fully complete process in the term of exploration and evaluation about the multi-core SoC architecture with target radar algorithms computing on it. As powerful radar system is in need and SoC technology is widely used in radar field, architecture considers not only speed of processing units but also large data throughput of multi-channels. This work focuses on the architecture exploration of radar signal processing system by using dataflow graph method. After creating dataflow graphs and accurate architecture models in SystemC-based simulation platform at system level, dataflow graph mapping strategy can be implemented into the models. Static computation and dynamic simulation with precise simulation results are used to analyze the mapping strategy and architecture. The one which can best fulfill the demand of target application at a lower cost is the purpose. A specific optional SoC architecture and several algorithms are used as an example to illustrate this complete process.

关键词： Computer architecture Computational modeling Radar System-on-chip Hardware Algorithm design and analysis Digital signal processing

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Study of equivalent thermal modeling and simulation of 2.5D/3D stacked dies module

Study of equivalent thermal modeling and simulation of 2.5D/...

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International conference on (ICEPT) Electronic Packaging Technology

作者： Fengwei Dai Daquan Yu Jing Zhou He Ma Xiaomeng Wu Xiangmeng Jing Chongshen Song Hongwen He Institutes of Microelectronics Chinese Academy of Sciences Beijing China National Center for Advanced Packaging Wuxi China

In the paper, an equivalent modeling method is proposed to simplify thermal simulation model of 2.5D stacked dies modules. A TSV and its surrounding silicon substrate or a micro bump and its surrounding underfill will be equivalent to a single body of material. Through this method, we will not only be able to obtain thermal characteristics of each part of the stacked dies module, but also can greatly simplify the calculation amount of numerical simulation. According to this method, we obtained thermal distribution map of 2.5D/3D stacked dies module; in addition, to guide and optimize thermal management design, we analyzed the influence of several parameters on maximum junction temperature of 2.5D stacked dies as well, such as spacing among dies, thermal conductivity of TIM2 (Thermal Interface Material), ambient temperature, wind speed and so on. It was found that with the increase in spacing among dies, the maximum junction temperature of dies decreases and the maximum decreasing amplitude is 4.4°C. Secondly, impact on the maximum junction temperature of die, the ambient temperature of the cabinet is the most serious. Finally, the wind speed of the cabinet and the thermal conductivity of TIM2 (Thermal Interface Material) also have a great effect on the maximum junction temperature of die.

关键词： Thermal conductivity Conductivity Silicon Junctions Through-silicon vias Heating

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Signal integrity study of high density through silicon via (TSV) technology

Signal integrity study of high density through silicon via (...

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Electronics Packaging Technology conference (EPTC)

作者： Bok Eng Cheah Jackson Kong Chee Kit Chew Kooi Chi Ooi Shanggar Periaman Intel Microelectronics (M) Sdn Bhd Halaman Kampung Jawa Penang Malaysia

This paper explores the electrical performance of several multi-channel TSV designs i.e. cross-etched full-plated TSV and cross-etched partial-plated TSV to further improve data transmission bandwidth among the vertically stacked silicon devices. The electrical characteristics of the multi-channel TSV designs were investigated and compared against the conventional TSV design in terms of return loss, insertion loss, near-end (NEXT) and far-end (FEXT) crosstalk. Fullwave electromagnetic simulation data showed the insertion loss performance of the multi-channel TSV designs are at par with the conventional TSV design up-to 50GHz. Meanwhile, the multi-channel TSV designs were found yielding improved NEXT and FEXT crosstalk performance. Transient analyses of respective TSV designs are also included in this paper for more conclusive discussions.

关键词： Through-silicon vias Insertion loss Capacitance Three-dimensional displays Silicon Solid modeling

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A MEMS resonator tank for an RF VCO application

A MEMS resonator tank for an RF VCO application

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IEEE International conference on Electronics, Circuits and Systems (ICECS)

作者： Daniel Zammit Owen Casha Ivan Grech Edward Gatt Joseph Micallef Department of Microelectronics and Nanoelectronics University of Malta Msida Malta

This paper presents the design and study of a MEMS tapped-inductor LC resonator tank, proposed to evaluate the improved performance over that generally achieved in standard CMOS passive component integration. The resonator tank, consisting of a fixed-value inductor and a variable capacitor, was implemented in the MetalMUMPs process and was targeted for a VCO intended for telemetry applications. A geometrically optimized 1.25 nH horseshoe inductor was designed and results show that it exhibits a Q-factor of 63 at 7.3 GHz and a self-resonating frequency of 17.6 GHz. In addition, an improved π-inductor model is proposed for design and simulation purposes. The variable capacitor was designed in a parallel-plate topology, using four serpentine springs. The capacitance can be varied from 0.183 pF to 0.245 pF with an actuation voltage in the range of 0 V-to-11.7 V. A Q-factor of 62 at 1.1 GHz and a self-resonating frequency above 10 GHz were achieved. The designed inductor and capacitor were configured in a resonator tank topology yielding an overall Q-factor of 22 at 4.9 GHz.

关键词： Inductors Q-factor Micromechanical devices Capacitors Substrates Integrated circuit modeling Voltage-controlled oscillators

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