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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是661-670 订阅

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Baseband modeling of a GNSS Receiver Front-end using SystemC/-AMS

Baseband Modeling of a GNSS Receiver Front-end using SystemC...

引用

PRIME 2012;8th conference on Ph.D. Research in microelectronics & Electronics

作者： Zhimiao Chen Yifan Wang Stefan Heinen Chair of Integrated Analog Circuits and RF Systems RWTH Aachen

ISBN: (纸本)9783800734429

The functionality verification of a mixed-signal sys- tem on chip requires the model for RF front-end with high simulation efficiency. The pure passband model cannot meet this requirement when a long system time simulation is run. The equivalent baseband model is an alternative. In this work, a new baseband modeling method based on a self-defined signal type is realized on the platform of SystemC/-AMS. This method can more accurately describe the block nonlinearity than the traditional equivalent baseband model. For the application in the design of a global navigation satellite system (GNSS) receiver front-end, the baseband simulation based on this method has much faster simulation speed than passband simulation. Index Terms — baseband modeling, GNSS, SystemC/-AMS, RF front-end

关键词： Baseband Passband Noise Radio frequency Integrated circuit modeling Global Navigation Satellite Systems Harmonic analysis

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modeling CMOS PIN photodiode using COMSOL

Modeling CMOS PIN photodiode using COMSOL

引用

International conference on microelectronics, ICM

作者： Mohamad Hamady Ehsan Kamrani Mohamad Sawan Polystim Neurotechnologies Laboratory Electrical Engineering Department Polytechnique de Montréal QUE Canada

modeling semiconductor devices has become mandatory in most challenging research activity. Finding a powerful tool that models these devices represents a goal of these users. In this work, Silicon PIN photodiode is designed using complementary metal-oxide semiconductor (CMOS) Technology. COMSOL Multiphysics is the selected challenging tool for simulation and characterization of this design. The adjustment of the proposed model as well as the different outputs like Electric field and Electric potential distribution, I-V characteristics and other parameters are presented. The output current has shown an allure of a current that consists of three regions: TrapAssisted Tunneling, Band-to-Band Tunneling and avalanche. These current regions in addition to the high value (10 5 V/cm) of the obtained electric field are typical for Silicon Avalanche Photodiodes (SiAPD). The possibility to use this tool for SiAPD analysis and simulation is therefore discussed.

关键词： Semiconductor process modeling Mathematical model Electric fields Semiconductor device modeling Silicon CMOS integrated circuits Junctions

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Systematic generation of performance models of reconfigurable analog circuits

Systematic generation of performance models of reconfigurabl...

引用

International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD)

作者： Manuel Velasco-Jiménez Rafael Castro-López Elisenda Roca Francisco Fernández Seville Microelectronics Institute IMSE-CNM CSIC University of Seville Spain

In this work, a systematic technique to generate performance models of reconfigurable analog circuits is presented. The performance models are obtained in the form of multi-mode Pareto-optimal fronts (mm-PoFs), a new type of Pareto-optimal front (PoF) that characterizes the set of different performances that reconfigurable circuits can attain. The technique is based on the use of an evolutionary algorithm (EA) that acts as an optimizer, and the simulator HSPICE to measure the circuit performances. The use of this technique will be illustrated for a wireless multistandard problem, where a reconfigurable op-amp will be considered.

关键词： Power demand Analog circuits Standards Solid modeling design methodology Evolutionary computation GSM

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Improved modeling of Intersymbol Interference in High Speed Serial Links

Improved Modeling of Intersymbol Interference in High Speed ...

引用

PRIME 2012;8th conference on Ph.D. Research in microelectronics & Electronics

作者： Andrea Cristofoli Pierpaolo Palestri Luca Selmi Nicola Da Dalt DIEGM - University of Udine Via delle Scienze Infineon Technologies AG Development Center Villach

We present a statistical approach that improves the modeling of Intersymbol Interference for the design and validation of High-Speed Serial Links. The method combines the computational advantages of a statistical technique and the accuracy in modeling the realistic pulse shape of a Spice simulation. Results obtained with the proposed approach are compared with Spice simulations of a 2.5 Gb/s CMOS differential transmitter driving different types of channel. Good agreement with the reference Spice simulations is achieved with a drastic reduction of computation time.

关键词： Transmitters Integrated circuit modeling Solid modeling Computational modeling Shape Analytical models Bit error rate

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simulation of ion implantation for CMOS 1µm using SILVACO tools

Simulation of ion implantation for CMOS 1µm using SILVACO t...

引用

International conference on microelectronics, ICM

作者： Mohamed Boubaaya Fayçal Hadj Hadj Larbi Slimane Oussalah Microelectronics and Nanotechnology Division Centre for Development of Advanced Technologies Algiers Algeria

One micron gate-length LDD-CMOS (Lightly Doped Drain - Complementary Metal Oxide Semiconductor) technology uses N and P-MOSFETs, realized on the same substrate, in a way to benefit simultaneously from a combination of their characteristics. Some regions of these transistors like the Wells and the Source/Drain are created by a reliable technique called ion implantation. The aim of this paper is to simulate the ion implantation steps included in the LDD-CMOS 1 micron process which has been acquired by CDTA ( Centre for Development of Advanced Technologies) from ISiT (Fraunhofer-Institut für Siliziumtechnologie). The process simulation framework ATHENA of the TCAD (Technology Computer Aided design) SILVACO's software was employed to simulate our process and extract some process technology parameters, such as P+ and N+ doping concentrations as well as the ion implantation energies and doses, and the corresponding junction depths.

关键词： Ion implantation Semiconductor process modeling Transistors Integrated circuit modeling Semiconductor device modeling Implants Doping profiles

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LDS based tools to ease template construction

LDS based tools to ease template construction

引用

International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD)

作者： A. Unutulmaz G. Dündar F.V. Fernández School of Electrical and Electronics Engineering Bogazici University Turkey Institute of Microelectronics of Sevilla CSIC and University of Sevilla Spain

Layout Description Script (LDS) is a domain specific language (DSL) intended to describe analog layouts. This paper introduces an LDS based tool, Capture, and an add-on, LDS Analyzer, for LDS. Capture aims to convert layout images into layout templates. Components of a layout are extracted with this tool and a template is synthesized from the extracted data. LDS Analyzer is an enhanced LDS parser. Analyzer investigates an LDS statement and conducts either simple parsing or enhanced parsing which make use of symbolic variables.

关键词： Layout Circuit synthesis Routing Educational institutions Data mining Optimization design automation

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Behavioral model of split capacitor array DAC for use in SAR ADC design

Behavioral model of split capacitor array DAC for use in SAR...

引用

PRIME 2012;8th conference on Ph.D. Research in microelectronics & Electronics

作者： Dmitry Osipov Yuriy Bocharov National Research Nuclear University "MEPhI" Russia

A model of a switched capacitor digital-to-analog converter (DAC) based on a split capacitor array is presented for use during the design of a successive approximation register (SAR) analog-to-digital converter (ADC). The model takes the effects of parasitic capacitors into account, and the values of these parasitic capacitors can be extracted from the circuit topology by using Calibre by Mentor Graphics or a similar tool. The influence of the two main parasitic capacitor types (those parallel to and those common to the capacitors in the arrays) on the DAC characteristics is analyzed. We provide expressions for fast manual calculation of the integral non-linearity (INL) and differential non-linearity (DNL) errors according to the values of the parasitic capacitors. simulation results from a Verilog-A module based on this model are given. The model provides higher simulation speeds with accuracy close to that of a transistor-level model by using the extracted parasitic parameters.

关键词： Capacitors Arrays Integrated circuit modeling Mathematical model Hardware design languages Equations simulation

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Surrogate models of Pareto-optimal planar inductors

Surrogate models of Pareto-optimal planar inductors

引用

International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD)

作者： M. Kotti R. González-Echevarría E. Roca R. Castro-López F.V. Fernández M. Fakhfakh J. Sieiro J.M. López-Villegas University of Sfax Sfax Tunisia Seville Microelectronics Institute (IMSE-CNM) CSIC University of Seville Seville Spain Grup de Radiofreqüència Facultat de Física Universitat de Barcelona Barcelona Spain

Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is obtained by embedding an electromagnetic simulator into a multi-objective optimization tool. Then, starting from the obtained optimal samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35μm CMOS technology are provided.

关键词： Inductors Q factor Inductance Integrated circuit modeling Optimization Computational modeling Radio frequency

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design and simulation methodology for switch-cap circuits used in data converter applications

Design and simulation methodology for switch-cap circuits us...

引用

International conference on microelectronics, ICM

作者： Sanad Kawar Mahmood Mohammed Khaldoon Abugharbieh Electrical Engineering Department Princess Sumaya University for Technology Amman Jordan

This paper provides a full methodological approach to designing and verifying differential sample and hold switched-capacitor circuits used in A/D converters. It provides a step-by-step process for translating system requirements such as signal-to-noise ratio (SNR) and sampling frequency into A/D requirements and subsequently into op-amp specifications. It also includes the design process of a switched-capacitor common mode feedback circuit (CMFB) to control the common mode output voltage. Furthermore, this paper provides practical methods for verifying the stability of the system. A design and simulation example for a differential sample and hold switched-capacitor circuit operating in a system requiring 5 MHz sampling frequency and a 6-bit A/D converter is provided. Mentor Graphics CAD tools were used in the design and simulations process using 180 nm CMOS device models. This paper can be used as a resource for design engineers in the industry as well as universities teaching graduate level advanced electronics and data converter courses.

关键词： Circuit stability Integrated circuit modeling Stability analysis Capacitors Switching circuits Topology Voltage control

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An automated layout-aware design flow

An automated layout-aware design flow

引用

International conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit design (SMACD)

作者： A. Toro-Frías R. Castro-López E. Roca F. V. Fernández Seville Microelectronics Institute IMSE-CNM CSIC University of Seville Spain

In analog integrated circuit design, it has always been necessary to improve the designer's productivity. The iterations between the electrical and physical synthesis, required to correct deviations due to parasitics, do degrade that productivity. The inclusion of the physical implementation directly within the electrical synthesis process, would in principle remove many or all of these iterations. This paper presents a fully-automated layout-aware design flow, whose key aspects are: (1) it uses commercially available tools and platforms to attain a highly integrated solution, (2) it provides solutions in the form of Pareto-optimal fronts, which represent the circuit's valuable trade-offs (and can be used in modern design flows), and (3) it allows including the impact of parasitics right into the fronts. This paper details the necessary tools and their integration for automation of the design flow and provides several examples of its use.

关键词： Layout Algorithm design and analysis Optical fibers Optimization Transistors Productivity Analog circuits

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