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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Accelerating RTL simulation with GPUs 11

Accelerating RTL simulation with GPUs

引用

IEEE International conference on Computer-Aided design

作者： Hao Qian Yangdong Deng Institute of Microelectronics Tsinghua University Beijing China

ISBN: (纸本)9781457713989

With the fast increasing complexity of integrated circuits, verification has become the bottleneck of today's IC design flow. In fact, over 70% of the IC design turn-around time can be spent on the verification process in a typical IC design project. Among various verification tasks, Register Transfer Level (RTL) simulation is the most widely used method to validate the correctness of digital IC designs. When simulating a large IC design with complicated internal behaviors (e.g., CPU cores running embedded software), RTL simulation can be extremely time consuming. Since RTL-to-layout is still the most prevalent IC design methodology, it is essential to speedup the RTL simulation process. Recently, General Purpose computing on Graphics Processing Units (GPGPU) is becoming a promising paradigm to accelerate computing-intensive workloads. A few recent works have demonstrated the effectiveness of using GPU to expedite gate and system level simulation tasks. In this work, we proposed an efficient GPU-accelerated RTL simulation framework. We introduce a methodology to translate Verilog RTL description into equivalent GPU source code so as to simulate circuit behavior on GPUs. In addition, a CMB based parallel simulation protocol is also adopted to provide a sufficient level of parallelism. Because RTL simulation lacks data-level parallelism, we also present a novel solution to use GPU as an efficient task-level parallel processor. Experimental results prove that our GPU based simulator outperforms a commercial sequential RTL simulator by over 20 fold.

关键词： Graphics processing unit Integrated circuit modeling Hardware design languages Kernel Parallel processing Load modeling

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Polymer cored BGA ball reliability optimisation

Polymer cored BGA ball reliability optimisation

引用

European microelectronics and Packaging conference, EMPC

作者： D.C. Whalley H. Kristiansen L. Halbo Conpart AS Skjetten Norway Wolfson School of Mechanical and Manufacturing Engineering Loughborough University Loughborough UK

This paper presents the results from simulation studies of the mechanical performance of BGA interconnects based on the use of polymer cored solder balls (PCSBs) as an alternative to the solid solder balls that are typically used. PCSBs have previously been shown to offer improved reliability and this study was performed to improve understanding of the effects of two key PCSB design variables, i.e. metallisation thickness and polymer modulus on their fatigue performance. The results show that minimising the polymer modulus is beneficial in reducing plastic strains in both the solder and copper metallisation on the polymer ball, but that the metallisation thickness has a much less significant effect unless the polymer core modulus is extremely low.

关键词： Reliability Polymers Computational modeling Assembly Facsimile Optimization Thermal conductivity

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An improved multiphysics modelling approach for dielectrophoresis-based cell separation

An improved multiphysics modelling approach for dielectropho...

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Canadian conference on Electrical and Computer Engineering (CCECE)

作者： Antoine Gagné Mohamed Amine Miled Mohamad Sawan Department of Electrical Engineering École Polytechnique de Montreal Québec Canada

ISBN: (纸本)9781424497881;9781424497898

This article presents a new multiphysics modelling approach for cell manipulation by dielectrophoresis. This approach is proposed to model and predict the behavior of particles injected into a microchannel due to the application of an electrical field. The objective of this model is to better characterize microelectronic circuits dedicated to design and implement hybrid systems such as lab-on-chips integrating microelectronics and microfluidic structures. The proposed model allows to determine the required configuration of microelectronic circuits and needed control signals to generate. This model applies primarily to applications using dielectrophoresis cell separation in a micro- channel. Then, by using the proposed model, the cell behaviour can be predicted using an advanced multiphysics simulation method.

关键词： Integrated circuit modeling Mathematical model microelectronics Biological system modeling Dielectrophoresis Microchannel Electric potential

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A genetic neural network modeling of GaN HEMTs for RF power amplifiers design

A genetic neural network modeling of GaN HEMTs for RF power ...

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International conference on microelectronics, ICM

作者： Anwar Jarndal Swaroop Pillai Hussein Abdulqader Fadhel M. Ghannouchi Electrical and Computer Engineering Department University of Nizwa Nizwa Oman IRadio Laboratory ECE Department University of Calgary Calgary AB Canada

A genetic neural network based large-signal model for GaN HEMT transistor suitable for designing power amplifiers (PAs) is presented along with its parameters extraction procedure. This model is relatively easy to construct and implement in CAD software and requires only DC and S-parameter measurements. The modeling procedure was applied to a 4-W packaged GaN-on-Si HEMT and the developed model is validated by comparing its large-signal simulation to measured data. The model has been employed for simulating a switching-mode inverse class-F power amplifier. Very good agreement between the amplifier simulation and measurement shows the validity of the model.

关键词： Solid modeling MODFETs HEMTs Gallium nitride Integrated circuit modeling Computational modeling Logic gates

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Junction vertical slit field-effect transistor (JVeSFET) - compact DC model

Junction vertical slit field-effect transistor (JVeSFET) - c...

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International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： Andrzej Pfitzner Michał Staniewski Michał Strzyga Institute of Microelectronics and Optoelectronics Warsaw University of Technology Warsaw Poland

The VeSTIC technology proposed by Maly seems to be very attractive for manufacturing of mixed analogue/digital circuits of highly regular layout in nanoscale. First results of a feasibility study of a new JFET structure designed in the VeSTIC 3D geometry JVeSFETs are very promising and indicate good electrical properties. A preliminary compact model for circuit simulation has been presented in this paper.

关键词： Numerical models Logic gates Mathematical model Junctions Threshold voltage Semiconductor process modeling Doping

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Verilog-A model of a high-k HfO2-Ta2O5 capacitor

Verilog-A model of a high-k HfO2-Ta2O5 capacitor

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International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： George Angelov Nikolay Bonev Rostislav Rusev Marin Hristov Albena Paskaleva Dentcho Spassov Department of Microelectronics ECAD Laboratory FETT Technical University of Sofia Sofia Bulgaria Institute of Solid State Physics Bulgarian Academy of Sciences Sofia Bulgaria

A circuit simulation model of a MOS capacitor using high-k HfO 2 -Ta 2 O 5 mixed layer structure is developed using Verilog-A hardware description language. Model equations are based on the BSIM3v3 model core. Capacitance-voltage (C-V) and current-voltage (I-V) characteristics are simulated in Spectre circuit simulator within Cadence CAD system and validated against measurements of stack structure.

关键词： Mathematical model Solid modeling Hafnium compounds Capacitance Logic gates Integrated circuit modeling Substrates

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Vertical-Slit Field-Effect Transistor (VeSFET) - design space exploration and DC model

Vertical-Slit Field-Effect Transistor (VeSFET) - design spac...

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International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： Andrzej Pfitzner Institute of Microelectronics and Optoelectronics Warsaw University of Technology Warsaw Poland

This paper presents an in-depth discussion of the Vertical-Slit Field-Effect Transistor's (VeSFET's) operation. The junction-less twin gate VeSFET is the basic component of a new 3D VeSTIC technology proposed by Maly. Our numerical TCAD simulations confirm the attractive properties of VeSFETs, such as high I on to I off ratio, low leakage currents, and effective current control by independently biased symmetric gates. These simulations serve as a backbone for an analytical approximation of the VeSFET characteristics, and the first, rudimentary compact DC model for circuit simulation has been developed.

关键词： Logic gates Threshold voltage Substrates Mathematical model Silicon Integrated circuit modeling Numerical models

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A multi-domain electrostatic actuator design tool based on analytical models

A multi-domain electrostatic actuator design tool based on a...

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International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： Cezary Maj Andrzej Napieralski Michal Olszacki Mohammad Al-Bahri Patrick Pons Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland Laboratoire dAnalyses et dArchitecture des Systemes INSA INP ISAE LAASUPS Université de Toulouse Toulouse France

One of the most promising and evolving technology is MEMS. Its market has grown rapidly in recent years. It is the merit of simulation techniques evolution, which allows estimation of a device performance before its fabrication and consequently reducing the time to market and the production costs. One of the most popular technique is FEM analysis due to its wide range of application and ability of performing multi-domain simulation. However, it has some disadvantages concerning simulation time. Often, simulations of some simple devices are time consuming. One of them is an electrostatic actuator that needs nonlinear analysis. Moreover, a bended membrane form induces additional complex calculations. It seems that fast and reliable analytical modeling will be a good alternative. In this paper, a dedicated tool for micromachined membrane-based electrostatic actuator is presented.

关键词： Analytical models Electrostatics Finite element methods Mathematical model Electrostatic actuators Electrodes

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Development and characterization of 300mm large panel eWLB (embedded wafer level BGA)

Development and characterization of 300mm large panel eWLB (...

引用

European microelectronics and Packaging conference, EMPC

作者： Seung Wook Yoon Yaojian Lin Pandi C. Marimuthu STATS ChipPAC Ltd. Singapore STATS ChipPAC Limited Singapore

This paper will highlight some of the recent advancements in 300mm eWLB large panel development. Compared to 200mm case, 300mm large panel has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100~150% more warpage with 300mm large panel compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper also presents study of process optimization for 300mm eWLB and on overall warpage behavior in different process steps. Finally 300mm eWLB test vehicles are fabricated and tested in JEDEC standard test conditions. It also describes mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps.

关键词： Materials Electromagnetic compatibility US Department of Energy Semiconductor device modeling

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Thermal modeling and characterization of Package with Through-Silicon-Vias (TSV) Interposer

Thermal modeling and characterization of Package with Throug...

引用

Electronics Packaging Technology conference (EPTC)

作者： X. Q. Xing Y. J. Lee T. Y. Tee X. Zhang S. Gao W. S. Kwon Institute of Microelectronics Agency for Science Technology and Research Singapore NEPES Private Limited Singapore

Numerical simulation of micro-bumped flip chips mounted on a TSV interposer is conducted to study the thermal performance of the package. The 3D package, which consists of two chips, each dissipating 4W, is evaluated under various conditions with its thermal resistances θ ja θ jb , θ jc and θ jma determined according to JEDEC or MIL-STD standard. Instead of building the detailed model, equivalent thermal conductivity model is adopted for anisotropic bump-underfill layers, silicon interposer and the substrates. Effects of design parameters to the waste heat dissipation, such as the density of TSV in the interposer and the presence of mold encapsulation are investigated. In addition, maximum power dissipation of the package is explored. These modeling results are useful for design optimisation, and also to provide thermal design guideline for a reliable, high performance, and cost-effective 3D package.

关键词： Electronic packaging thermal management Silicon Thermal conductivity Conductivity Heating Through-silicon vias Solid modeling

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