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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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XFVHDL4: A hardware synthesis tool for fuzzy systems

XFVHDL4: A hardware synthesis tool for fuzzy systems

引用

International conference on Intelligent Systems design and Applications (ISDA)

作者： M. Brox S. Sánchez-Solano L. Delgado Department of Computer Architecture University of Cordoba Cordoba Spain Microelectronics Institute of Seville CNM-CSIC Seville Spain School of Computer Engineering of Seville University of Seville Seville Spain

This paper presents a design technique that allows the automatic synthesis of fuzzy inference systems and accelerates the exploration of the design space of these systems. It is based on generic VHDL code generation which can be implemented on a programmable device (FPGA) or an application specific integrated circuit (ASIC). The set of CAD tools supporting this technique includes a specific environment for designing fuzzy systems, in combination with commercial VHDL simulation and synthesis tools. As demonstrated by the analyzed design examples, the described development strategy speeds up the stages of description, synthesis, and functional verification of fuzzy inference systems.

关键词： Random access memory Fuzzy systems Libraries Field programmable gate arrays Integrated circuit modeling Hardware Pipelines

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System modeling and Analysis of the IEEE 802.15.4 Physical Layer design

System Modeling and Analysis of the IEEE 802.15.4 Physical L...

引用

2011 IEEE 9th International conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

作者： Jikang Xia Lan Chen Ying Li Yinhao Zhou Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China

Physical layer structure usually is first considered to design a standard SoC in wireless sensor networks, while few practical works can be referenced. This paper presents detailed functional system' modeling which obeys IEEE 802.15.4 protocol and performance analysis of three physical layer bands. Emphatically, the system includes a novel algorithm of de-spreading with minimum hamming distance and an implementation of half-sine pulse shaping filters. According to the simulation results, error control coding like BCH is recommended to use to enhance the data accuracy, and the low complexity filters can effectively improve the system performance. The contribution of this paper is providing valuable reference for the further design on wireless sensor network baseband chips.

关键词： Signal to noise ratio Analytical models Bit error rate Payloads

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Study of threshold voltage modeling for small-scaled strained Si nMOSFET

Study of threshold voltage modeling for small-scaled straine...

引用

International conference on Electric Information and Control Engineering

作者： Qu, Jiang-Tao Zhang, He-Ming Qin, Shan-Shan Xu, Xiao-Bo Hu, Hui-Yong Key Lab of Wide Band-Gap Semiconductor Materials and Devices School of Microelectronics Xidian University Xi'an 710071 China

ISBN: (纸本)9781424480395

In this paper, based on the distribution of electric field in the channel which follows the Guass Law, an analytical expression of Quasi-2D threshold voltage model for strained Si nMOSFET with Polycrystalline SiGe gate was established. With this model, the variation threshold voltage with its design physical and geometric parameters can be predicted, such as Ge content, oxide thickness, doping concentration, gate length, and drain bias. The validity of the model was proved by ISE TCAD simulation. This model is significant for the design of high performance strained Si nMOSFET © 2011 IEEE.

关键词： Threshold voltage

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modeling and simulations of 1 KV/5 A normally-off 4H-SiC VJFET

Modeling and simulations of 1 KV/5 A normally-off 4H-SiC VJF...

引用

IEEE International conference on Multi Topic

作者： M. Khalid S. Riaz S. Naseem Microelectronics Division Centre of Excellence in Solid State Physics University of Punjab Lahore Pakistan

Silicon carbide (SiC) has proved to be a promising material for the development of high temperature and high power applications because of excellent thermal and physical properties. In this study, 2D numerical simulation is performed using industry based Sentaurus TCAD tools. The aim of this research work is to design a device which provides high performance for power applications. Complete design provides the excellent forward and blocking characteristics. simulation results show that increasing temperature, improve the forward characteristics and 5 A saturation current at 600 K is observed at V GS = 3 V. Also, a very low on-resistance is observed at 600 K which is 0.027 mΩ. The design also provides good blocking capability at room temperature which indicates high value of figure of merits (FOM). The calculated values of FOM decrease with increasing temperature and 19.75 MW (300 K) to 0.5 MW (600 K) are observed at V GS = -2 V. In addition, its high current value and superior FOM makes 4H-SiC VJFET an excellent device that can give better performance for high temperature and high power applications.

关键词： Logic gates Numerical models

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An Efficient 90nm Technology-Node GHz Transceiver of On-Chip Global Interconnect

An Efficient 90nm Technology-Node GHz Transceiver of On-Chip...

引用

2011 IEEE 9th International conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

作者： Zaixiao Zheng Zhigang Mao Jianfei Jiang Department of Microelectronics Shanghai JiaoTong University Shanghai 200240. China

Today high speed signal transmission system for on chip global interconnect requires elaborate design of the transceiver. The design goal of transceiver is to ensure the transmission obtains 'an improvement in latency and power, which are the two most important factors in high speed transmission. In this paper, we present an efficient structured transceiver which implements low swing technology based on the differential structure with the accurate modeling of the on chip global interconnect. And we give the principals of the structure and compare the optimized simulation results with the traditional inverter insertion method used to decrease the delay of the global interconnect. Our transceiver design is based on the 90nm CMOS technology and TSMC 90nm interconnect structure on Metal 5. The global interconnect length we focus on is the general length 10mm. Compared to repeater insertion, this system has a latency advantage of 17％ and remarkable advantage in power up to 33.9％.

关键词： 90nm technology Differential transmission Low swing 3-D multi-level modeling

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Signal Integrity simulation for SiP Using GTLE

Signal Integrity Simulation for SiP Using GTLE

引用

2011 12th International conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

作者： Jia Jia liqiang Cao lixi Wan Institute of Microelectronics Chinese Academy of Science Beijing 100029 China

Signal integrity (SI) simulation for system-in-package (SiP) is a bottleneck in SiP design flow. This paper presents a novel numerical algrothm for SI simulation in packaging structure. This algorithm is based on 2D Generalized Transmission Line Equation (GTLE), Finite Difference Time Domain (FDTD) and mesh division technique. SI is simulated using mesh division technique where the model of SI is obtained by regarding each cell as a 2D transmission line. 2D GTLE is a group partial equation about voltage and current density distribution on a power/ground plane pair. After reduction, the voltage equation for 2D GTLE is obtained, which is a wave equation. One method to solve the wave equation is by the finite-difference scheme. In this paper, the fringe effect and absorbing boundary condition is applied to implement the wave equation efficiently and easily. Three test cases are presented to explain the solution of the wave equation. The methodology described in prior section has been implemented in a CAD tools. The results from our method were compared to those from the full-wave simulator to show efficiently in signal integrity simulation.

关键词： Mathematical model Solid modeling Equations Time domain analysis Finite difference methods Numerical models Integrated circuit modeling

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A methodology for modeling embedded processors for architecture exploration

A methodology for modeling embedded processors for architect...

引用

International conference on microelectronics, ICM

作者： Ahmed Elhossini Shawki Areibi Robert Dony School of Engineering University of Guelph Guelph Canada

Architecture exploration for embedded systems is becoming an indispensable tool for System-on-Chip designers. This process requires the evaluation of many architectures that are generated during the exploration process. The evaluation process has a significant impact on the quality of the results and could consume a substantial amount of CPU time. Accordingly, the evaluation process should provide enough accuracy to guide the optimization process to promising points in the design space in reasonable time. In this paper an efficient approach for performance evaluation of embedded systems is proposed. Several cycle-accurate simulations are performed for commercial embedded processors used in our study. The simulation results are used to build Artificial Neural Network (ANN) models with accuracy up to 90% compared to cycle-accurate simulations with a very significant time saving.

关键词： Program processors Artificial neural networks Accuracy Power demand Training Computer architecture Benchmark testing

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designing a New Biological Function in Synthetic Biology

Designing a New Biological Function in Synthetic Biology

引用

2011 2ND International conference on Innovative Computing and Communication and 2011 Asia-Pacific conference on Information Technology and Ocean Engineering(CICC-ITOE 2011)

作者： Qun Wei Chemical Engineering Institute Northeast dianli University

Synthetic biology is a science resulting from the connection between biotechnology and engineering sciences. It aims to design and build new biological systems and *** this paper, models of biologic gates using different abstraction levels have been presented. For each kind of model, its advantages and drawbacks were discussed. The high-level model will be used during the first step of the design to validate the concept. It allows fast simulation, even for big systems, and can be completed by mathematical tools in order to automatism the process. An intermediate model, using templates(like in microelectronics), gives some indications about concentration and timing which allows to validate a system in a worst- case situation without complex simulations. Finally, the low- level model, which uses biological ODEs, can be used to predict accurately the timedependent evolution of protein concentration in the cell. Two types of low-level model are presented: the signal flow model, which consists in explicit ODEs and the conservative model which is based on implicate ODEs coming from matter conservation principle. For the latter, we developed a formalism that permits to represent a biological mechanism by an electronic circuit using voltage and current sources, resistances and capacities.

关键词： Index Terms—Biological Function Synthetic Biology modeling

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designing a New Biological Function in Synthetic Biology

Designing a New Biological Function in Synthetic Biology

引用

The 2011 International conference on Computer, Communication, Control and Automation (3CA 2011)

作者： Qun Wei Chemical Engineering Institute Northeast dianli University

Synthetic biology is a science resulting from the connection between biotechnology and engineering sciences. It aims to design and build new biological systems and functions. In this paper, models of biologic gates using different abstraction levels have been presented. For each kind of model, its advantages and drawbacks were discussed. The high-level model will be used during the first step of the design to validate the concept. It allows fast simulation, even for big systems, and can be completed by mathematical tools in order to automatism the process. An intermediate model, using templates(like in microelectronics), gives some indications about concentration and timing which allows to validate a system in a worst- case situation without complex simulations. Finally, the low- level model, which uses biological ODEs, can be used to predict accurately the time-dependent evolution of protein concentration in the cell. Two types of low-level model are presented: the signal flow model, which consists in explicit ODEs and the conservative model which is based on implicate ODEs coming from matter conservation principle. For the latter, we developed a formalism that permits to represent a biological mechanism by an electronic circuit using voltage and current sources, resistances and capacities.

关键词： Biological Function,Synthetic Biology,modeling

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Development of Low-cost Wafer Level Package through Integrated design and simulation Analysis

Development of Low-cost Wafer Level Package through Integrat...

引用

2011 12th International conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

作者： Tong Yan Tee In Soo Kang Haoyang Chen Glen Siew Serine Soh Jong Heon Kim Shan Gao Germaine Hoe Teck Kheng Lee Bok Leng Ser Hun Shen Ng Nepes Pte Ltd.12 Ang Mo Kio Street 65 Singapore 569060. Institute of Microelectronics.11 Science Park Road Singapore Science Park II Singapore 117685. Institute of Technical Education.201 Circuit Road Singapore 379498. SMARTS Technology LLP.Blk 425 Canberra Road #11-477 Singapore 750425.

Wafer level package (WLP) provides the smallest form factor to satisfy multifunctional device requirements along with improved signal integrity for today's latest handheld electronics. WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Three sizes of LCWLP are designed and simulated, prior to assembly and reliability tests. The structural design features electrical, mechanical and thermal simulations of LCWLP with three chip sizes and ball layout. simulation results show LCWLPs investigated are able to satisfy the functional and reliability requirements. Electrical simulation demonstrates that LCWLP with the same I/O counts but smaller package size, has better functional performance than FCBGA. Mechanical simulation indicates that wafer level warpage of all LCWLPs studied are within acceptable range for wafer level processes. For board level reliability, LCWLPs are expected to pass the thermal cycling test. Furthermore, LCWLPs are small in sizes with very low junction-to-case thermal resistance, able to keep the maximum junction temperature low and cool the chips during operations. Its thermal performance is strongly influenced by the chip size but independent of the Cu RDL density.

关键词： Resistance Copper Electronic packaging thermal management Junctions Semiconductor device modeling Semiconductor device reliability

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