检索结果-内蒙古大学图书馆

Heat Dissipation design for a High Density-High Power Chip Package

Heat Dissipation Design for a High Density-High Power Chip P...

2011 12th International conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

作者： Jing Zhou Liqiang Cao Xueping Guo Qidong Wang Daniel Guidotti Xiangmeng Jing Daquan Yu Lixi Wan Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China

In this paper several heat dissipation mechanisms are studied in an effort to improve heat dissipation of a high-power packaged chip in its environment. Specifically we examine a cavity-down structure consisting of a copper plate in thermal contact with the back side of the chip. In order to evaluate the thermal performance of the cavity-down approach, three structures are compared via simulation. Heat transport occurs by conduction, radiation and convection. The first depends on material properties, thickness and temperature gradient. The second is only effective if the temperature of the radiator is much higher than that of the absorber and the two are in close proximity. Convection is most effective at high mass flow and large differential temperatures. For the problem at hand we consider, several different thicknesses of the copper heat spreader to optimize conduction within the bounds of the package. In addition, forced air convection is optimized, within the package limitations. Optimum cooling conditions are obtained by parameterization of variables: air flow direction, fan position, and package placement.

关键词： Heating Electronic packaging thermal management Copper Atmospheric modeling Temperature Cooling Substrates

来源：评论

学校读者我要写书评

暂无评论

Analytical modeling and simulation Studies of High Voltage Super-junction Drift layer for Power MOSFET

Analytical Modeling and Simulation Studies of High Voltage S...

引用

22nd International conference on microelectronics (ICM 2010)

作者： Kondekar, Pravin N. Indian Inst Informat Technol Design & Mfg Jabalpur MP India

ISBN: (纸本)9781612841519

In the conventional VDMOS high voltage super-junction (SJ) power transistor, to achieve high breakdown voltage (BV), you have to use lower doping and higher thickness of the drift layer which prohibitively increases it on resistance making it unsuitable for use. Super-junction power MOSFET (CooIMOS (TM)) claim to resolve this limitation and high voltage device up 1000V are using super junction drift layer with relatively low on resistance. In this paper an effort is made to explain in detail with the help of analytical treatment and simulation results to understand the physical mechanisms involved in improving the on resistance with high BV. An analytical modeling method is also proposed to get the design guide line for device dimensions and optimum doping levels for minimum on resistance based on Super-junction Theory.

关键词： Super-junction MOSFET VDMOS Charge imbalance Breakdown voltage Power MOSFET Charge compensation

来源：评论

学校读者我要写书评

暂无评论

Virtual prototyping advanced by statistic and stochastic methodologies

Virtual prototyping advanced by statistic and stochastic met...

引用

2010 11th International conference on Thermal, Mechanical and Multi-Physics simulation, and Experiments in microelectronics and Microsystems, EuroSimE 2010

作者： Rzepka, Sven Müller, Axel Michel, Bernd Fraunhofer ENAS Micro Material Center Chemnitz Germany Fraunhofer ENAS Micro Material Center Berlin Germany BorgWarner BERU Systems GmbH Dept. Modeling and Analysis Ludwigsburg Germany

ISBN: (纸本)9781424470266

The paper reports three examples of best industrial practice showing the substantial benefits gained in terms of time-to-market reduction when virtual prototyping is enhanced by statistical and stochastic methodologies. These examples from a microelectronics setting of high volume component and module manufacturing deal with different fields: i) ball grid array (BGA) design optimization based on sophisticated design-of-experiments (DoE) and response surface (RS) schemes, ii) material modeling based on stochastic parameter identification and optimization, and iii) process pre-qualification by involving a stochastic robustness analysis. ©2010 IEEE.

关键词： Virtual prototyping

来源：评论

学校读者我要写书评

暂无评论

Moisture diffusion modeling and application in a 3D RF module subject to moisture absorption and desorption loads

Moisture diffusion modeling and application in a 3D RF modul...

引用

2010 11th International conference on Thermal, Mechanical and Multi-Physics simulation, and Experiments in microelectronics and Microsystems, EuroSimE 2010

作者： Zhu, Liping Monthei, Dean Lambird, Gene Holgado, Wally TriQuint Semiconductor Inc. OR United States

ISBN: (纸本)9781424470266

Moisture induced interfacial delamination failures are often found in a microelectronic package within die attach epoxy and laminate substrate during moisture sensitivity reliability test. In this paper, a piecewise normalization approach is proposed to simulate moisture sensitivity test with both preconditioning absorption and reflow desorption phases. A bi-material model with analytical solutions is used to validate the modeling approach. It is shown that the moisture concentration using proposed modeling approach can be correlated well with analytical solutions in both preconditioning absorption and reflow desorption phases. The modeling approach then has been applied to a 3D RF module, a typical system in package, to effectively obtain distribution of moisture concentration which is one of key parameters in calculation of moisture induced hygroscopic stress and vapor pressure induced stress and thus the moisture induced risk can be quickly assessed in early product development for optimal design to achieve a goal of design for reliability. ©2010 IEEE.

关键词： Moisture

来源：评论

学校读者我要写书评

暂无评论

Accurate EC-ANN modeling for A RF-MEMS extended tuning range varactor

Accurate EC-ANN modeling for A RF-MEMS extended tuning range...

引用

2nd Asia Pacific conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2010

作者： Wang, Jie Sun, Lingling Liang, Yaping Department of Electrical Engineering Zhejiang University Hangzhou Zhejiang 310027 China Microelectronics CAD Center Hangzhou Dianzi University Hangzhou Zhejiang 310018 China

ISBN: (纸本)9781424467372

A novel accurate and efficient modeling method based on Equivalent Circuit trained Artificial Neural Network (EC-ANN) technique is developed for a RF-MEMS extended tuning range varactor. The parameters are extracted directly from the equivalent circuit model and used as training and testing sets for the ANN. Experiments show that the proposed approach can be used to fast and accurately model the RF characteristics of the RF-MEMS varactor. The results can agree with the EC-ANN predictions and the Ansoft HFSS simulations. To extend the capabilities of the proposed methodology, the developed EC-ANN modeling technique is used for design, simulation and optimization of the MEMS circuits.

关键词： Equivalent circuits

来源：评论

学校读者我要写书评

暂无评论

Mixed-level modeling for network on chip infrastructure in SoC design

Mixed-level modeling for network on chip infrastructure in S...

引用

Asia-Pacific conference on Circuits and Systems

作者： Hu, Yang Yin, Shouyi Liu, Leibo Wei, Shaojun Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics Tsinghua University Beijing 100084 China

ISBN: (纸本)9781424474561

We present a concise, fast, accurate, efficient mixed-level full-system based realistic application-oriented simulation platform in this paper which aims to evaluate the cycle-accurate behavior of interconnection component thus help developers to explore more optimized NoC architecture. A trace-driven transaction-level simulation environment is built to get realistic traffic patterns for interconnection. We design wrappers to translate the transaction-level traffic patterns into cycle-accurate flits. We implement routers at cycle-accurate level which use fixed five-step pipeline architectures pursuing more details in design, while implement peripherals (IP cores) at transaction-level following TLM 2.0 standard. Due to we only need to focus on the performance of interested part, that is the interconnection, under the premise of keeping the accuracy of interconnection simulation, the utilization of transaction-level models makes the peripheral modeling in full-system simulation environment more efficient, lightweight, configurable and scalable. © 2010 IEEE.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

simulation of thermal behavior for networks-on-chip

Simulation of thermal behavior for networks-on-chip

引用

28th Norchip conference, NORCHIP 2010

作者： Wegner, Tim Cornelius, Claas Gag, Martin Tockhorn, Andreas Uhrmacher, Adelinde Institute of Applied Microelectronics and Computer Engineering University of Rostock Richard-Wagner-Str. 31 18119 Rostock-Warnemuende Germany

ISBN: (纸本)9781424489732

Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based simulation environment for systems based on NoCs, is introduced. VulcaNoCs is designed to enable simultaneous execution of both high-level system simulation and dynamic modeling of temperature distributions in NoC-based systems. To emulate a system's thermal properties equivalent RC-circuits are used, exploiting the dualism between heat flow and electrical phenomena. To verify the temperature model, VulcaNoCs is compared to a more commonly used SPICE-based approach, exhibiting significant increases in simulation performance of up to 98,5% for modeling a 2x2 NoC, for example. ©2010 IEEE.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

Multiphysics modeling and design of ultralarge multiwafer MOVPE reactor for group III-nitride light emitting diodes

Multiphysics modeling and design of ultralarge multiwafer MO...

引用

2010 11th International conference on Thermal, Mechanical and Multi-Physics simulation, and Experiments in microelectronics and Microsystems, EuroSimE 2010

作者： Kim, Changsung Sean Hong, Jongpa Shim, Jihye Won, Yongsun Kwon, Yong-Il Corporate R and D Institute Samsung Electro-Mechanics Co. Ltd. Suwon 443-743 Korea Republic of LED Lab. Samsung LED Co. Ltd. Suwon 443-743 Korea Republic of

ISBN: (纸本)9781424470266

A multiphysics modeling and design has been performed for the world's largest Metal Organic Vapor Phase Epitaxy (MOVPE) reactor by combining Theory of Inventive Problem Solving (TRlZ) for concept design, design for Six Sigma (DFSS) for shape optimization, and Computer-Aided Engineering (CAE) simulations of multi-scale from atomic to macro scales. Numerical simulations considering gas phase chemical reactions and surface chemistry have been thoroughly verified by comparing with experimental measurements from various MOVPE reactors. As a preliminary study, two transparent mock-up models for the ultra-large MOVPE reactor were made in real scale and their internal flow fields were measured by laser Doppler velocimetry (LDV). A RF induction heater was also simulated by coupling the thermo-fluid field and electro-magnetic field together. Since the MOVPE reactor was manufactured, numerous tests for high-temperature reliability and temperature uniformity have repeatedly been conducted. Consequently, these multidisciplinary approaches have been successfully applied to develop the ultralarge MOVPE reactor for group III-nitride light emitting diode (LED). ©2010IEEE.

关键词： Computer aided engineering

来源：评论

学校读者我要写书评

暂无评论

Advanced analysis on board trace reliability of WLCSP under drop impact

引用

microelectronics RELIABILITY 2010年第7期50卷 928-936页

作者： Syed, Ahmer Tee, Tong Yan Ng, Hun Shen Anderson, Rex Khoo, Choong Peng Rogers, Boyd Amkor Technol Inc Singapore 118222 Singapore

Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSPnl (TM)), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design, three primary failure modes can be observed, i.e. copper (Cu) board trace crack, Cu RDL (redistribution layer) vertical crack and Cu/Under Bump Metallization (UBM) delamination. CSPnl can exhibit distinct failure modes under different test board and/or CSPnl designs, resulting in a vast difference in drop test lifetimes. The primary failure mode is shifted whenever the weakest link is removed through design improvement. This paper will focus on detailed analysis of copper board trace crack under drop test, using an integrated approach of testing, failure analysis, material characterization and modeling. Board design guidelines are formulated to understand the effects of I/O position, board trace routing direction, board trace width, tear drop design, PCB pad size, stack-up thickness, and alloy materials on board trace reliability. Comparison is also made on possible impact on Cu RDL reliability. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： WLCSP Drop Test Solder Joint Reliability design modeling Copper Interconnect

来源：评论

学校读者我要写书评

暂无评论

Reliability modeling on a MOSFET power package based on embedded die technology

引用

microelectronics RELIABILITY 2010年第7期50卷 923-927页

作者： Yang, Daoguo Kengen, Martien Peels, W. G. M. Heyes, David van Driel, W. D. Guilin Univ Elect Technol Gulin Peoples R China NXP Semicond NL-6534 AE Nijmegen Netherlands

Embedding of discrete semiconductors into substrates has the advantages of achieving high degree of miniaturization, good electrical performance and possible low cost. A MOSFET power package based on the embedded die technology was developed and the demonstrators were built. To reduce cost and time-to-market, thermo-mechanical virtual prototyping is applied to support the package development. 2D and 3D parametric FE models were established to conduct numerical simulations to investigate the thermo-mechanical reliability performance under packaging processes and test conditions. The package design and material variations, such as the thicknesses of the Cu layer and the resin in the RCC foil, the Bond Line Thickness (BLT), the thickness and material properties of prepreg, via dimensions and via-filling, were included in the parametric models. The root cause for die cracking, delamination between the interface die/RCC foil, and cracking of Cu vias were analyzed based on the simulation results. Verification of the modeling results was conducted through comparison with the test results. The results indicate that the prediction from the FE modeling matches reasonably well with the test results. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： METAL oxide semiconductor field-effect transistors ELECTRONIC packaging RELIABILITY (Engineering) COMPOSITE materials -- Delamination THERMOPHYSICAL properties MATERIALS -- Mechanical properties ENGINEERING -- Mathematical models COMPUTER simulation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：