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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Advanced analysis on board trace reliability of WLCSP under drop impact

Advanced analysis on board trace reliability of WLCSP under ...

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10th International conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in Micro-Electronics and Micro-Systems

作者： Syed, Ahmer Tee, Tong Yan Ng, Hun Shen Anderson, Rex Khoo, Choong Peng Rogers, Boyd Amkor Technol Inc Singapore 118222 Singapore

Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSPnl (TM)), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design, three primary failure modes can be observed, i.e. copper (Cu) board trace crack, Cu RDL (redistribution layer) vertical crack and Cu/Under Bump Metallization (UBM) delamination. CSPnl can exhibit distinct failure modes under different test board and/or CSPnl designs, resulting in a vast difference in drop test lifetimes. The primary failure mode is shifted whenever the weakest link is removed through design improvement. This paper will focus on detailed analysis of copper board trace crack under drop test, using an integrated approach of testing, failure analysis, material characterization and modeling. Board design guidelines are formulated to understand the effects of I/O position, board trace routing direction, board trace width, tear drop design, PCB pad size, stack-up thickness, and alloy materials on board trace reliability. Comparison is also made on possible impact on Cu RDL reliability. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： WLCSP Drop Test Solder Joint Reliability design modeling Copper Interconnect

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Thermomechanical design and modeling of porous alumina-based thin film packages for MEMS

Thermomechanical design and modeling of porous alumina-based...

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2010 11th International conference on Thermal, Mechanical and Multi-Physics simulation, and Experiments in microelectronics and Microsystems, EuroSimE 2010

作者： Zekry, Joseph Vandevelde, Bart Bouwstra, Siebe Puers, Robert Van Hoof, Chris Tilmans, Harrie A. C. Imec Kapeldreef 75 3001 Heverlee Belgium Katholieke Universiteit Leuven Belgium MEMS TC Amsterdam Netherlands

ISBN: (纸本)9781424470266

Thin film 0-level or wafer-level MEMS packages exhibit relatively low flexural strength and yet they are required to reliably protect the enclosed MEMS devices under extreme processing and operational conditions. In this paper, we present a thermomechanical study of porous alumina-based thin film MEMS packages by making use of finite element modeling (FEM) techniques. We developed a 2D axisymmetric FEM that includes a porosity-dependent orthotropic representation of the porous alumina layer. The results of the FEM for a typical thin film package show around 15% enhancement over an analytical circular plate model in terms of the accuracy of calculating the maximum cap deflection under 105Pa differential pressure. The simulated package performance illustrates the significance of several parameters such as the package geometry, external hydrostatic pressure, residual stresses in the thin film, and the ambient temperature. simulations further show that a circular package of 180μm diameter, featuring an 8μm thick cap and a central supporting pillar of 20μm diameter can withstand hydrostatic pressures up to 9MPa, which could occur during the process of plastic packaging with an epoxy molding compound. Furthermore, the thermal expansion mismatch between the different materials composing the thin film package poses a challenge to fulfill the reliability characteristics of these packages. It is however possible, based on FEM simulation results, to achieve reliable operation in the temperature range between -55°C and +125°C for a circular package of 6μm cap thickness and 250μm diameter without a supporting pillar. ©2010 EEE.

关键词： Thin films

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modeling of digital background calibration with signal-dependent dithering for A 14-bit, 100-MS/s pipelined ADC

Modeling of digital background calibration with signal-depen...

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2nd Asia Pacific conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2010

作者： Sun, Kexu Wang, Xuan He, Lenian Institute of VLSI Design Zhejiang University Hangzhou China

ISBN: (纸本)9781424467372

This paper presents a scheme of 14-bit 100MS/s pipelined analog-to-digital converters (ADCs) with digital calibration. Signal-dependent pseudo-random dithering has been used in the proposed model to measure the errors caused by finite gain and capacitors mismatch in multiplying digital-to-analog converters and correct them in the digital domain. Comparing with fixed-magnitude PN dithering, a signal-dependent dithering scheme has an advantage of injecting larger dithering, so that the signal decorrelation time could be shorter while the signal range maintains the same. According to the calibration scheme, a behavior model has been established, furthermore the simulation results showed that when the ADC worked at the sampling speed of lOOMS/s, a 14-bit pipelined ADC with 0.1% capacitors mismatch achieved a signal-to-noise and distortion ratio of 74 dB, and the INL could be limited within ±0.9 LSB.

关键词： Digital to analog conversion

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Reliability modeling on a MOSFET power package based on embedded die technology

Reliability modeling on a MOSFET power package based on embe...

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10th International conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in Micro-Electronics and Micro-Systems

作者： Yang, Daoguo Kengen, Martien Peels, W. G. M. Heyes, David van Driel, W. D. Guilin Univ Elect Technol Gulin Peoples R China NXP Semicond NL-6534 AE Nijmegen Netherlands

ISBN: (纸本)9781424441594

Embedding of discrete semiconductors into substrates has the advantages of achieving high degree of miniaturization, good electrical performance and possible low cost. A MOSFET power package based on the embedded die technology was developed and the demonstrators were built. To reduce cost and time-to-market, thermo-mechanical virtual prototyping is applied to support the package development. 2D and 3D parametric FE models were established to conduct numerical simulations to investigate the thermo-mechanical reliability performance under packaging processes and test conditions. The package design and material variations, such as the thicknesses of the Cu layer and the resin in the RCC foil, the Bond Line Thickness (BLT), the thickness and material properties of prepreg, via dimensions and via-filling, were included in the parametric models. The root cause for die cracking, delamination between the interface die/RCC foil, and cracking of Cu vias were analyzed based on the simulation results. Verification of the modeling results was conducted through comparison with the test results. The results indicate that the prediction from the FE modeling matches reasonably well with the test results. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： Dies

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modeling of MIM capacitors in 0.25 μm SiGe BiCMOS process up to 140 GHz

Modeling of MIM capacitors in 0.25 μm SiGe BiCMOS process u...

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作者： Hamidian, Amin Zhang, Zihui Subramanian, Viswanathan Boeck, Georg Microwave Engineering Laboratory Berlin Institute of Technology Einsteinufer 25 10587 Berlin Germany

ISBN: (纸本)9783981375404

This paper presents a modeling technique for metal-insulator-metal capacitors up to 140 GHz realized in a high performance 0.25 μm SiGe BiCMOS process. The presented modeling technique is also applicable for different semiconductor technologies. Starting from the parasitic effect of capacitor plates until the substrate and ground effects, the method implemented here includes all the significant parasitic elements. On-chip coupling elements between the capacitor to ground and substrate have also been considered. The modeled capacitors have been compared with electromagnetic simulations and measurements. The results show a very good accuracy of the model for millimeter-wave frequencies which makes it quite appropriate for circuit design in V-band and W-band frequencies. As a case study, the simulation results of a power amplifier designed with help of this model is presented and compared with measurement and full electromagnetic simulation results.

关键词： Electromagnetic simulation

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Analytical inversion-mode varactor modeling based on the EKV model and its application to RF VCO design

Analytical inversion-mode varactor modeling based on the EKV...

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作者： Bremer, Jan-K. Peikert, Tim Mathis, Wolfgang Institute of Theoretical Electrical Engineering Leibniz University of Hannover Germany

ISBN: (纸本)9788392875635

An analytical modeling approach for the CV-characteristics of inversion-mode MOS varactors that is based on the continuous EKV model equations is presented. Based on this approach it is possible to obtain an analytical expression for the effective large signal capacitance of varactors incorporated into a VCO and to calculate and optimize the resulting VCO tuning sensitivity KVCO. We present a simple but quite accurate hyperbolic tangent approximation for the CV-characteristic of inversion-mode MOS varactors that depends on selected design variables and is therefore well suited to be used in a systematic VCO design flow. In order to verify the validity and accuracy of the modeling approach the CV-characteristics obtained by using the EKV based simulation model are compared with Spectre (Cadence) simulations using a BSIM 3.3 transistor model. As reference semiconductor technology we use a 0.35 μm CMOS process (C35) from austriamicrosytems (AMS). © 2010 by Department of microelectronics & Computer Science, Technical University of Lodz.

关键词： Varactors

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A hybrid Verilog-A and equation-defined subcircuit approach to MOS switched current analog cell modeling and simulation in the transient and large signal AC domains

A hybrid Verilog-A and equation-defined subcircuit approach ...

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作者： Brinson, M.E. Jahn, S. Nabijou, H. Faculty of Computing London Metropolitan University London United Kingdom

ISBN: (纸本)9788392875635

Conventional modeling and simulation of two phase switched current MOS integrated circuits is normally undertaken at semiconductor device level. This allows primary and secondary circuit effects to be studied and characterized. However, with the growing complexity of these circuits, transient domain simulation times can become prohibitively long, restricting the size of circuit that can be easily investigated. Measurable reductions in transient simulation run times can be achieved by modeling part, or all, of a switched current design as a macromodel. This paper introduces a hybrid approach to MOS switched current circuit modeling that combines the primary features of compact device modeling with functional circuit macromodeling. To illustrate the proposed hybrid modeling procedure the properties, and simulation model, of a MOS switched current analog memory cell are described. The material presented also demonstrates how recent trends in Quite universal circuit simulator (Qucs) technology promote embedded Verilog-A models and equation-defined subcircuits as integral elements in mixed-mode circuit and system design. © 2010 by Department of microelectronics & Computer Science, Technical University of Lodz.

关键词： Timing circuits

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High-speed power system stability simulation using analog computation: Systematic error analysis

High-speed power system stability simulation using analog co...

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作者： Nagel, Ira Fabre, Laurent Cherkaoui, Rachid Kayal, Maher Electronics Laboratory and Power Systems Laboratory Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9788392875635

This paper joins a series of papers dealing with high-speed power system emulators. It clarifies the last details about the system level of the AC emulation approach by analyzing and quantifying the systematic errors introduced during modeling. Thereby a new optimized generator model has been developed. Its main advantage is improved stability. The functionality of this optimized model is proven by behavioral simulation comparing its results to results of a numerical reference simulator and to the original generator model. © 2010 by Department of microelectronics & Computer Science, Technical University of Lodz.

关键词： Electric power system stability

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Silicon implementation of micro pressure sensor

Silicon implementation of micro pressure sensor

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2010 International conference on Electronic Devices, Systems and Applications, ICEDSA2010

作者： Wahab, Yufridin Zayegh, Aladin Begg, Rezaul Centre for Industrial Collaboration School of Microelectronic Engineering Universiti Malaysia Perlis Kangar Malaysia Centre for Microelectronics and Telecommunication Centre for Ageing Rehab. Exercise and Sport Science Victoria University Melbourne VIC Australia

ISBN: (纸本)9781424466320

Pressure sensing is one of the mostly performed measurement encompassing varieties of applications. The latest technology such as silicon based Micro-electromechanical Systems (MEMS) technology is favoured due to its competitive cost and proven performance. In our research, MEMS pressure sensor for biomedical application is investigated. There are a number of stages involved in our research for implementation of a MEMS pressure sensor which includes application review, conceptual design, modeling, simulation, tape-out, fabrication and characterization. A highly proven technology offered by Infineon Technologies SensorNor AS is used in this research and the requirements are discussed. Recently, the device is successfully implemented on silicon and our research is now entering the characterization stage. In this paper, the research work prior to fabrication, the fabrication result and the post foundry packaging tasks for full device characterization are discussed. Future works are also discussed in the final section. ©2010 IEEE.

关键词： Pressure sensors

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design experiences of a CMOS LNA for mm-waves

Design experiences of a CMOS LNA for mm-waves

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Enrique Rivera Parada Steve Tanner Cyril Botteron Pierre-André Farine Electronics & Signal Processing Laboratory Ecole Polytechnique Fédérale de Lausanne Neuchatel Switzerland

This paper describes some of the design experiences achieved during the design, simulation and characterization of a Complementary Metal-Oxide Semiconductor (CMOS) LNA which has been designed for 24GHz and fabricated in a standard 0.180 μm technology. More specifically, some technological limitations of the CMOS process for mm-wave applications are considered, before showing the outcomes of the schematic and post-layout simulations as well as the measurements and discussing the reasons for the difference between simulations and measurements. It is shown that the simulation results can be significantly improved using Electro-Magnetic (EM) post-layout simulations. Moreover, a post-layout simulation methodology allowing a straightforward integration of the EM simulations into the workflow is proposed.

关键词： Integrated circuit modeling Semiconductor device modeling Layout Transistors Gain CMOS integrated circuits simulation

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