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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

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Study on 3D Virtual Reality modeling

Study on 3D Virtual Reality Modeling

引用

International conference on Material and Manufacturing Technology

作者： Yue, Xuejun Hong, Tiansheng Xu, Xing Wu, Weibin South China Agr Univ Coll Engn 483 Wushan Guangzhou Guangdong Peoples R China South China Agr Univ Key Lab Key Technol Agr Machine & Equipment Guangzhou Guangdong Peoples R China South China Agr Univ Coll Engn Minist Educ Guangzhou Guangdong Peoples R China

ISBN: (纸本)9780878492435

We build out a very vivid and real conditions environment based on the virtual reality of a simulation computer technology, so that users can be in a virtual environment through the man-machine interface with a virtual environment direct interaction. This paper studies 3d virtual model development and integration including the system design to realize the functions and systems integration. In its implementation. we use the model tool, 3 D R C to structure three-dimensional model, and the model tool, and finally we use virtools tool to achieve a three-dimensional with the establishment of virtual scene model. Virtual reality (virtual reality, VR) is a computer senior man-machine interface on the basic feature of absorbion. interactiveness and constructiveness [1,2]. Specifically, virtual reality is a computer that creates the stereoscopic spaces, and users can interact space objects in the interaction and watch the operation of some part of the objects in space, and freely move with the users' will so that a sense of integration and participation are produced[3,4]. It is used in computer technology at the core of modern high technology,which means to build a realistic view, hear and touch the integration of a virtual environment with the necessary equipment and a virtual environment of the interaction and mutual influence, which results in the "immersion" be true of the environment and feel[5-7]. VR technology is computer technology, computer graphics, computer simulations visual and technical, visual physiology, psychology, the microelectronics visual display technique, solid technology, sensing to measure the technical, technological, information technology, and voice recognition software engineering and technology, integrated man-machine the skill interfacing, and network technology and artificial intelligence technology and the achievement of other high technology. Since the birth of a virtual reality technology, it has the huge economy. military and the Internet

关键词： Virtual Reality Virtual Campus Three dimension reconstruction

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Hierarchical performance estimation of analog blocks using Pareto Fronts

Hierarchical performance estimation of analog blocks using P...

引用

Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Engin Deniz Günhan Dündar Department of Electronic and Communication Engineering Dogus University Istanbul Turkey Department of Electrical and Electronics Engineering Bogazici University Istanbul Turkey Department of Electronic and Communication Engineering Dogus University

This paper presents a general approach for hierarchical performance estimation (PE) of any analog system. Not only PE is evaluated by the extracted Pareto Fronts (PF) but also an approximate design of the system is obtained. PE of an analog system requires a well-determined performance design space (PDS) exploration for a given technology. PF which is a very useful technique for evaluating the performance space, provides the set of all optimal trade-offs of competing performances of a given block. Thus, the designer can easily get insight into the capability of the system. In this work, a three-level system is divided into its subsystems and PF of each subsystem is determined. Then, hierarchical methodology of PF composition is applied from lower levels to higher levels so the PF of the main system is obtained with less computational effort. The novelty of the work lies on using simple algorithms instead of complex optimization algorithms and simulation loops.

关键词： Solid modeling Mathematical model Integrated circuit modeling Optimization design automation Space exploration Topology

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Cycle accurate simulator generator for NoGap

Cycle accurate simulator generator for NoGap

引用

Asia Pacific conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Per Karlström Faisal Akhlaq Sumathi Loganathan Wenbiao Zhou Dake Liu Department of EE Linkoping university Linköping Sweden

Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. However designing an ASIP is complicated by the fact that not only the processor but, also tools such as assemblers, simulators, and compilers have to be designed. Novel Generator of Accelerators And Processors (NoGap), is a design automation tool for ASIP design that imposes very few limitations on the designer. Yet NoGap supports the designer by automating much of the tedious and error prone tasks associated with ASIP design. This paper will present the techniques used to generate a stand alone software simulator for a processor designed with NoGap. The focus will be on the core algorithms used. Two main problems had to be solved, simulation of a data path graph and simulation of leaf functional units. The concept of sequentialization is introduced and the algorithms used to perform both the leaf unit sequentialization and data path sequentialization is presented. A key component of the sequentialization process is the Micro Architecture Generation Essentials (Mage) dependency graph. The mage dependency graph and the algorithm used for its generation are also presented in this paper. A NoGap simulator was generated for a simple processor and the results were verified.

关键词： Registers Program processors Multiplexing Pipelines Solid modeling Generators Hardware

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simulation of line-edge roughness effects in silicon nanowire MOSFETs

Simulation of line-edge roughness effects in silicon nanowir...

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International conference on simulation of Semiconductor Processes and Devices (SISPAD)

作者： Tao Yu Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, the effects of nanowire (NW) line-edge roughness (LER) in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) are investigated by 3-D statistical simulation in terms of both performance variation and mean value degradation. A physical model is developed for NW LER induced performance degradation in SNWTs for the first time. The results indicate large performance mean value degradations due to NW LER in SNWTs. However, the LER induced parameter variation is still acceptable. In addition, as the LER correlation length (Λ) scales beyond the gate length, new distribution of performance parameters is observed, which has dual-peaks rather than single in conventional Gaussian distribution. The optimization for NW LER parameters is given for SNWT design as well.

关键词： Logic gates Degradation Silicon Performance evaluation MOSFETs Integrated circuit modeling Solid modeling

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design of probabilistic-based Markov Random Field logic gates in 65nm CMOS technology

Design of probabilistic-based Markov Random Field logic gate...

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International SoC design conference, ISOCC

作者： Zhenghao Lu Xiao Peng Yu Kiat Seng Yeo Department of Microelectronics Soochow University Suzhou China Institute of VLSI Design University of Zhejiang Hangzhou China Division of Circuits and Systems School of Electrical and Electronic Engineering Nanyang Technological University Singapore

As the VLSI technology node is getting into the sub-100 nm regime, the reliability issues caused by random interferences such as noise, process variations and manufacturing defects are changing the nature of digital computation from deterministic to probabilistic. This paper studies the principle of probabilistic-based Markov Random Field (MRF) design methodology for CMOS static logic gates. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. A Differential Cascode Voltage Switch (DCVS) based MRF logic design method is proposed, which presents substantial noise immunity improvement over the normal MRF logic circuits. The proposed method is validated by simulation in 65 nm CMOS technology.

关键词： Inverters Noise Semiconductor device modeling Integrated circuit modeling CMOS integrated circuits Probabilistic logic Markov random fields

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modeling of digital background calibration with signal-dependent dithering for a 14-bit, 100-MS/s pipelined ADC

Modeling of digital background calibration with signal-depen...

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Asia Pacific conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Kexu Sun Xuan Wang Lenian He Institute of VLSI Design University of Zhejiang Hangzhou China

This paper presents a scheme of 14-bit 100MS/s pipelined analog-to-digital converters (ADCs) with digital calibration. Signal-dependent pseudo-random dithering has been used in the proposed model to measure the errors caused by finite gain and capacitors mismatch in multiplying digital-to-analog converters and correct them in the digital domain. Comparing with fixed-magnitude PN dithering, a signal-dependent dithering scheme has an advantage of injecting larger dithering, so that the signal decorrelation time could be shorter while the signal range maintains the same. According to the calibration scheme, a behavior model has been established, furthermore the simulation results showed that when the ADC worked at the sampling speed of 100MS/s, a 14-bit pipelined ADC with 0.1% capacitors mismatch achieved a signal-to-noise and distortion ratio of 74 dB, and the INL could be limited within ±0.9 LSB.

关键词： Calibration Capacitors Gain Noise simulation Accuracy Converters

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Alpha-emitter induced soft-errors in CMOS 130nm SRAM: Real-time underground experiment and Monte-Carlo simulation

Alpha-emitter induced soft-errors in CMOS 130nm SRAM: Real-t...

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IEEE International conference on Integrated Circuit design and Technology (ICICDT)

作者： S. Martinie S. Uznanski J.L. Autran P. Roche G. Gasiot D. Munteanu S. Sauze P. Loaiza G. Warot M. Zampaolo Institute of Materials Microelectronics and Nanosciences of Provence CNRS Aix Marseille University Marseilles France Jean Monnet ST Microelectronics S.A. Crolles France Institute of Materials Microelectronics and Nanosciences of Provence CNRS Aix Marseille University Saint Etienne en Devoluy France Carré Sciences Laboratoire Souterrain de Modane Modane France

ISBN: (纸本)9781424457731;9781424457748;9781424457755

This work reports a long-duration (> 2 years) realtime characterization study of SRAM memories at the underground laboratory of Modane (LSM) to quantify alpha emitter radioactive impurities present in the circuit materials and responsible of soft-errors detected in absence of atmospheric neutrons. Experimental data have been obtained using ~3.5 Gbit of SRAMs manufactured in CMOS 130 nm technology. In a second part of this work, the underground experiment is simulated using a Monte-Carlo code to extract the contamination level related to the disintegration chain of uranium in silicon at secular equilibrium. Results are finally compared to data obtained from experimental counting experiments using an ultra low background alpha-particle gas proportional counter.

关键词： Random access memory CMOS technology Laboratories Impurities Radioactive materials Neutrons Manufacturing Atmospheric modeling Circuit simulation Data mining

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Machine Vision for Starfruit (Averrhua Carambola) Inspection

Machine Vision for Starfruit (Averrhua Carambola) Inspection

引用

Asia International conference on modeling & simulation

作者： M.F. Ahmad Kamil Musa Mokji U.U. Sheikh S.A.R. Abu-Bakar Department of Microelectronics and Computer Engineering Faculty of Electrical Engineering Universiti Teknologi Malaysia Skudai Johor Malaysia

ISBN: (纸本)9781424471966;9780769540627

This paper describes a machine vision system for starfruit inspection. We propose a setup framework for image acquisition. The acquired image is then analyzed using convex hull algorithm to determine the shape defect and classify the starfruit. This paper proposes a hardware design to capture starfruit images from three sides so as to obtain overall shape of the fruit. The framework was simulated using Autodesk 3dsmax 2010 software and prototype hardware was built to verify the design.

关键词： Machine vision Inspection Shape Hardware Humans Cameras Image analysis Lighting Asia Analytical models

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Bottom-up Digital Music simulation System Under Program Control

Bottom-up Digital Music Simulation System Under Program Cont...

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International conference on MultiMedia and Information Technology, MMIT

作者： Li Yue Luo Yujia Ma Chunyan College of Software and Microelectronics Northwestern Polytechnical University Xi'an China

ISBN: (纸本)9781424466016;9780769540085

With the popularity of Internet applications, digital music has entered our daily life deep. Research in the field of digital music draws more attention of interested people; however, there still has no set of complete design architecture about the digital music system simulation. As a result, many people interested in digital music and programmers have difficulty to study and research in this field. This paper will describe a complete simulation process of the digital music system under program control and in an object oriented way. The article will take a bottom-up approach to describe the file structure, running process, encapsulation way, program interface, logical structure simulation and user interface of digital music system.

关键词： Control system synthesis Object oriented modeling Synthesizers Instruments Hardware Computer architecture Production Encapsulation Keyboards Multiple signal classification

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Static Average Case Power Estimation Technique for Block Ciphers

Static Average Case Power Estimation Technique for Block Cip...

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Euromicro Symposium on Digital System design

作者： Tingcong Ye Dilip Vasudevan Jiaoyan Chen Emanuel Popovici Michel Schellekens Centre for Efficiency Oriented Languages CEOL and Department of Microelectronics University College Cork Cork Ireland

In this paper a new static average case dynamic power estimation technique is introduced based on the property of randomness preservation for digital circuits. The proposed technique is validated by estimating the average case power for a block cipher, DES with a lower estimation error percentage of 0.9481 % and lesser simulation time with a pattern reduction of (2" × 2"!)-(2" × 2" × 2) for n bit design. The same technique can be extended to any block cipher, including the AES and IDEA-NXT.

关键词： Logic gates Estimation Power demand Registers Power generation Integrated circuit modeling

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