检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,367 篇 会议
46 篇 期刊文献
6 册 图书

馆藏范围

1,419 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

615 篇 工学
- 387 篇 电气工程
- 246 篇 电子科学与技术（可...
- 221 篇 计算机科学与技术...
- 128 篇 材料科学与工程（可...
- 119 篇 软件工程
- 89 篇 机械工程
- 66 篇 动力工程及工程热...
- 59 篇 控制科学与工程
- 42 篇 化学工程与技术
- 35 篇 信息与通信工程
- 31 篇 仪器科学与技术
- 23 篇 力学（可授工学、理...
- 15 篇 冶金工程
- 15 篇 生物医学工程（可授...
- 10 篇 建筑学
- 9 篇 光学工程
- 9 篇 土木工程
- 8 篇 交通运输工程
- 8 篇 安全科学与工程
- 7 篇 生物工程
255 篇 理学
- 146 篇 物理学
- 116 篇 数学
- 45 篇 化学
- 22 篇 系统科学
- 10 篇 生物学
- 10 篇 统计学（可授理学、...
38 篇 管理学
- 37 篇 管理科学与工程(可...
8 篇 医学
- 7 篇 临床医学
- 6 篇 基础医学(可授医学...
- 5 篇 药学(可授医学、理...
4 篇 法学
4 篇 艺术学
2 篇 农学
1 篇 经济学
1 篇 教育学

主题

272 篇 computational mo...
230 篇 integrated circu...
190 篇 circuit simulati...
179 篇 microelectronics
126 篇 semiconductor de...
115 篇 analytical model...
107 篇 solid modeling
96 篇 mathematical mod...
65 篇 simulation
61 篇 silicon
58 篇 predictive model...
53 篇 hardware design ...
53 篇 micromechanical ...
50 篇 load modeling
50 篇 hardware
49 篇 cmos technology
47 篇 spice
45 篇 design automatio...
43 篇 logic gates
42 篇 finite element a...

机构

13 篇 institute of mic...
13 篇 institute of mic...
12 篇 institute of mic...
7 篇 institute of mic...
6 篇 department of mi...
6 篇 institute of mic...
6 篇 department of mi...
6 篇 school of softwa...
5 篇 school of microe...
5 篇 nxp semiconducto...
5 篇 national microel...
5 篇 school of microe...
5 篇 institute of mic...
5 篇 philips applied ...
5 篇 imec leuven
5 篇 institute of mic...
5 篇 amic angewandte ...
5 篇 agilent technol ...
5 篇 delft university...
4 篇 shanghai researc...

作者

10 篇 xiaowu zhang
10 篇 roca e.
9 篇 castro-lopez r.
9 篇 a. napieralski
8 篇 rodriguez r.
8 篇 nafria m.
7 篇 l.j. ernst
7 篇 g.q. zhang
7 篇 martin-martinez ...
7 篇 sven rzepka
7 篇 fernandez f. v.
7 篇 s. selberherr
7 篇 zhang gq
6 篇 andrzej napieral...
6 篇 m.k. iyer
6 篇 ru huang
6 篇 n. ranganathan
6 篇 k.m.b. jansen
5 篇 khaoula mbarek
5 篇 sami ghedira

语言

1,398 篇 英文
10 篇 中文
8 篇 其他
3 篇 德文

检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是921-930 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

modeling of the Effective Mobility for Polysilicon Thin Film Transistor

Modeling of the Effective Mobility for Polysilicon Thin Film...

引用

2008 9th International conference on Solid-State and Integrated-Circuit Technology

作者： Bing-Hui Yan*, Bin Li, Ruo-He Yao, Xue-Ren Zheng Institute of microelectronics, School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510640, P. R. China

In this paper, a model of the effective mobility for the on-current of p-Si TFT is proposed, taking into account the gain size, the drain bias, the imperfection crystal scattering mechanism, and the surface-roughness scattering mechanism. It is found that at the linearity region, the effective mobility decreases with the drain bias increasing and increases with the grain size increasing. The simulation results are in a good agreement with the experimental data.

关键词： modeling of the Effective Mobility for Polysilicon Thin Film Transistor TFT

来源：评论

学校读者我要写书评

暂无评论

Development of multi-gate mosfet models for circuit simulation with a compact modeling platform

Development of multi-gate mosfet models for circuit simulati...

引用

International conference on Mixed design of Integrated Circuits and Systems (MIXDES)

作者： H.J. Mattausch M. Chan J. He H. Koike M. Miura-Mattausch T. Nakagawa Y. J. Park T. Tsutsumi Z. Yu Graduate School of Advanced Sciences of Matter Hiroshima University HigashiHiroshima Japan Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Hong Kong China School of Computer & Information Engineering Shenzhen Graduate School Peking University Shenzhen China Nan electronics Research Institute National Institute for Advanced Industrial Science and Technology Tsukuba Ibaraki Japan School of Electrical Engineering and Computer Science and NSI-NCRC Seoul National University Seoul South Korea Department of Computer Science School of Science and Technology Meiji University Kawasaki Japan Institute of Microelectronics Tsinghua University Beijing China

Research is reported that aims at a framework for efficient development of multi-gate MOSFET models for circuit simulation and is carried out in an international collaboration among different research teams. A common platform for compact-model development, based on the Verilog-A language, is also constructed to verify as well as to efficiently merge the individual contributions from each collaborator into the final completed compact model.

关键词：

来源：评论

学校读者我要写书评

暂无评论

modeling of the Turn-On Characteristics of Poly-silicon Thin-Film Transistors with Considering Kink Effect

Modeling of the Turn-On Characteristics of Poly-silicon Thin...

引用

2008 9th International conference on Solid-State and Integrated-Circuit Technology

作者： Bin Li Ting Chen Xue-Ren Zheng Institute of Microelectronics School of Electronic and Information EngineeringSouth China University of Technology

A semi-empirical analytical model of the turn-on characteristics of poly-silicon thin-film transistor(TFT) with considering kink effect is presented based on the physical characteristics of poly-silicon thin *** reference to the approach of modeling the kink effect in SOI devices and considering the grain boundaries in poly-silicon thin film,the dc cliaracteristics of poly-silicon TFT are simulated,including drain induced grain boundary lowering(DIGBL) effect,impact ionization,floating body effect,parasitic bipolar transistor(PBT) effect,*** simulation results show a good agreement with the experimental data.

关键词： modeling of the Turn-On Characteristics of Poly-silicon Thin-Film Transistors with Considering Kink Effect TFT

来源：评论

学校读者我要写书评

暂无评论

Sapphire-removed induced the deformation of high power InGaN light emitting diodes

Sapphire-removed induced the deformation of high power InGaN...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： C. N. Han T .L. Chou C. F. Huang K. N. Chiang Advanced Microsystem Packaging and Nano-Mechanics Research Laboratory Department of Power Mechanical Engineering National Tsing Hua University Hsinchu Taiwan Epistar Corporation Limited Hsinchu Taiwan

Thick copper films on vertically structures InGaN LEDs play a critical role after sapphire removed. The most commonly used GaN thin film growth technique is metal-organic chemical vapor deposition (MOCVD), which provides a high growth temperature, as a result, high intrinsic stress takes place between sapphire and InGaN surface. If the aforementioned metal supporter experiences a large warpage induced from intrinsic stress after sapphire removed, the subsequent processes would be very difficult to carried out. To solve the above issue, a finite element (FE) numerical simulation was employed for stress-strain behavior analysis of the LED device, the results reveal that, increasing the thickness of metal layer or implementing a pre-metal deposition buffer layer can apparently reduce the device warpage after sapphire removal. Based on the above design concepts, the experimental result depicts that, the warpage of LED wafer can be effectively reduced by 25% when metal layer increased from 62.5 um to 82.5 um, which shows good agreements with FE result, hence validates the established research methodology. And more importantly, based on the process modelling and sapphire-removal simulation-technique developed in this study, an optimal novel LED structure is designed for the reduction of process induced warpage. To conclude, a LED chip structural design-process modeling-fabrication methodology was successfully developed, and can be further contributed to the LED industry.

关键词： Light emitting diodes Stress Copper Gallium nitride Sputtering Chemical vapor deposition MOCVD Temperature Finite element methods Numerical simulation

来源：评论

学校读者我要写书评

暂无评论

modeling and designing of RF MEMS switch using ANSYS

Modeling and designing of RF MEMS switch using ANSYS

引用

International conference on Emerging Technologies, ICET

作者： Aamir F. Malik M. Shoaib S. Naseem S. Riaz Microelectronics Research Center University of Punjab Lahore Pakistan

This paper presents the design optimization and simulation of low-voltage series and capacitive radio frequency (RF) Micro-electromechanical (MEMS) switches using ANSYS Multiphysics. First, a series switch is simulated using shape memory alloy (SMA) which shows that the use of SMA beam to actuate switching, allows the excitation voltage to be relatively much lower (5 V) compared to that needed for electrostatic actuation (30 V). Secondly, in the capacitive switch structure both contact plates of the switch are designed as displaceable membranes with similar dimensions and conditions, differing on only membrane materials. The obtained results (5 V) indicate about 30% reductions in actuation voltage from the conventional single beam (15 V). The stress on the beam due to the actuation voltage is also reduced increasing the switching life time.

关键词： Switches Radiofrequency microelectromechanical systems Voltage Radio frequency Biomembranes design optimization Micromechanical devices Shape memory alloys Electrostatic actuators Contacts

来源：评论

学校读者我要写书评

暂无评论

Employing 65 nm CMOS SOI for 60 GHz WPAN Applications

Employing 65 nm CMOS SOI for 60 GHz WPAN Applications

引用

2008 IEEE International conference on Microwaves, Communications, Antennas and Electronic Systems

作者： Christopher Mounet Alexandre Siligaris Alain Michel Massimo Capodiferro CEA LETI MINATEC Grenoble France Ansoft Corporation Buc France Ansoft Corporation Rome Italy

Increasing memory capacity in mobile devices together with the transition to wireless connections for consumer electronics and PC products is driving the need for wireless equipment with data rates of up to 10 Gbps. The worldwide 7GHz unlicensed band around 60GHz provides the opportunity for multi-gigabit-persecond wireless communication and is a real opportunity for developing next generation Wireless Personal Area Networks (WPANs). Mass production requirements coupled with the cost constraints of mobile devices result in a need to identify an alternative to existing, expensive Gallium Arsenide (GaAs) and Indium Phosphide (InP) technologies, currently used widely in millimeter-wave (mm-wave) Microwave Monolithic Integrated Circuit (MMIC) fabrication. Complementary Metal Oxide Semiconductor (CMOS) devices using Silicon-On-Insulator (SOI) technology at the 65nm technology node currently show very attractive performance for mm-wave MMIC design [1]. This paper discusses the design of a 60GHz Low Noise Amplifier (LNA) using a standard low power SOI CMOS process from ST microelectronics. After an overview of WPAN applications, we will outline the technology as well as the mm-wave design challenges. Using recent work on Coplanar Waveguide (CPW) modeling [2], we will describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip passive devices. A short description of the transistor model will also be provided. Finally, after a short description of the transceiver and its building blocks, we will discuss the details of the LNA design and show how the simulation results compare to the measurements.

关键词： Coplanar waveguides CMOS technology Semiconductor device modeling Millimeter wave technology MMICs Electromagnetic modeling Analytical models Integrated circuit technology Personal digital assistants Bandwidth

来源：评论

学校读者我要写书评

暂无评论

modeling of smart compliant electro-active polymer actuator

Modeling of smart compliant electro-active polymer actuator

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： S. Soulimane M. Al Ahmad M. Matmat H. Camon LAAS CNRS Toulouse France UPS INSA INP ISAE Université de Toulouse Toulouse France LAAS CNRS Toulouse

The electro-active polymers smart materials are typically characterized by then large strain, low modulus, and high compliance which make them suitable and of efficient use in area of actuation. Dielectric electroactive polymer (DEAP) actuators combine high energy density with large displacements, low power consumption and fast response time, which make them very attractive for a wide variety of applications, both on the macro- and micro-scale. The design and fabrication of a proper actuator for micro pump and micro mirror applications requires an explicit knowledge of the involving materials as well as the miniaturizations techniques. The prediction of the mechanical behavior when dc bias is applied is often performed thought the help of suitable multi-physics tools. These tools generally based on the finite element analysis algorithms. The results of these simulations will provide quantitative characterizations concerning the actuation spatial resolution, and also allows optimizing the fabrication process in terms of materials and integrations steps. The scope of this work is to shows how a multi-physics tool such as CoventorWare is used to anticipate the electromechanical behaviour of micro actuator comprising a PDMS material for actuation. The simulation investigates the electromechanical coupling in the dielectric elastomer actuators.

关键词： Polymers Intelligent actuators Dielectric materials Fabrication Capacitive sensors Energy consumption Delay Micropumps Mirrors Finite element methods

来源：评论

学校读者我要写书评

暂无评论

modeling of the Turn-On Characteristics of Poly-silicon Thin-Film Transistors with Considering Kink Effect

Modeling of the Turn-On Characteristics of Poly-silicon Thin...

引用

2008 9th International conference on Solid-State and Integrated-Circuit Technology

作者： Bin Li*, Ting Chen, Xue-Ren Zheng Institute of microelectronics, School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510640, P. R. China

A semi-empirical analytical model of the turn-on characteristics of poly-silicon thin-film transistor (TFT) with considering kink effect is presented based on the physical characteristics of poly-silicon thin film. With reference to the approach of modeling the kink effect in SOI devices and considering the grain boundaries in poly-silicon thin film, the dc characteristics of poly-silicon TFT are simulated, including drain induced grain boundary lowering (DIGBL) effect, impact ionization, floating body effect, parasitic bipolar transistor (PBT) effect, etc. The simulation results show a good agreement with the experimental data.

关键词： VDS TFT modeling of the Turn-On Characteristics of Poly-silicon Thin-Film Transistors with Considering Kink Effect

来源：评论

学校读者我要写书评

暂无评论

design and Optimization of Bump Structures of Large Die Fine Pitch Copper/Low-k FCBGA and Copper Post Interconnections

Design and Optimization of Bump Structures of Large Die Fine...

引用

Electronics Packaging Technology conference (EPTC)

作者： Kalyan Biswas Shiguo Liu Xiaowu Zhang TC Chai IBIDEN Singapore Private Limited Singapore Singapore Institute of Microelectronics Singapore

This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design, metal cracks at RDL were found for the conventional SnAg bump and Cu post samples. In order to improve the bump structure design a thermo-mechanical modeling was performed to identify the effects of different design parameters and to identify the best solution to achieve reliable assembly performance. simulation has identified few contributing factors: RDL pad thickness, dielectric thickness, UBM via size, UBM size and chip thickness. Then a series of parametric study was performed to identify the set of design points at which the finite element analysis provides the lowest stress level in RDL pad and low-k layer of the chip. Based on the results a guideline for bump configuration is proposed. To confirm the assembly performance of the optimized bump structure, the improved design has been incorporated into final test vehicle, which has a better assembly performance with no RDL pad metal crack found.

关键词： Copper design optimization Assembly Thermomechanical processes Dielectrics Parametric study Finite element methods Performance analysis Stress Guidelines

来源：评论

学校读者我要写书评

暂无评论

Optimization of high density interconnections (HDI) printed circuit boards robustness

Optimization of high density interconnections (HDI) printed ...

引用

Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： A. Chaillot O. Maire C. Munier L. Tonnelier C. Chastanet Eads France/Innovation Works Suresnes France Airbus France Suresnes France

This document provides a first "how-to" guide for modelling thermo-mechanical behaviour of an HDI board submitted to reflow process using finite element modelling (FEM). The parametric model constructed here includes microvias, buried vias and plated through holes (PTH). The HDI board is composed of a central core and two micro via layers on each external side. Firstly, equivalent material properties of the complete stack-up were determined according to three pre-preg materials (mat. A as ref., mat. B and mat. C) and core thickness (0.9, 1.1 and 1.3 mm as ref.) below and above their glass transition temperature, Tg. Several simulations were then done on the reference board in order to evaluate the impact of the temperature shock (above Tg) on the ageing of the HDI board. Finally, we focused on the behaviour of the buried via, which is a highly critic part of the HDI board. The objective was to optimize, for the different assembly processes (leaded and lead free), the choice of the FR4 material types as well as the design rules (core thickness and buried via diameter for example). Discussions on results in link with experimental data and calculation approximations are done in this study in order to better understand the failure roots and to determine way of simulation methodology improvements.

关键词： Integrated circuit interconnections Printed circuits Robustness Semiconductor device modeling Temperature Environmentally friendly manufacturing techniques Thermomechanical processes Finite element methods Parametric statistics Material properties

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共142页 << < 89 90 91 92 93 94 95 96 97 98 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：