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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： J.-S. Goo Q. Chen A. Pandey Y. Apanovich T. Ly V. Wason N. Subba C. Thuruthiyil A. B. Icel Computing Solutions Group Advanced Micro Devices Inc. Sunnyvale CA USA

ISBN: (纸本)9781424419548

Accurate extraction of the SPICE model parameter is critical in the CMOS IC design. However, it faces difficult issues in state-of-the-art MOSFET technology. First, the gate CV parameter extraction is challenging due to small values and many extrinsic components that need to be de-embedded. Second, the systematic offset of the gate critical dimension (CD) exists between test structures and circuits, introducing a significant uncertainty. Thus, it is not uncommon that the validation of a circuit-level SPICE model involves arbitrary adjustments of capacitance parameters that undermine the confidence level of the model parameters. This paper presents seamless methodologies to resolve these issues. Circuit-level validation of the methodology is given for 65nm PD-SOI ring oscillators (ROs), covering a wide range of simulation conditions.

关键词： Logic gates Integrated circuit modeling Capacitance Inverters MOSFET circuits Delay simulation

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Lead-free solder material characterization for thermo-mechanical modeling

Lead-free solder material characterization for thermo-mechan...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Edith S. W. Poh W. H. Zhu X. R. Zhang C. K. Wang Anthony Y. S. Sun H. B. Tan Packaging Analysis & Design Center United Technologies Research Center Inc. Singapore Singapore

Systematic mechanical characterization has been done on lead-free solder alloys, i.e., SAC105, SAC205, SAC305, SAC105Ni0.02, and SAC105Ni0.05 as promising alternatives of SnPb solder. Solder joints in service stay in high homologous temperatures that have profound effects on mechanical properties such as creep and the apparent elastic modulus. Mechanical deformation behaviors of bulk solder alloys at temperatures between 298 K and 398 K, as well as strain rates between 10 -5 to 10 -1 under isothermal conditions, have been studied for the above 5 solder alloys with a designed bulk test vehicle. Isostress loading conditions on the solders were also conducted to study creep behaviour. Based on substantial experimental measurement results, the elastic modulus, yield stress and UTS of the various SAC solder alloys show direct relationships with Ag content at temperatures between 298 K and 398 K. The relationships of strain rate, temperature, Ag content and material properties were developed and material constants are presented. Basic material parameters with viscoplastic constitutive relations for solders encompassing temperature and strain rate dependence have been obtained through curve fitting with experimental data. The creep constitutive model has also been established. By implementing the developed creep or viscoplastic constitutive models of solders into FEA models, the life of an electronic package under thermal cycling and drop performance in board level tests can be evaluated. Material compositions such as Ag content and Ni dopant effect are also studied for their influence on mechanical properties. It was reported that Ni dopant could improve solder joint drop performance by changing the microstructure of the material.

关键词： Environmentally friendly manufacturing techniques Lead Thermomechanical processes Temperature Creep Semiconductor process modeling Soldering Mechanical factors Capacitive sensors Strain measurement

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A Framework for modeling, simulation and Automatic Code Generation of Sensor Network Application

A Framework for Modeling, Simulation and Automatic Code Gene...

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IEEE Communications Society conference on Sensor and Ad Hoc Communications and Networks (SECON)

作者： Mohammad Mostafizur Rahman Mozumdar Francesco Gregoretti Luciano Lavagno Laura Vanzago Stefano Olivieri Politecnico di Turino Torino Italy STMicroelectronics Milan Italy MathWorks Torino Italy

Showing functional correctness by simulation before implementation, and preserving it by automated code generation, is extremely useful to reduce the development time for an embedded application. This is even more true for wireless sensor networks, since their nodes often provide very rudimentary debugging facilities, and sufficiently large networks for realistic analysis may be expensive to deploy. While this approach, also known as model-based design, is becoming quite standard for several domains that have similar constraints as wireless sensor networks, such as automotive electronics, there is a lack of tools for this purpose in the WSN world. In order to fill this gap, in this paper we present a framework (based on Simulink, Stateflow and Embedded Coder) in which an engineer can create sensor network components (both at the application and at the protocol level) that can be used as building blocks to model, simulate and automatically generate code for different underlying platforms and operating systems.

关键词： Wireless sensor networks Debugging Operating systems Application software Automotive electronics Automotive engineering Sensor systems and applications Protocols microelectronics Light emitting diodes

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Separating modeling and simulation aspects in hardware/software system design

Separating modeling and simulation aspects in hardware/softw...

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18th International conference on microelectronics (ICM 2006)

作者： Lapalme, J. Aboulhamid, E. M. Nicolescu, G. Rousseau, F. Univ Montreal Montreal PQ Canada Ecole Polytech Montreal PQ Canada TIMA Grenoble France

ISBN: (纸本)9781424407644

Many are working on the productivity gap problem affecting the Electronic design Automation. None of the current paths seems to be a silver bullet but object-oriented framework-based solutions such as SystemC are gaining a great deal of momentum and acceptance. Despite all the efforts which have been spent one the development of these types of solutions, as well as the numerous satellite tools which add a lot of value to the approach;very few efforts have been spent on the cornerstone task of investigating which software design techniques and technologies should be used to develop effective framework-based solutions. The main objective of the article is to present how new software engineering technologies may be used to create better framework-based modeling solutions by promoting separation of concerns between modeling and simulation aspects.

关键词： framework modeling simulation system-level design

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A fully static scheduling approach for fast cycle accurate SystemC simulation of MPSoCs

A fully static scheduling approach for fast cycle accurate S...

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International conference on microelectronics

作者： Buchmann, Richard Greiner, Alain Univ Paris 06 LIP6 4 Pl Jussieu F-75005 Paris France

ISBN: (纸本)9781424418466

This paper presents principles and tools to facilitate Mufti-Processor System on Chips (MPSoCs) design and modeling, and to speed up cycle accurate SystemC simulation. We describe an effective way to build an hardware architecture virtual prototype, using a library of SystemC simulation models based on communicating synchronous finite state machines. This modeling approach supports a fully static scheduling strategy, based on the analysis of the combinational dependency graph. Our static scheduling algorithm has been implemented in the SystemCASS simulator, and provides speed-up of one order of magnitude versus the standard event-driven SystemC simulation engine. The modeling approach proposed in this paper has been adopted by the SoCLIB french national project, that is an open modeling and simulation platform for multi-processors system on chips.

关键词： Scheduling algorithms

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Correlation between chemistry of polymer building blocks and microelectronics reliability

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microelectronics RELIABILITY 2007年第2-3期47卷 290-294页

作者： Bressers, H. J. L. van Driel, W. D. Jansen, K. M. B. Ernst, L. J. Zhang, G. Q. IMO BE Innovat NXP Semicond NL-6534 AE Nijmegen Netherlands Delft Univ Technol NL-2628 CD Delft Netherlands NXP Semicond NL-5600 JZ Eindhoven Netherlands

Among various materials, polymers are widely used in microelectronics as different product constituents, such as encapsulants, conductive or non-conductive adhesives, undertills, molding compounds, insulators, dielectrics, and coatings. The behavior of these polymer constituents determines the performance, such as functionality and reliability, of the final products. Therefore, the successful development of microelectronics depends on, to some extent, the optimal design and processing of polymer materials. Due to the development trends of microelectronics, characterized mainly by ongoing miniaturization down to the nano scale, technology and functionality integration, eco-designing, shorter-time-to-market, development and application of polymers become one of the bottlenecks for microelectronic industry. Aiming at optimizing the product/process development, we have been spending a lot of effort to understand and design polymer behavior in microelectronics, such as material pre-selection, processing, characterization and modeling. Although these efforts are necessary, the ultimate benefits can only be realized if the relationship between chemistry and the behavior can be understood and predicted. This paper presents some results of our effort to establish the links between chemical details of the polymers and microelectronics reliability. (c) 2006 Elsevier Ltd. All rights reserved.

关键词： POLYMERS microelectronics ELECTRONIC packaging RELIABILITY (Engineering)

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Robust analog/RF circuit design with projection-based performance modeling

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IEEE TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 2007年第1期26卷 2-15页

作者： Li, Xin Gopalakrishnan, Padmini Xu, Yang Pileggi, Lawrence T. Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

In this paper, a robust analog design (ROAD) tool for posttuning (i.e., locally optimizing) analog/RF circuits is proposed. Starting from an initial design derived from hand analysis or analog circuit optimization based on simplified models, ROAD extracts accurate performance models via transistor-level simulation and iteratively improves the circuit performance by a sequence of geometric programming steps. Importantly, ROAD sets up all design constraints to include large-scale process and environmental variations, thereby facilitating the tradeoff between yield and performance. A crucial component of ROAD is a novel projection-based scheme for quadratic (both polynomial and posynomial) performance modeling, which allows our approach to scale well to large problem sizes. A key feature of this projection-based scheme is a new implicit power iteration algorithm to find the optimal projection space and extract the unknown model coefficients with robust convergence. The efficacy of ROAD is demonstrated on several circuit examples.

关键词： analog/RF circuit circuit optimization performance model robust design

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MPSoC power estimation framework at transaction level modeling

MPSoC power estimation framework at transaction level modeli...

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19th International conference on microelectronics, ICM

作者： Atitallah, Rabie Ben Niar, Smail Dekeyser, Jean-Luc DaRT Project INRIA-FUTURS France

ISBN: (纸本)9781424418473

Early power estimation is increasingly important in Multiprocessor System-On-Chip (MPSoC) architectures for a reliable design Space Exploration (DSE). In this paper, we present an MPSoC power modeling framework at the Timed Programmer View (PVT) level that offers a good performance/power tradeoff to be found early in the design flow. Using a hybrid power modeling methodology, we developed several power models derived from both physical measurements and analytical expressions. Plugging these power models into the PVT architectural simulator makes it easy to estimate the application's performance and power consumption with high simulation speedup. The effectiveness of our method is illustrated through a DSE for a parallelized version of H.263 encoder application. © 2007 IEEE.

关键词： Multiprocessing systems

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Electronic system level models for functional verification of system-on-chip

Electronic system level models for functional verification o...

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9th International conference on the Experience of designing and Application of CAD Systems in microelectronics

作者： Adamov, Alexander Mostovaya, Karina Syzonenko, Inna Melnik, Alexey Kharkov Natl Univ Radio Elect DAD Dept UA-61166 Kharkov Ukraine

ISBN: (纸本)9789665335870

Modern verification environments based on object-oriented methodology is a system-level solution that manages the process and data for a particular system-on-chip model. These systems give an ability to integrate smaller blocks of design into larger blocks, which may eventually be integrated into a system. That is reason for performing designing and functional verification at a system level, which allow teams to rapidly create large system-on-chip designs by integrating premade blocks. Integrated verification systems used to store and manage huge amount of simulation data. However, when the amount of data is large, it is difficult to analyze and extract information from it. This data can be archived for later use or it can be mined to look for different kind of violations or to get statistical information about the specified design. The paper describes the system-level verification environment for a functional verification System-on-Chip models. With the help of novel approach we can easily use opportunities, that system-level modeling gives its, such as: early software validation of the system, performance analysis of the system, transaction-level verification of the project, architectural analysis of System-on-chip (SoC), power analysis of a chip, searching hardware/software tradeoffs.

关键词： verification system level modeling System-on-Chip data mining knowledge discovery

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Artificial neural network based modeling of GaAsHBT and power amplifier design for wireless communication system

Artificial neural network based modeling of GaAsHBT and powe...

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18th International conference on microelectronics (ICM 2006)

作者： Alam, M. S. Farooq, O. Izharuddin Armstrong, G. A. Aligarh Muslim Univ Dept Elect Engn Coll Engn & Technol Aligarh 202002 Uttar Pradesh India Aligarh Muslim Univ Dept Elect Engn Aligarh 202001 Uttar Pradesh India Queens Univ Belfast Sch Elect & Elect Engn Belfast BT7 1NN Antrim North Ireland

ISBN: (纸本)9781424407644

The power amplifier (PA) used in modern wireless system needs to perform better from point of view linearity and efficiency. A crucial perquisite for the design of PA is the availability of suitable device models. Artificial neural networks (ANN) recently gained attention as a fast and flexible way to develop HBT device model when compared to the conventional modeling approach based on empirical equations and can demonstrate better accuracy. The framework for this ANN based model is a common-emitter large-signal equivalent circuit model, which has been implemented in Agilent Advance design System (ADS) simulation environment. An excellent agreement between modeled and bias dependent DC and S -parameters and harmonic power in non-linear mode of operation was obtained. Using developed ANN based HBT model PA design was carried out. At collector voltage V-c of 34V, the power amplifier shows an excellent linearity (first ACPR <-42.2dBc) up to 28dBm of rated output power for CDMA applications. At the rated output power level, PAE was found to be more than 35%. All the CDMA wireless PA specifications like gain, power-added efficiency (PAE) and adjacent channel power rejection (ACPR) are achieved over nominal and extreme temperature conditions.

关键词： neural network power amplifier GaAsHBT large signal modeling equivalent circuit model

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