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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是951-960 订阅

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Checking Properties of PLL designs using Run-time Verification

Checking Properties of PLL Designs using Run-time Verificati...

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2007 International conference on microelectronics (ICM'07)

作者： Zhi Jie Dong Mohamed H. Zaki Ghiath Al Sammane Sofiene Tahar Guy Bois ECE Department Concordia University Canada École Polytechnique de Montreal Génie Informatique Montreal QUE Canada

Due to challenges associated with its verification process, analog and mixed signal designs like PLLs require a considerable portion of the total design time. In this paper, we propose a run-time verification approach for PLL designs. The essence of this approach is to monitor properties of interest by timed automata integrated within an automatic stimulus generation framework. The objective is to guide simulation by an appropriate simulation trace in order to quickly detect errors by the property monitor.

关键词： Phase locked loops Runtime Computerized monitoring Automata Mathematical model Computational modeling Signal design Logic Signal processing Testing

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Statistical methodologies for integrated circuits design

Statistical methodologies for integrated circuits design

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Andrea Padovani Andrea Chimenton Piero Olivo Paolo Fantini Loris Vendrame Serena Mennillo Dipartimento di Ingegneria Università di Ferrara Ferrara Italy STMicroelectronics Monza Italy

The continuous scaling of physical dimensions has strongly increased circuit performance variability and the traditional corner-case methodology is becoming unreliable. As a consequence, there is an urgent need for new and more accurate statistical models. In this scenario, the purpose of this paper is twofold: 1) to give the reader the basic concepts of statistical modeling, and 2) to discuss a viable statistical approach that could be adopted into a traditional IC design flow for the next technology generations.

关键词： Statistical analysis Integrated circuit synthesis Integrated circuit modeling Circuit optimization Manufacturing processes Circuit simulation Uncertainty Robustness Circuit testing Integrated circuit noise

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modeling and design of a Novel Integrated Band-Pass Sigma-Delta Modulator

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12th IFIP International conference on Personal Wireless Communications, PWC 2007

作者： Fujcik, Lukas Haze, Jiri Vrba, Radimir Forejtek, Jiri Zavoral, Pavel Prokop, Roman Michaeli, Linus Dept. of Microelectronics FEEC Brno University of Technology Brno Czech Republic Dept. of Electronis and Multimedia Communications FEI Technical University of Kosice Kosice Slovakia

ISBN: (纸本)9780387741581

The paper deals with a bandpass sigma-delta modulator (BP SDM), which is used for conversion of signal from capacitive pressure sensor. This approach is absolutely new and unique, because this kind of modulator is utilized only for wireless and video applications. The main advantage of BP SDM is due to its defined band. That is why it is resistant against offsets of its sub-circuits. Another important advantage is low power consumption, since the BP SDM digitizes only narrow band instead of whole Nyquist band with similar dynamic range. The paper shows basic ideas of this approach and simulation results. The main stages are implemented in switched-capacitor (SC) technique. The paper presents two possibilities how to design PLL block. The first one is conventional approach and the other one is with digital sigma-delta modulator as generator of input harmonic signal.

关键词： Phase locked loops

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Fostering the reuse and collaborative development of models in the AMS SoC design process

Fostering the reuse and collaborative development of models ...

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： Torsten Mahne Alain Vachoux Yusuf Leblebici Laboratoire de Systèmes Microélectroniques (LSM) EPFL/STI/IMM/LSM École Polytechnique Fédérale de Lausanne Lausanne Switzerland

Systems-on-chips (SoCs) integrate more and more heterogeneous components: analog/RF/digital circuits, sensors, actuators, software. For the design of these systems very different description formalisms, or models of computation (MoCs), and tools are used for the different subblocks and design stages, which often create interoperability problems. Additionally the verification of a complete SoC is difficult due to huge performance problems. The goal of this Ph.D. work is to develop an efficient modeling and simulation platform that supports the design of mixed-signal SoCs using component models written in different design languages and using different MoCs. One component of this work is the development of a Web-based platform for collecting behavioral models and supporting the design of analog and mixed-signal (AMS) SoCs. Its current state and an outlook on its further development is the focus of this paper.

关键词： Collaboration Process design Radio frequency Computational modeling Collaborative software Actuators World Wide Web Digital circuits Software design Pulp manufacturing

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High-speed multi-bit continuous-time bandpass delta-sigma modulator

High-speed multi-bit continuous-time bandpass delta-sigma mo...

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Ph.D. Research in microelectronics and Electronics (PRIME)

作者： A. Mariano D. Dallet Y. Deval J-B Begueret Integrated Circuits Design Team IMS Laboratory University of Bordeaux 1 France

A High-Speed Multi-Bit Bandpass Continuous- Time Delta-Sigma Modulator is presented in this paper. This modulator samples at high-IF signals, performing the direct conversion in the modern RF front-end receivers. In order to improve the design flexibility, an advanced design methodology is used. This methodology is very interesting for complex mixed-signal IC design, since it combines behavioral models and transistor level models in the same environment, reducing the simulation time.

关键词： Delta modulation design methodology Radio frequency Integrated circuit modeling Digital modulation Receivers Transistors design optimization Sampling methods Predictive models

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Multi-scale energy-based failure modeling of bond pad structures

Multi-scale energy-based failure modeling of bond pad struct...

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8th International conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in Micro-Electronics and Micro-Systems

作者： van der Sluis, O. van Silfhout, R. B. R. Engelen, R. A. B. van Driel, W. D. Zhang, G. Q. Philips Appl Technol High Tech Campus 7 NL-5656 AE Eindhoven Netherlands Delft Univ Technol Dept Precis & Microsyst Engn NL-2600 AA Delft Netherlands NXP Semicond IMO Innovat BY1055 NL-6534 AE Nijmegen Netherlands NXP Semicond NL-5656AE Nijmegen Netherlands

ISBN: (纸本)9781424411054

Thermo-mechanical reliability issues have been identified as major bottlenecks in the development of future microelectronic components. This is caused by the following technology and business trends: (1) increasing miniaturisation, (2) introduction of new materials, (3) shorter time-to-market, (4) increasing design complexity and decreasing design margins, (5) shortened development and qualification times, (5) gap between technology and fundamental knowledge development [22]. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [8]. However, bad mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back end structure when no appropriate development is performed [4]. The scope of this paper is on the development of numerical models that are able to predict the failure sensitivity of complex three-dimensional multi-layered structures while taking into account the details at the local scale of the microelectronic components by means of a multi-scale method. The damage sensitivity is calculated by means of an enhanced version of the previously introduced Area Release Energy (ARE) criterion. This enhancement results in an efficient and accurate prediction of the energy release rate (ERR) at a selected bimaterial interface in any location. Moreover, due to the two-scale approach, local details of the structure are readily taken into account. In order to evaluate the efficiency and accuracy of the proposed method, several two-dimensional and three-dimensional benchmarks will be simulated. The paper focusses on the enhanced ARE method, including several two- and three-dimensional benchmarks.

关键词： microelectronics

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A behavior-oriented simulation tool for design and optimization of sigma-delta ADCs

A behavior-oriented simulation tool for design and optimizat...

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International conference on ASIC

作者： Xin Zhang Dunshan Yu Shimin Sheng Institute of Microelectronics Peking University Beijing China

In this paper, a behavior-oriented simulation tool is proposed for the designing and optimizing of sigma-delta ADCs. We show how this kind of simulation tool can be used in a top-down design flow in the mixed-signal system design. The imperfections of the analog cells as integrators, comparator, and the CpAMPs are analyzed in detail, which guides the design towards high performance. Besides, the modeling, simulation, and design of a second-order sigma-delta modulator are presented as a proof for the effectiveness of the simulation tool. A peak SNR of 91.5 dB, a 15 bit resolution, and a 57 m W power dissipation are obtained through HSPICE simulation. Currently chip is in the fabrication phase.

关键词： design optimization Delta-sigma modulation Signal design Analytical models Digital modulation Circuits Performance analysis Power dissipation Fabrication Phase modulation

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design a 4GHz PLL for wireless receiver

Design a 4GHz PLL for wireless receiver

引用

International conference on ASIC

作者： Yunfeng Wang Qing Ye Jiahan Man Jun Fan Tianchun Ye Institute of Microelectronics Chinese Academy and Sciences Beijing China

:This paper presents the design of a 4 GHz PLL used in wireless receiver. The Verilog-A models are used in behavioral level simulation and in post-layout simulation. The design is based on SMIC 0.18 um 1P6M CMOS RF process. The settling time is 19us and the reference spur is 42.2 dB, the phase noise of VCO is -115 dBc/Hz@lMHz, the power dissipation of the PLL is 36 mW.

关键词： Phase locked loops Semiconductor device modeling Circuit simulation Phase frequency detector Low pass filters Hardware design languages Charge pumps Transfer functions Voltage-controlled oscillators Clocks

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A Behavior-Oriented simulation Tool for design and Optimization of Sigma-Delta ADCs

A Behavior-Oriented Simulation Tool for Design and Optimizat...

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2007 7th International conference on ASIC Electronic Version(ASICON 2007)

作者： Xin Zhang Dunshan Yu Shimin Sheng Institute of microelectronics,Peking University,Beijing 100871,China

In this paper,a behavior-oriented simulation tool is proposed for the designing and optimizing of Sigma-Delta *** show how this kind of simulation tool can be used in a top-down design flow in the mixed-signal system *** imperfections of the analog cells as integrators,comparator,and the OpAMPs are analyzed in detail,which guides the design towards high ***,the modeling,simulation,and design of a second-order sigma-delta modulator are presented as a proof for the effectiveness of the simulation tool.A peak SNR of 91.5dB,a 15bit resolution,and a 57mW power dissipation are obtained through HSPICE *** chip is in the fabrication phase.

关键词： simulation ADC A Behavior-Oriented simulation Tool for design and Optimization of Sigma-Delta ADCs Delta

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Electronic System Level Models for Functional Verification of System-on-Chip

Electronic System Level Models for Functional Verification o...

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International conference on CAD Systems in microelectronics (CADSM)

作者： Alexander Adamov Karina Mostovaya Inna Syzonenko Alexey Melnik DAD Department Kharkov National University of Radioelectronics Kharkiv Ukraine

Modern verification environments based on object-oriented methodology is a system-level solution that manages the process and data for a particular system-on-chip model. These systems give an ability to integrate smaller blocks of design into larger blocks, which may eventually be integrated into a system. That is reason for performing designing and functional verification at a system level, which allow teams to rapidly create large system-on-chip designs by integrating premade blocks. Integrated verification systems used to store and manage huge amount of simulation data. However, when the amount of data is large, it is difficult to analyze and extract information from it. This data can be archived for later use or it can be mined to look for different kind of violations or to get statistical information about the specified design. The paper describes the system-level verification environment for a functional verification system-on-chip models. With the help of novel approach we can easily use opportunities, that system-level modeling gives us, such as: early software validation of the system, performance analysis of the system, transaction-level verification of the project, architectural analysis of system-on-chip (SoC) , power analysis of a chip, searching hardware/software tradeoffs.

关键词： System-on-a-chip Object oriented modeling Power system modeling Hardware Data mining Process design Performance analysis Software prototyping Virtual prototyping Software performance

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