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检索条件"任意字段=Conference on Design, Modeling, and Simulation in Microelectronics"

共 1419 条记录，以下是971-980 订阅

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Behavioral Modelling of Vibrating Piezoelectric Micro-Gyro Sensor and Detection Electronics

Behavioral Modelling of Vibrating Piezoelectric Micro-Gyro S...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： S. Megherbi R. Levy F. Parrain H. Mathias O. Le Traon D. Janiaud J. P. Gilles Institut d'Electronique Fondamentale UMR 8622 University of Paris-Sud 11 Orsay France Onera/DMPH Chatillon France

This paper describes the development of a model of vibrating piezoelectric micro-gyro sensor using analog hardware description. Our procedure implies several steps with emphasis in model complexity reduction and identification of critical parameters. The proposed macro-model permits multi-physic simulations including mechanical, piezo-electric and electrical analytic descriptions and allows a top-down development approach. As a tool for coding our descriptions, we use analog hardware description language (Verilog-A). For achieving the behavioural computation results, CADENCE simulation environment was used. The critical parameters of the gyro are then studied: the output noise, the output bias and scale factor stability over temperature.

关键词： Vibrations Mechanical sensors Hardware design languages Resonance Sensor phenomena and characterization Computational modeling Temperature Force sensors Electrodes Equations

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Computational Methods and High Speed Imaging Methodologies for Transient-Shock Reliability of Electronics

Computational Methods and High Speed Imaging Methodologies f...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Pradeep Lall Department of Mechanical Engineering and Center for Advanced Vehicle Electronics Aubum University Auburn AL USA

Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the state- of-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. In this paper, the modeling approaches and high-speed experimental techniques for first-level solder interconnects in shock and drop of electronics assemblies have been discussed. The shock and vibration reliability prediction of electronic interconnects involves multiple scales from macro-scale transient-dynamics of electronic assembly to micro-structural damage history of interconnects. Previous modeling approaches include, solid-to-solid sub-modeling using a half test PCB board, shell-to-solid sub-modeling technique using a quarter- symmetry model. Inclusion of model symmetry in state- of-art models saves computational time, but targets primarily symmetric mode shapes. Explicit modeling approaches has been presented, which enable prediction of both symmetric and anti-symmetric modes, which may dominate an actual drop-event. Approaches presented include, smeared property models, Timoshenko-beam element models, explicit sub-models, and continuum-shell models. A failure-envelope approach based on wavelet transforms and damage proxies has been discussed to model drop and shock survivability of electronic packaging. Data on damage progression under transient- shock and vibration in both 95.5 Sn 4.0 Ag 0.5 Cu and 63 Sn 37 Pb ball-grid arrays has been presented. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a user-specified confi

关键词： Electric shock Strain measurement Testing Assembly Solid modeling Predictive models Tin Electrical resistance measurement Displacement measurement Accelerometers

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design Optimization of a 35nm Independently-Double-Gated Flexfet SOI Transistor

Design Optimization of a 35nm Independently-Double-Gated Fle...

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IEEE SOI-3D-Subthreshold microelectronics Technology Unified conference (S3S)

作者： R.S. Chintala S. Vootkuri S. A. Parke Tennessee Technological University Cookeville TN USA

Flexfet is a new SOI IDG-CMOS technology with a damascene metal top gate and an implanted JFET bottom gate that are self-aligned in a gate trench. The independent top and bottom gates are contacted at opposite sides of the channel by a local interconnect that is embedded in the isolation region between devices. A simple analytical dynamic threshold voltage model is developed and verified by extensive device simulation. Optimization of the topgate oxide thickness, silicon thickness, and gate work functions for a 35 nm long NMOSFET is achieved by device simulation. Ideal 1.0V/V dynamic threshold control of this device is achieved.

关键词： design optimization Threshold voltage Silicon Voltage control MOSFET circuits Semiconductor device modeling Thickness control conference proceedings Analytical models Isolation technology

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A compressed BiCGStab algorithm for power and ground network analysis

A compressed BiCGStab algorithm for power and ground network...

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International conference on ASIC

作者： Haohang Su Yimen Zhang Yuming Zhang Jincai Man Microelectronics School Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices Xidian University Xi'an China

An effective method is proposed based on compressed BiCGStab approaches to perform static and transient simulations for large-scale power and ground network circuits and a good result is obtained. Extensive experimental results on large-scale power and ground network show that presented method is over two orders faster than HSPICE in transient simulations. Furthermore, our algorithm reduces over 95% of memory usage than HSPICE and 75% of memory usage than ICCG while the accuracy is not compromised.

关键词： Algorithm design and analysis Voltage Equations Transient analysis Circuit simulation Power system modeling Computational modeling Large-scale systems Linear systems Power grids

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Generating VHDL-AMS Models of Digital-to-Analogue Converters From MATLAB®/SIMULINK®

Generating VHDL-AMS Models of Digital-to-Analogue Converters...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Alexandre Cesar Rodrigues da Silva Ian Grout Jeffrey Ryan Thomas O'Shea Department of Electrical Engineering UNESP-School of Engineering Ilha Solteira Sao Paulo Brazil Department of Electrical Engineering School of Engineering Ilha Solteira SP Brazil Department of Electronic and Computer Engineering University of Limerick Co. Limerick Republic of Ireland

Today, the trend within the electronics industry is for the use of rapid and advanced simulation methodologies in association with synthesis toolsets. This paper presents an approach developed to support mixed-signal circuit design and analysis. The methodology proposed shows a novel approach to the problem of developing behavioral model descriptions of mixed-signal circuit topologies, by construction of a set of subsystems, that supports the automated mapping of MATLAB reg /SIMULINK reg models to structural VHDL-AMS descriptions. The tool developed, named MS2SV, reads a SIMULINK reg model file and translates it to a structural VHDL-AMS code. It also creates the file structure required to simulate the translated model in the SystemVisiontrade. To validate the methodology and the developed program, the DAC08, AD7524 and AD5450 data converters were studied and initially modelled in MATLAB reg /SIMULINK reg . The VHDL-AMS code generated automatically by MS2SV, (MATLAB reg /SIMULINK reg to SystemVisiontrade), was then simulated in the SystemVisiontrade. The simulation results show that the proposed approach, which is based on VHDL-AMS descriptions of the original model library elements, allows for the behavioural level simulation of complex mixed-signal circuits.

关键词： Mathematical model Computer languages Circuit simulation Circuit synthesis design methodology Electronic design automation and methodology Industrial electronics Electronics industry Computational modeling Computer simulation

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A Study on self-timed asynchronous subthreshold logic

A Study on self-timed asynchronous subthreshold logic

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IEEE International conference on Computer design: VLSI in Computers and Processors, (ICCD)

作者： Niklas Lotze Maurits Ortmanns Yiannos Manoli Chair of Microelectronics Department of Microsystems Engineering University of Freiburg Freiburg im Breisgau Germany

This paper investigates self-timed asynchronous design techniques for subthreshold digital circuits. In this voltage range extremely high voltage-dependent delay uncertainties arise which make the use of synchronous circuits rather inefficient or their reliability doubtful. Delay-line controlled circuits face these difficulties with self-timed operation with the disadvantage of necessary timing margins for proper operation. In this paper we discuss these necessary timing overheads and present our approach to their analysis and reduction to a minimum value by the use of circuit techniques allowing completion detection. Transistor-level simulation results for an entirely delay-adaptable counter under variable supply down to 200 mV are presented. Additionally an analytical comparison and simulation of timing and energy consumption of more complex subthreshold asynchronous circuits is shown. The outcome is that a combination of delay-line based circuits with circuits using completion detection is promising for applications where the supply voltages are at extremely low levels.

关键词： Timing Delay Integrated circuit modeling Logic gates Delay lines Radiation detectors Safety

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modeling Alpha and Neutron Induced Soft Errors in Static Random Access Memories

Modeling Alpha and Neutron Induced Soft Errors in Static Ran...

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IEEE International conference on Integrated Circuit design and Technology (ICICDT)

作者： Kevin M. Warren Jeffrey D. Wilkinson Scott Morrison Robert A. Weller Mark E. Porter Brian D. Sierawski Robert A. Reed Marcus H. Mendenhall Ron D. Schrimpf Lloyd W. Massengill Institute for Space and Defense Electronics Nashville TN USA Medtronic CRDM Device Technology Minneapolis MN USA Electrical Engineering and Computer Science Department Vanderbilt University Nashville TN USA Medtronic Microelectronics Center Inc. Tempe AZ USA Free Electron Laser Center Vanderbilt University Nashville TN USA

Experimental thermal neutron and alpha soft error test results of a 4 Mbit SRAM fabricated on a 0.25 mum process are evaluated using Vanderbilt University's RADSAFE toolkit. The capabilities of the radiation transport code are demonstrated by accurately reproducing experimental results and predicting operational soft error rates for the memory.

关键词： Neutrons SRAM chips Semiconductor materials Circuit simulation Random access memory Error analysis USA Councils Radioactive materials Solid modeling Testing

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The design and optimization of gain-boosted OTA for high speed and high accuracy sample and hold amplifier

The design and optimization of gain-boosted OTA for high spe...

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7th International conference on ASIC (ASICON 2007), vol.2

作者： Liu Zao Cheng Jun Zhang Hong Chen Guican Department of Microelectronics Xi''an Jiaotong University China

In this paper, a systematical method of designing a high gain and high speed gain-boosted operational transconductance amplifier (gain-boosted OTA) is introduced through mathematically modeling its small signal equivalent circuits in a simple and useful way. By applying root locus techniques to the conclusion of this model, two different ways of optimizing the performance of the gain-boosted OTA are proposed. To verifying the design methods, SMIC 0.18μm CMOS technology and 1.8V supply voltage are applied to implement this high gain and high speed OTA. The simulation results show that the output of the sample and hold amplifier (SHA) using these OTAs has minimized ring and overshoot, achieving SNR over 100dB and SNDR over 70dB with 39.9MHZ sinusoid input, and at the higher frequency region, with input signal of 79.9MHZ, the SNR over 81dB and SNDR over 63dB can be achieved.

关键词： design optimization design methodology Semiconductor device modeling CMOS technology Signal design Transconductance Operational amplifiers Mathematical model Equivalent circuits Voltage

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A Study of Failure Mechanism and Reliability Assessment for the Panel Level Package (PLP) Technology

A Study of Failure Mechanism and Reliability Assessment for ...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Ming-Chih Yew Hsiu-Ping Wei Ching-Shun Huang Dyi-Chung Hu Wen-Kung Yang Kou-Ning Chiang Advanced Packaging Research Center Advanced Microsystem Packaging and Nano-Mechanics Research Laboratory Department of Power Mech. Engineering National Tsing Hua University Hsinchu Taiwan Advanced Chip Engineering Technology Inc. Hsinchu Taiwan

In this study, a new packaging technology, chip-on-metal (COM) panel level package (PLP), is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. During the manufacturing process, the filler polymer material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler polymer and the chip surface, and the pitch of the chip side is fanned-out. In our previous research, it was shown that the thermo- mechanical behavior of the COM PLP is different from the convention wafer level package (WLP) because of the designed packaging structure. In this study, the reliability characteristic of the proposed PLP technology is investigated and discussed through finite element analysis (FEA). The macro-micro modeling methodology is applied to assist in the reliability assessment of the trace/pad junction. From the simulated results, the mean cycle to failure of the solder joints can be highly increased by the proposed packaging technology. However, the new failure mode may happen at the metallic redistribution layer. The reliability of the signal trace in the COM PLP can be improved by an experienced design of the trace layout. Thus, the proposed PLP technology will have a high potential for various applications in the near future.

关键词： Failure analysis Packaging Polymers Wafer scale integration Assembly Manufacturing processes Finite element methods Semiconductor device modeling Soldering Signal design

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Wideband 0.18μm CMOS VCO using active inductor with negative resistance

Wideband 0.18μm CMOS VCO using active inductor with negativ...

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European conference on Circuit Theory and design, ECCTD

作者： Grzegorz Szczepkowski Gerard Baldwin Ronan Farrell Center for Telecommunications Value Chain Research Institute of Microelectronics and Wireless Systems Co Kildare Maynooth National University of Ireland Ireland

This paper presents a wideband voltage controlled oscillator topology based on an active inductor generating negative resistance. The proposed architecture covers a frequency band between 1.325 GHz - 2.15 GHz with average in-band phase noise of -86 dBc/Hz at 1 MHz offset from the carrier frequency. Power consumption of the oscillator core is 28 mW from a 1.8 V supply. The circuit has been simulated in Eldo RF (design Architect IC, Mentor Graphics) using UMC 0.18 mum 1P6M Salicide RF CMOS model libraries.

关键词： Wideband Voltage-controlled oscillators Active inductors Radio frequency Integrated circuit modeling Topology Phase noise Energy consumption Circuit simulation CMOS integrated circuits

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