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conference on design and architectures for signal and image processing (dasip)

作者： Meinl, Frank Kunert, Martin Blume, Holger Robert Bosch GmbH Adv Engn Sensor Syst Leonberg Germany Leibniz Univ Hannover Inst Mikroelekt Syst Hannover Germany

ISBN: (纸本)9791092279153

Direction of arrival (DOA) estimation is an important array signal processing technique, used by various applications such as radar, sonar or wireless communication. Most of the known DOA algorithms suffer from a significant performance reduction and even fail completely under difficult conditions, like small antenna aperture size, correlated signals or a small number of snapshots. Maximum-Likelihood (ML) methods have been investigated thoroughly and are known to still work even in such difficult scenarios. Though, the major drawback of ML methods is their computational cost, especially in the case of large MIMO (multiple-input multiple-output) configurations. This work presents a novel hardware accelerator architecture, which is able to compute the exact ML estimation in the case of one or two targets. It is shown, that the computational demanding vector product can be implemented with the help of CORDIC units, which help to save a considerable amount of hardware resources. Furthermore, the result of the single target estimator can be reused to efficiently compute the estimates in the two-target case. Finally, the performance of the architecture is evaluated by a FPGA implementation which is able to process more than 20 000 detections from 16 channels with 256 steering vectors in real-time (25 Hz).

关键词： Automotive radar driver assistance direction of arrival maximum-likelihood estimation radar signal processing CORDIC hardware accelerator FPGA

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Special issue: design and architectures for real-time signal and image processing

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JOURNAL OF REAL-TIME image processing 2018年第1期15卷 1-2页

作者： Huebner, Michael Ruhr Univ Bochum ESIT Bochum Germany

The conference on design and architectures for signal and image processing-dasip addresses the development of complex applications involving signal, image and control processing based on a new approach called Algorithm–Architecture–Matching, which aims to leverage the design flow by a simultaneous study of both algorithmic and architectural issues, taking into account multiple design constraints, as well as algorithm and architecture optimizations. Embedded Systems and Cyber-physical Systems (CPS), especially in relation to image and signal processing, are a big step forward from the basic data-gathering networks, and they have been called to be the fourth industrial revolution. [...]the important contribution of CPS is its integration and connection of the hardware elements, e.g., sensors, actuators and computing units, with the software functionalities, e.g., automated routines and supervisor software, to perform energy efficiency and simultaneously keeping safety requirements. In the area of optimization, the paper “Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors” [11] and “A linked list run-length-based single-pass connected component analysis for real-time embedded hardware” [12] are completing this excellent special issue.

关键词： ARCHITECTURE image processing Building construction time signal signals

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Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study

Dataflow program analysis and refactoring techniques for des...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Ab Rahman, Ab Al-Hadi Casale Brunet, Simone Alberti, Claudio Mattavelli, Marco SCI-STI-MM École Polytechnique Fédérale de Lausanne Switzerland

ISBN: (纸本)9791092279016

This paper presents a methodology to perform design space exploration of complex signal processing systems implemented using the CAL dataflow language. In the course of space exploration, critical path in dataflow programs is first presented, and then analyzed using a new strategy for computational load reduction. These techniques, together with detecting design bottlenecks, point to the most efficient optimization directions in a complex network. Following these analysis, several new refactoring techniques are introduced and applied on the dataflow program in order to obtain feasible design points in the exploration space. For a MPEG-4 AVC/H.264 decoder software and hardware implementation, the multi-dimensional space can be explored effectively for throughput, resource, and frequency, with real-time decoding range from QCIF to HD resolutions.

关键词： Space research

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Fuzzy Logic modeling for Objective image Quality Assessment

Fuzzy Logic modeling for Objective Image Quality Assessment

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conference on design and architectures for signal and image processing (dasip)

作者： Tchendjou, Ghislain Takam Alhakim, Rshdee Simeu, Emmanuel Univ Grenoble Alpes TIMA F-38000 Grenoble France CNRS TIMA F-38000 Grenoble France

ISBN: (纸本)9791092279153

This paper presents a novel methodology of objective image quality assessment (IQA) based on Fuzzy Logic (FL) method. The main purpose is to automatically assess the quality of image in agreement with human visual perception. The used attributes (quality metrics) and evaluation criteria (human rating mean opinion score MOS) are extracted from image quality database TID2013. The fuzzy model design starts by selecting the most independent attributes, by applying Pearson's correlation approach and seeking the most correlated metrics with the corresponding MOS. Then, Adaptive Neuro-Fuzzy Inference System (ANFIS) is applied in order to construct an objective fuzzy model able to efficiently predict the image quality correlated with the subjective MOS. In this paper, different fuzzy models are produced by modifying certain ANFIS configurations. After that, we select the appropriate ANFIS model that provides high prediction accuracy and stability with taking into account its implementation complexity. The overall architecture of the selected FL model consists of four input metrics, two bell-shaped membership functions associated to each input metric, two fuzzy if-then rules, two linear combination equations and one output which gives the image adequate quality score. Finally the performance of the proposed fuzzy model is compared with other IQA models produced by different machine learning methods, the simulation results demonstrate that the fuzzy logic model has a high stable behavior with the best agreement with human visual perception.

关键词： image Quality Assessment Machine Learning Fuzzy Logic Fuzzy Inference System ANFIS

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Hardware-software implementation of vehicle detection and counting using virtual detection lines 8

Hardware-software implementation of vehicle detection and co...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Kryjak, Tomasz Komorkiewicz, Mateusz Gorgon, Marek AGH Univ Sci & Technol Fac Elect Engn Automat Comp Sci & Biomed Engn Dept Automat & Biomed Engn Al Mickiewicza 30 PL-30059 Krakow Poland

ISBN: (纸本)9791092279061

In this paper a hardware-software system for vehicle detection and counting at intersections is presented. It has been implemented and evaluated on the heterogeneous Zynq platform. The vehicle detection is based on the concept of virtual detection lines (VDL). Differences in colour, horizontal edges and Census transform results between areas around the VDL for two consecutive frames are used to disclosure particular vehicles. This part of the system is designed in hardware description language and implemented in the reconfigurable resources of the Zynq platform. Information about the vehicle presence, along with the time-spatial image obtained at the VDL are transmitted and processed on the ARM core integrated in the Zynq device. This allows to perform further analysis and eliminate false or multiple detections. The solution has been evaluated on several video sequences recorded in various conditions: sunny day (the occurrence of deep shadows), cloudy day, rain and night-time. The system could be an important element of an intelligent transportation system (ITS) i. e. applied in a smart camera.

关键词： Vehicle detection Smart cameras Intelligent transportation systems Video sequences Hardware design languages software implementation Virtual Intersection False

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Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case

Evaluation of analog and digital signal processing on PSoC a...

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conference on design and architectures for signal & image processing

作者： Werner, Stephan Stiehle, Bernhard Becker, Juergen Karlsruhe Inst Technol Inst Informat Proc Technol ITIV Karlsruhe Germany

ISBN: (纸本)9791092279115

One trend for signal processing hardware is the increasing integration of different functionalities in one mixed-signal chip. But the additional integration of analog components on one chip with digital components and a micro-processor like in the Programmable System on Chip (PSoC) from Cypress is accompanied with the extension of the design space and the need to explore it by evaluating different implementations with the same functionality to find a good trade-off between analog and digital signal processing. This paper evaluates different implementations of the discrete cosine transform (DCT) with different analog-digital partitioning. Therefore the DCT is integrated as software controlled analog circuit based on the switched capacitors and operational amplifiers available in the analog subsystem of the PSoC architecture. The presented analog DCT implementation scales linear and the number of simultaneously computable spectral signal components is only limited by the available on-chip resources on the currently used PSoC5LP. To evaluate the analog implementation, the DCT is also implemented as software executed on the ARM Cortex-M3 integrated in the PSoC5LP. The comparison of both solutions shows that the analog hardware available on the PSoC architecture can be used to directly process analog sensor signals with only minor additional off-chip components with a CPU load of about 8% caused by the software controlling the analog subsystem.

关键词： PSoC DCT discrete cosine transform analog design switched capacitors analog-digital design space exploration mixed signal processing

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Synthesis of arithmetic expressions for the fixed-point arithmetic: The Sardana approach

Synthesis of arithmetic expressions for the fixed-point arit...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Ioualalen, Arnault Martel, Matthieu Univ. Perpignan Via Domitia Digits Architectures et Logiciels Informatiques F-66860 Perpignan France Univ. Montpellier II Laboratoire d'Informatique Robotique et de Microelectronique de Montpellier UMR 5506 F-34095 Montpellier France CNRS Laboratoire d'Informatique Robotique et de Microelectronique de Montpellier UMR 5506 F-34095 Montpellier France

ISBN: (纸本)9782953998726

Sardana is a tool which optimizes the arithmetic expressions present in source codes. The optimization is done by synthesizing automatically new mathematically equal expressions, given ranges of values for the variables. In previous work, Sardana has been used to optimize the numerical accuracy of floating-point expressions, by minimizing the worst roundoff error on the result of the evaluation. In this article, we show how our tool can be used to synthesize arithmetic expressions optimized for the fixed-point arithmetic. In this context, Sardana minimizes the number of bits required to represent without overflow the integer parts of the fixed-point numbers possibly occurring at any stage of the evaluation of an expression. We present experimental results showing how our tool optimizes the implementation of digital filters commonly used in image processing. © 2012 ECSI.

关键词： Fixed point arithmetic

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Exploration platform of embedded SIMD architecture for autonomous retinas

Exploration platform of embedded SIMD architecture for auton...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Chevobbe, Stéphane Pajaniradja, Suresh Letellier, Laurent CEA LIST Embedded Computing Laboratory Gif-sur-Yvette F-91191 France

ISBN: (纸本)9781424487356

An integrated smart camera is a single chip composed of a sensor tightly coupled with one or more processing elements. The image processing applications that are mapped on such systems can require processing power in the range of supercomputer. To face the increasing application needs we propose in this paper a SIMD based processor optimized for the low and intermediate level of image processing. The architecture is composed of several SIMD cluster. Each cluster includes a configurable number of 2-Way PE (processing Element) ranging from 32 to 256 running at 200 MHz. These cluster configurations provide between 12 to 102 GOPS. © 2010 IEEE.

关键词： image processing

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design and analysis of an FPGA based encoder SoC for locally stationary image source

Design and analysis of an FPGA based encoder SoC for locally...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Bai, Yuhui Ahmed, Syed-Zahid Granado, Bertrand ETIS - ENSEA - Université Cergy Pontoise - CNRS Cergy France LIP6 - Université Pierre et Marie Curie - CNRS Paris France

ISBN: (纸本)9791092279016

Hierarchical Enumerative Coding (HENUC) is a lossless compression algorithm used in a wavelet based image encoder. By manipulating the wavelet coefficients into locally stationary sequences, HENUC is demonstrated to provide good compression efficiency according to our experimental results. We extended our previous work on FPGA encoder SoC, exploiting an innovative on-chip memory access manner in the bit-plane coding using dual port, as well as an address-based data traversal technique during the coding. Performance results are based on the Altera's 40nm Stratix IV EP4SGX230 FPGA, on a DE4 board from Terasic, where the optimized dual port HENUC architecture is implemented in a Nios II processor based system on chip. We present the resource utilization and the execution time evaluations. We show that our implementation at 100MHz can provide around 10X speedup over 2.4GHz Intel Xeon 8-core CPU, which is about twice as faster as our previous result.

关键词： System-on-chip

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Smart sensor architectures for embedded biosignal analysis

Smart sensor architectures for embedded biosignal analysis

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Pfundt, Benjamin Reichenbach, Marc Eskofier, Björn Fey, Dietmar Department Computer Science Computer Architecture Friedrich-Alexander-University Erlangen-Nuremberg Germany Department Computer Science Pattern Recognition Lab Friedrich-Alexander-University Erlangen-Nuremberg Germany

ISBN: (纸本)9791092279016

In many sports and medical applications small and wearable sensors are used that capture motion and physiological signals. Yet, commonly such sensor are only capable of acquiring raw data, which is afterwards transmitted to a smartphone or other mobile computing device where processing and classification is carried out. This results in limited usability because another device has to be worn. Moreover, high power consumption due to continuous transmission is a main disadvantage. Therefore, we propose a smart sensor approach that can alleviate these problems by carrying out the processing on the sensor itself. To house the processing schemes in the sensor node we developed a new computer architecture utilizing an FPGA and an ASIC. To show the benefits of the in-sensor processing, we chose two representative biosensor applications: a movement and fall detection system for the elderly and a swimming style recognition system for professional athletes. Compared to conventional approaches the same classification rate can be achieved while saving space, power, weight and setup costs.

关键词： Field programmable gate arrays (FPGA)

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