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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是101-110 订阅

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Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform

Hyperspectral image classification using a parallel implemen...

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conference on design and architectures for signal and image processing (dasip)

作者： Madronal, D. Lazcano, R. Fabelo, H. Ortega, S. Callico, G. M. Juarez, E. Sanz, C. Tech Univ Madrid UPM Ctr Software Technol & Multimedia Syst CITSEM Madrid Spain ULPGC Res Inst Appl Microelect IUMA Las Palmas Gran Canaria Spain

ISBN: (纸本)9791092279153

In this paper, a study of the parallel exploitation of a Support Vector Machine (SVM) classifier with a linear kernel running on a Massively Parallel Processor Array platform is exposed. This system joins 256 cores working in parallel and grouped in 16 different clusters. The main objective of the research has been to develop an optimal implementation of the SVM classifier on a MPPA platform whilst the architectural bottlenecks of the hyperspectral image classifier are analyzed. Experimenting with medical images, the parallelization of the SVM classification has been conducted using three strategies: i) single- and multi-core processing, ii) single- and multi-cluster analysis and iii) single- and double-buffer execution. As a result, an average core processing speedup of 11.8 has been achieved when parallelizing the SVM classification process in a single cluster. On the contrary, since data communication accounts for 34.7% of the total execution time in the sequential case, the total speedup is upper-bounded to 2.9. Using a double-buffer methodology, a total speedup of 2.84 has been achieved on a single cluster. At last, the feasibility of a portable version of a linear SVM has been demonstrated.

关键词： Support Vector Machine Hyperspectral Imaging Massively Parallel processing Real-time processing Energy consumption awareness

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FPGA-based detection of QRS complexes in ECG signal

FPGA-based detection of QRS complexes in ECG signal

引用

conference on design and architectures for signal and image processing, dasip 2015

作者： Hassen, Amina El Histace, Aymeric Terosiet, Mehdi Romain, Olivier ETIS Lab ENSEA University of Cergy-Pontoise 6 avenue du Ponceau Cergy95014 France

ISBN: (纸本)9791092279108

This paper presents an FPGA-based algorithm for automatic detection of QRS complexes in ECG signals. The proposed algorithm is divided into 3 blocks: Filtering, Contrast Enhancement, and finally a Detection block based on time and amplitude thresholding of the enhanced data. The entire detection scheme was developed in accordance with embedding constraints. For validation, the method was tested on the MIT/BIH arrhythmia database containing 48 records of 30-minutes ECG. The FPGA-based algorithm correctly detects 95,35 percent of the QRS complexes, with a very limited ratio of false detection (only 8%). These results are in accordance with the most recent state-of-The-Art off-line algorithms on the same database, and improves significantly FPGA-based ones that were tested on a limited number of ECG extracted from the MIT/BIH set of data. © 2015 IEEE.

关键词： Electrocardiograms

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design under constraints of availability and energy for sensor node in wireless sensor network

Design under constraints of availability and energy for sens...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Hoang, Van-Trinh Julien, Nathalie Berruet, Pascal Lab-STICC/University of South-Brittany Research Center BP 92116 56321 Lorient France

ISBN: (纸本)9782953998726

Wireless Sensor Network (WSN) technology has been getting a lot of attention in recent years due to its low-cost, portability, easy deployment, self-organisation, and reconfigurability. Two main challenges faced by designers are availability and power/energy management for WSN. This paper presents a design for a wireless sensor node, which provides automated reconfiguration for both availability and energy-efficient use. This design introduces an original device named Power and Availability Manager (PAM) combined with a FPGA. The first one is considered as the intelligent part for the best use of energy and fault-tolerance, while the other enhances the availability in case of hardware failure for a node. Simulation model of these solutions together is based on General Stochastic Petri Net (GSPN). The results indicate a gain of availability from 9% to 31% for sensor node over twelve years, from 9% to 46% for sensor cluster over eighteen years, from 11% to 45% for whole network over fifty years. Our approach also results in significant energy-saving : up to 61% by using DPM policy, and up to 62.5% by using DPM and DVFS policies over seven days. These results allow us to evaluate and to show a design of WSN node for increased availability as well as energy-saving by using our approach. © 2012 ECSI.

关键词： Energy efficiency

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TURNUS: an open-source design space exploration framework for dynamic stream programs 8

TURNUS: an open-source design space exploration framework fo...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Casale-Brunet, S. Wiszniewska, M. Bezati, E. Mattavelli, M. Janneck, J. W. Canale, M. Ecole Polytech Fed Lausanne SCI STI MM Multimedia Grp CH-1015 Lausanne Switzerland Lund Univ Dept Comp Sci S-22100 Lund Sweden Politecn Torino Dipartimento Automat & Informat Turin Italy

ISBN: (纸本)9791092279061

Although the research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support have not emerged so far. Therefore, the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high level of abstraction makes the quality of the resulting implementation strongly dependent on the experience or individual preferences of the designer. In this work we are presenting TURNUS, a unified dataflow design space exploration framework for heterogeneous parallel systems. This open source framework represents a decade of research on high-level modelling and simulation methods and tools for system level performance estimation and optimization. Last year we presented heuristic algorithms that were focused on the results of exploration in terms of algorithmic optimization, rapid performance estimation, application throughput, buffer size dimensioning and power optimization. This year we are presenting the novelties that have been introduced in TURNUS such as clock gating, pipelining optimization, kernel splitting algorithms, advanced partitioning algorithms and scheduling optimization based on model predictive control techniques.

关键词： co-exploration dataflow design space

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Task migration of DSP application specified with a DFG and implemented with the BSP computing model on a CPU-GPU cluster

Task migration of DSP application specified with a DFG and i...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Mansouri, Farouk Huet, Sylvain Fristot, Vincent Houzet, Dominique GIPSA-lab UMR 5216 CNRS/INPG/UJF/Universite Stendhal F-38402 Grenoble cedex France

ISBN: (纸本)9791092279016

Nowadays computer applications are becoming heavier and require, at the same time, real-time results. The Heterogeneous clusters with their computing power represent a good solution to this request. However, it is possible that during the execution, a computing element of the cluster becomes defaulting, needs maintenance, or that the load needs to be rebalanced... In this paper, we propose a migration strategy for relocating the execution of a task to another computing element. In particular, we are interested in remap nodes of Data Flow Graph (DFG), representing Digital signal processing (DSP) application, onto heterogeneous (CPU-GPU) clusters while keeping up the flow of data and minimizing the temporal perturbation. For our approach, we give a lower bound for the flow of data after the migration and, validate it by the real-time construction of visual saliency map from video input.

关键词： Digital signal processing

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architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology

Architectures and signal reconstruction methods for nanoseco...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Zlatanski, Martin Uhring, Wilfried Zint, Virginie Le Normand, Jean-Pierre Mathiot, Daniel Institut d'Électronique du Solide et des Systèmes 23 rue du Loess 67037 Strasbourg France

ISBN: (纸本)9781424487356

This paper presents the state of the art of the Integrated Streak Camera (ISC) architectures in standard CMOS technology. It focuses on some of the methods required for reconstructing the luminous events profile from the chip raw data. Two main ISC architectures are presented. The first adopts the traditional for the most silicon imagers pixel array configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable to the slit of a Conventional Streak Camera (CSC), coupled to an amplifier stage and an analog sampling and storage unit. For both architectures, depending on the on-chip processing of the photocharges, appropriate signal reconstruction techniques are required in order to restore the luminous signal shape. A novel single vector ISC front-end architecture with an asynchronous photodiode reset scheme is presented. Algorithms allowing the luminous event reconstruction are proposed and validated through simulations for all the ISCs considered. © 2010 IEEE.

关键词： signal reconstruction

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A wavelet-based demosaicking algorithm for embedded applications

A wavelet-based demosaicking algorithm for embedded applicat...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Courroux, Sébastien Guyetant, Stéphane Chevobbe, Stéphane Paindavoine, Michel CEA LIST Embedded Computing Laboratory Gif-sur-Yvette F-91191 France LEAD Laboratory Université de Bourgogne 21000 Dijon France

ISBN: (纸本)9781424487356

This paper presents an alternative to the spatial reconstruction of the sampled color filter array acquired through a digital image sensor. A demosaicking operation has to be applied to the raw image to recover the full-resolution color image. We present a low-complexity demosaicking algorithm processing in the wavelet domain. Produced images are available at the output of the algorithm either in the spatial representation or directly in the wavelet domain for high-level post processing in the latter domain. Results show that the computational complexity has been lowered by a factor of five compared to state of the art demosaicking algorithms. © 2010 IEEE.

关键词： image processing

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Real-time classification based on color and texture attributes on an FPGA-based architecture

Real-time classification based on color and texture attribut...

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conference on design and architectures for signal and image processing

作者： Ibarra-Manzano, Mario-Alberto Devy, Michel Boizard, Jean-Louis CNRS LAAS 7 avenue du Colonel Roche 31077 Toulouse France Université de Toulouse UPS LAAS Toulouse France

ISBN: (纸本)9781424487356

The design and the implementation of algorithms on FPGA-based architectures, is a complex task, above all for image processing. Many vision applications (video monitoring, obstacle detection from a vehicle) require real time performance. This paper analyzes only a classical function involved in these applications: pixel characterization by an attribute vector, and pixel classification as belonging or not to an interest class. Typical attributes are color and texture. Color is described by the chrominance given by the a and b coordinates in the CIE-Lab color space. Texture is only computed from the L* coordinate, describing the local intensity variations in a neighborhood of every pixel. AdaBoost has been selected in order to learn how to classify every pixel from its attribute vector. From a learning data base, it is learnt off line how to select and combine a given number of weak classifiers;then, the classifier parameters are loaded on an FPGA-based kit. This paper proposes different architectures and presents some results obtained from images acquired from a robot, in order to classify a pixel as Ground or Obstacle. © 2010 IEEE.

关键词： image texture

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A noise-agnostic self-adaptive image processing application based on evolvable hardware

A noise-agnostic self-adaptive image processing application ...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Mora, Javier Gallego, Ángel Otero, Andrés López, Blanca De La Torre, Eduardo Riesgo, Teresa Center of Industrial Electronics - CEI Universidad Politécnica de Madrid Spain

ISBN: (纸本)9791092279016

Evolvable Hardware (EH) is a technique that consists in the usage of reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). In this demo, a proof of concept is shown in which an EH-based filter is used to remove different types of noise from an image. This filter, together with all the needed control and a processor to run the EA, is fully implemented in an FPGA without needing any external control.

关键词： image processing

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Rakeness-based Compressed Sensing on Ultra-Low Power Multi-Core Biomedical Processors 8

Rakeness-based Compressed Sensing on Ultra-Low Power Multi-C...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Bortolotti, Daniele Mangia, Mauro Bartolini, Andrea Rovatti, Riccardo Setti, Gianluca Benini, Luca Univ Bologna DEI I-40126 Bologna Italy Swiss Fed Inst Technol Integrated Syst Lab Zurich Switzerland Univ Bologna ARCES I-40126 Bologna Italy Univ Ferrara ENDIF I-44100 Ferrara Italy

ISBN: (纸本)9791092279061

Technology scaling enables today the design of ultra-low cost wireless body sensor networks for wearable biomedical monitors. The typical behaviour of such systems consists of multi-channel input biosignals acquisition, data compression and final output transmission or storage. To achieve minimal energy operation and extend battery life, several aspects must be considered, ranging from signal processing to architectural optimizations. The recently proposed Rakeness-based Compressed Sensing (CS) paradigm deploys the localization of input signal energy to further increase compression without sensible RSNR degradation. Such output size reduction allows for trading off energy from the compression stage to the transmission or storage stage. In this paper we analyze such tradeoffs considering a multi-core DSP for input biosignal computation and different technologies for either transmission or local storage. The experimental results show the effectiveness of the Rakeness approach (on average approximate to 44% more efficient than the baseline) and assess the energy gains in a technological perspective.

关键词： Compressed sensing Energy sources Battery Life Size reduction tradeoffs system behavior PROCESSOR signal processing local storage

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