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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是121-130 订阅

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Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems

Hardware/software co-design of H.264/AVC encoders for multi-...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Dias, Tiago Roma, Nuno Sousa, Leonel INESC-ID Lisbon ISEL-PI Lisbon IST-TU Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal

ISBN: (纸本)9781424487356

This paper presents a multi-core H.264/AVC encoder suitable for implementations in small and medium complexity embedded systems. The proposed structure results from an efficient hardware/software co-design methodology, where the encoder software application is highly optimized and structured in a very modular and efficient manner, so as to allow its most complex and time consuming operations to be offloaded to dedicated hardware accelerators. The considered methodology adopts a simple and efficient core interconnection mechanism to easily allow the inclusion and the removal of such optimized processing cores. Experimental results obtained with the implementation in a Virtex4 FPGA of an H.264/AVC encoder using an ASIP IP core as a ME hardware accelerator have proven the advantages of this methodology. For the considered system, speedup factors greater than 15 were obtained with a very modest increase of the involved hardware resources. © 2010 IEEE.

关键词： Embedded systems

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Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation

Automated generation of an efficient MPEG-4 Reconfigurable V...

引用

2010 conference on design and architectures for signal and image processing, dasip2010

作者： Gu, Ruirui Piat, Jonathan Raulet, Mickael Janneck, Jorn W. Bhattacharyya, Shuvra S. Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States IETR Laboratory UMR CNRS 6164 Image and Remote Sensing Group 35043 Rennes Cedex France United Technologies Research Center Berkeley CA United States

ISBN: (纸本)9781424487356

This paper proposes an automatic design flow from user-friendly design to efficient implementation of video processing systems. This design flow starts with the use of coarse-grain dataflow representations based on the CAL language, which is a complete language for dataflow programming of embedded systems. Our approach integrates previously developed techniques for detecting synchronous dataflow (SDF) regions within larger CAL networks, and exploiting the static structure of such regions using analysis tools in The Dataflow interchange format Package (TDP). Using a new XML format that we have developed to exchange dataflow information between different dataflow tools, we explore systematic implementation of signal processing systems using CAL, SDF-like region detection, TDP-based static scheduling, and CAL-to-C (CAL2C) translation. Our approach, which is a novel integration of three complementary dataflow tools - the CAL parser, TDP, and CAL2C - is demonstrated on an MPEG Reconfigurable Video Coding (RVC) decoder. © 2010 IEEE.

关键词： Video signal processing

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Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform

Memory access analysis and optimization of a parallel H.264/...

引用

2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Brandenburg, Jens Stabernack, Benno Fraunhofer Institute for Telecommunications Image Processing Department Embedded Systems Group Einsteinufer 37 10587 Berlin Germany

ISBN: (纸本)9791092279016

HW/SW co-design and optimization requires an in-depth performance and bottleneck analysis of the developed system. Due to the increasing gap between the performance of the processing elements and the memory subsystem also memory access analysis plays an important role in this optimization task. This is especially the case for state of the art media signal processing applications, like video decoders, with their growing demand for high memory bandwidths and low latency data accesses. Optimizing memory partitioning, memory hierarchy, memory characteristics and allocation of data structures formulates a multidimensional HW/SW co-optimization problem with increasing complexity due to the trend towards embedded multi-core platforms. In order to aid the developer with these optimization tasks, performance and memory access analysis tools are needed. Nowadays there exist many different vendor specific debug and profiling tools for different processor architectures addressing different aspects of the overall co-optimization problem. Moving to heterogeneous platforms makes the combination and integration of the different profiling data a challenging task. Moreover it is important to combine the profiling results with information gathered from dedicated components, like interrupts, signals and/or synchronization events, representing the actual hardware platform. To overcome this issue we propose a flexible tracing and profiling methodology capable to trace all hardware aspects of the modeled simulation platform. Based on this methodology we developed a tool, which gives a comprehensive overview of the software tasks running on the various processing elements of the particular execution platform. Furthermore our tool provides detailed non-intrusive memory access and performance analyses based on SystemC virtual platform simulation models for heterogeneous embedded multi-core platforms. A demonstration of the tools capabilities is given by an exemplary analysis of a Scalable Vi

关键词： Video signal processing

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designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Designing dynamically reconfigurable SoCs: From UML MARTE mo...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Quadri, Imran Rafiq Meftali, Samy Dekeyser, Jean-Luc INRIA LILLE NORD EUROPE LIFL University of Lille Lille France

ISBN: (纸本)9781424487356

Due to continuous hardware/software evolution related to Systems-on-Chip (SoC) and the addition of features such as Partial Dynamic Reconfiguration, the complexity of SoC design and development has escalated exponentially. This has resulted in increased time to market and development costs. Without the usage of effective design tools and methodologies, large complex SoCs are becoming increasingly difficult to manage, resulting in a productivity gap. The design space, representing all technical decisions that need to be elaborated by the SoC design team is therefore, becoming immense and difficult to explore. Similarly, manipulation of these systems at low implementation levels such as Register Transfer Level (RTL) can be hindered by human interventions and the subsequent errors. This paper presents a novel design methodology that decreases the design complexity by raising the design abstraction levels. It makes use of Model-Driven Engineering and the UML MARTE profile to move from high level UML models to automatic code generation, for implementing dynamically reconfigurable SoCs. © 2010 IEEE.

关键词： Integrated circuit design

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Dual-core reconfigurable demosaicing engine for next generation of portable camera systems

Dual-core reconfigurable demosaicing engine for next generat...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Zhao, Xin Yi, Ying Erdogan, Ahmet T. Arslan, Tughrul School of Engineering King's Buildings University of Edinburgh Mayfield Road Edinburgh EH9 3JL United Kingdom

ISBN: (纸本)9781424487356

This paper presents a high performance dual-core reconfigurable processor implementation methodology for a demosaicing system that targets next generation camera systems. The implementation methodology is based on dual-core architecture with coarse-grained dynamically reconfigurable processors. The demosaicing system adopts Freeman's algorithm that has been partitioned and mapped onto two customized and tailored heterogeneous processor cores. The demosaicing engine's implementation has been optimized by compilation techniques and special approaches for the targeting processor. Simulation results demonstrate that the resulting demosaicing system provides high throughput reaches up to 241.6Mpixels/s, which represents a 1.82x speedup compared to a single-core implementation. © 2010 IEEE.

关键词： Reconfigurable architectures

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A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

A methodology for precise comparisons of processor core arch...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Rousseau, B. Manet, Ph. Loiselle, I. Legat, J.-D. Vandierendonck, H. Place du Levant 3 B-1348 Louvain-la-Neuve Belgium Ghent University Dept. ELIS HiPEAC St.-Pietersnieuwstraat 41 B-9000 Gent Belgium

ISBN: (纸本)9781424487356

The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels. © 2010 IEEE.

关键词： Very long instruction word architecture

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An in-band reconfigurable network node based on a heterogeneous platform

An in-band reconfigurable network node based on a heterogene...

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2010 conference on design and architectures for signal and image processing, dasip2010

作者： Markert, E. Billich, E. Tischendorf, C. Proß, U. Leibelt, T. Heinkel, U. Knäblein, J. Schneider, A. Chemnitz University of Technology Department of Circuit and Systems Design Germany Alcatel-Lucent Nuremberg Germany BlueWonder Communications GmbH Dresden Germany CoreMountains GmbH Chemnitz Germany

ISBN: (纸本)9781424487356

This paper describes the implementation of a heterogeneous network node as a reconfigurable application based on embedded ASIC technology. The key points of the paper are the distribution of the reconfiguration data in-band over the network and the in-service-reconfiguration of the network node itself. The node consists of a static ASIC part and three reconfigurable various-grained FPGA-like areas included in one chip. The overall goal is to implement a system that can monitor an Ethernet data stream, extracts configuration data marked by the EtherType field in the Ethernet header and updates its functionality during operation time. © 2010 IEEE.

关键词： Reconfigurable architectures

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Camera-based system for tracking and position estimation of humans

Camera-based system for tracking and position estimation of ...

引用

2010 conference on design and architectures for signal and image processing, dasip2010

作者： Hartmann, Robert Al MacHot, Fadi Mahr, Philipp Bobda, Christophe University of Potsdam Department of Computer Science August-Bebel-Str. 89 D-14482 Potsdam Germany

ISBN: (纸本)9781424487356

The human population is getting older and older, as stated by current studies. Because elderly people are at a higher risk of in house accidents there is an increasing need for ambient assisted living systems. These systems should detect accidents or dangerous situations in order to improve the quality of life for these people. The goal of this work is to build a robust and intelligent system which estimates the position of humans using only one camera. The position is used to detect falls and to allow an immediate call for help. The solution is based on a foreground-background-segmentation using Gaussian Mixture Models to first detect people and than analyze their main and ideal orientation using moments. This allows to decide whether a person is staying or lying on the floor. The system has a low latency and a detection rate of 88% in our case study. © 2010 IEEE.

关键词： image segmentation

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Hardware code generation from dataflow programs

Hardware code generation from dataflow programs

引用

2010 conference on design and architectures for signal and image processing, dasip2010

作者： Siret, Nicolas Wipliez, Matthieu Nezan, Jean-François Rhatay, Aimad Lead Tech. Design F-35700 Rennes France IETR INSA Rennes F-35043 Rennes France

ISBN: (纸本)9781424487356

The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software architecture, which improve the computational power but also increase the design complexity and the time to market. New design flows have been developed to help designers in the development of complex architecture. These design flows are often based on the use of languages with a higher level of abstraction. RVC-CAL is a dataflow programming language which provides the good features in this context. An RVC-CAL dataflow program can be compiled to various target software languages (e.g. C, Java, LLVM) with the Open RVC-CAL Compiler (Orcc). In this paper, we will present a new hardware code generator that generates a high-quality portable VHDL code with hierarchical architecture from a RVC-CAL dataflow program in a matter of seconds. The paper explains the underlying principles of the hardware code generator, and presents the results obtained from an Inverse DCT described as an RVC-CAL dataflow program. © 2010 IEEE.

关键词： C (programming language)

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Proceedings of 2021 Workshop on design and architectures for signal and image processing, dasip 2021

Proceedings of 2021 Workshop on Design and Architectures for...

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14th Workshop on design and architectures for signal and image processing, dasip 2021, held jointly with the 16th HiPEAC conference

ISBN: (纸本)9781450389013

The proceedings contain 9 papers. The topics discussed include: architecture of a low latency H.264/AVC video codec for robust ML based image classification;automotive perception system evaluation with reference data obtained by a UAV;convolutional fully-connected capsule network (CFC-CapsNet);DExIE – an IoT-class hardware monitor for real-time fine-grained control-flow integrity;GEGELATI: lightweight artificial intelligence through generic and evolvable tangled program graphs;hardware-software implementation of the PointPillars network for 3D object detection in point clouds;low-power sign-magnitude FFT design for FMCW radar signal processing;multiple transform selection concept modeling and implementation using interface based SDF graphs;and on cache limits for dataflow applications and related efficient memory management strategies.

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